JPS61194873A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61194873A JPS61194873A JP3566685A JP3566685A JPS61194873A JP S61194873 A JPS61194873 A JP S61194873A JP 3566685 A JP3566685 A JP 3566685A JP 3566685 A JP3566685 A JP 3566685A JP S61194873 A JPS61194873 A JP S61194873A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- region
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 230000015556 catabolic process Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims abstract description 9
- 230000002265 prevention Effects 0.000 claims description 13
- 230000006378 damage Effects 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 2
- 230000005591 charge neutralization Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 2
- 230000003449 preventive effect Effects 0.000 abstract 2
- 230000009257 reactivity Effects 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.
従来、半導体装置を構成する電極膜４は、例えば第５図
に示す如く、フィールド酸化膜１を形成した半導体基板
２の素子領域上に電極絶縁膜３を介して形成されている
。而して、電極絶縁膜３の膜厚は、通常８００Ｘ以上と
比較的厚肉に設定されており、電極膜４をプラズマエツ
チング法や反応性イオンエツチング法でノ々ターニング
しても、電極絶縁膜３には何ら支障けなかった。Conventionally, as shown in FIG. 5, for example, an electrode film 4 constituting a semiconductor device is formed on an element region of a semiconductor substrate 2 on which a field oxide film 1 is formed, with an electrode insulating film 3 interposed therebetween. The thickness of the electrode insulating film 3 is usually set to be relatively thick, 800X or more, and even if the electrode film 4 is repeatedly turned by plasma etching or reactive ion etching, the electrode insulating film 3 will not be insulated. Membrane 3 was not affected in any way.
しかしながら、半導体装置の微細化に伴って電極絶縁膜
３も薄肉になり、次のような問題が起きている。すなわ
ち、プラズマエツチングによる電極膜４の・臂ターニン
グは、その際に使用するレジスト膜に電極膜厚の２倍以
上の変換差を考慮しなければならず、電極絶縁膜３を十
分に薄肉にして半導体装置を微細化することができない
。このため、微細化した半導体装置を得るには、電極膜
４のパターニングに反応性イオンエツチングを採用する
必要がある。However, with the miniaturization of semiconductor devices, the electrode insulating film 3 has also become thinner, causing the following problems. In other words, when turning the electrode film 4 by plasma etching, it is necessary to take into account a conversion difference of more than twice the electrode film thickness in the resist film used at that time, and it is necessary to make the electrode insulating film 3 sufficiently thin. It is not possible to miniaturize semiconductor devices. Therefore, in order to obtain a miniaturized semiconductor device, it is necessary to employ reactive ion etching for patterning the electrode film 4.
しかし、反応性イオンエツチングによって電極膜４の・
母ターニングを行うと、電極絶縁膜３が薄肉の場合には
ｉ４ターニングの際に電極絶縁膜３が静電破壊され易い
。このため所望仕様を満した半導体装置を高歩留りで得
ることができない。However, due to reactive ion etching, the electrode film 4
When pre-turning is performed, if the electrode insulating film 3 is thin, the electrode insulating film 3 is likely to be damaged by electrostatic discharge during i4 turning. For this reason, it is not possible to obtain semiconductor devices meeting desired specifications at a high yield.
この問題を解消するために電極絶縁膜３をシリコンナイ
トライド膜と酸化膜の二層構造にして強度を高めること
も考えられる。しかしこのような手段によるものでは、
製造工程が複雑になる問題がある。In order to solve this problem, it is conceivable to make the electrode insulating film 3 have a two-layer structure of a silicon nitride film and an oxide film to increase its strength. However, by such means,
There is a problem that the manufacturing process becomes complicated.
また、従来の半導体装置では、電極絶縁膜３が薄肉の場
合、電極膜４の・リーニング後であっても強い電界を伴
った処理やノイズ信号等によシミ極絶縁膜３の静電破壊
が起き易く、信頼性の高い半導体装置を得ることができ
なかった。In addition, in conventional semiconductor devices, when the electrode insulating film 3 is thin, electrostatic breakdown of the electrode insulating film 3 can occur due to processing with a strong electric field, noise signals, etc. even after the electrode film 4 has been stripped. This problem easily occurred, and it was not possible to obtain a highly reliable semiconductor device.
本発明は、電極膜の下地膜である電極絶縁膜の破壊防止
を達成した半導体装置を提供することをその目的とする
ものである。An object of the present invention is to provide a semiconductor device that achieves prevention of destruction of an electrode insulating film, which is a base film of an electrode film.
本発明は、電極膜及び絶縁膜の所定領域又はその近傍領
域に絶縁膜破壊防止領域を設けて、電極絶縁膜の破壊防
止を達成した半導体装置である。The present invention is a semiconductor device in which an insulating film breakdown prevention region is provided in a predetermined region of an electrode film and an insulating film or in a region in the vicinity thereof, thereby achieving prevention of breakdown of an electrode insulating film.
以下、本発明の実施例について図面を参照して説明する
。第１図（Ａ）は、本発明の一実施例の断面図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1(A) is a sectional view of one embodiment of the present invention.
図中１０は、フィールド酸化膜１ノを形成した半導体基
板である。フィールド酸化膜１１で囲まれた素子領域上
には、８００ｘ以下の薄肉の電極絶縁膜１２が形成され
ている。10 in the figure is a semiconductor substrate on which a field oxide film 1 is formed. On the element region surrounded by the field oxide film 11, a thin electrode insulating film 12 of 800x or less is formed.
電極絶縁膜１２の所定領域には、素子領域に通じる開口
部１３が形成されている。電極絶縁膜１２及びフィール
ド酸化膜１１上には、多結晶シリコン等からなる電極膜
１４が形成されている。つまり、電極膜１４の所定領域
は、開口部１３を介して半導体基板１０に直接接触して
絶縁膜破壊防止領域１５を形成している。An opening 13 communicating with the element region is formed in a predetermined region of the electrode insulating film 12 . An electrode film 14 made of polycrystalline silicon or the like is formed on the electrode insulating film 12 and field oxide film 11. That is, a predetermined region of the electrode film 14 directly contacts the semiconductor substrate 10 through the opening 13 to form the insulation film breakdown prevention region 15 .
このように構成された半導体装置によれば。According to the semiconductor device configured in this way.
第１図の）に示す如く、電極膜１４上の所定領域にレノ
スト膜１６を載置して反応性イオンエツチングによシミ
極膜１４の／ＩＰターニングを行うと、電極膜１４の一
部分が半導体基板１０に接触して絶縁膜破壊防止領域１
５を形成しているので、ａ４ターニングの際に発生した
電荷１１は速やかに基板内に流入し中和される。その結
果、電極絶縁膜１２に過剰な電界が加わるのを阻止して
、静電破壊が起きるのを防止することができろ。As shown in ) of FIG. 1, when the Lenost film 16 is placed on a predetermined area on the electrode film 14 and /IP turning of the stain electrode film 14 is performed by reactive ion etching, a part of the electrode film 14 becomes a semiconductor. Insulating film breakdown prevention region 1 in contact with substrate 10
5, the charges 11 generated during a4 turning quickly flow into the substrate and are neutralized. As a result, it is possible to prevent an excessive electric field from being applied to the electrode insulating film 12 and prevent electrostatic breakdown from occurring.
また、実施例の半導体装置では、電極絶縁膜１２ｆ）１
１Ｘ厚ｔ２００Ｘ、４００１，５ｏｏｌ。Further, in the semiconductor device of the embodiment, the electrode insulating film 12f)1
1X thickness t200X, 4001,5ool.
夫々に設定して絶縁膜破壊に対する製造歩留りを調べた
ところ、第２図に示す如く、８（１前後の値を示したが
、従来の半導体装置では２０〜７０チの製造歩留りであ
ることが実験的に確認された。When we investigated the manufacturing yield with respect to insulation film breakdown with each setting, we found that the manufacturing yield was around 8 (1), as shown in Figure 2, but the manufacturing yield of conventional semiconductor devices is 20 to 70 inches. Confirmed experimentally.
また、実施例の半導体装置では、電極膜１４のｐ４ター
ニング後における強い電界を処理やノイズ信号等の際に
も電極絶縁膜１２の静電破壊の発生は抑制され、極めて
高い信頼性を発揮することが確認された。In addition, in the semiconductor device of the embodiment, the occurrence of electrostatic discharge damage of the electrode insulating film 12 is suppressed even when processing a strong electric field after P4 turning of the electrode film 14, noise signals, etc., and exhibits extremely high reliability. This was confirmed.
なお、絶縁膜破壊防止領域Ｉ５は、第３図に示す如く、
素子領域上に複数６個設け、その各々に所定／ＩＰター
ンの電極膜１８を形成するようにしても良い。また、絶
縁膜破壊防止領域１９は、第４図（Ａ）に示す如く、電
極絶縁膜１２の所定領域をエツチング等により薄肉して
形成しても良い。また、第４図＠）に示す如く、電極絶
縁膜１２の所定領域により選択的にイオン注入或はエツ
チングを施して静電破壊誘発領域２０を形成し、これを
絶縁膜破壊防止領域としても良い。Note that the insulation film breakdown prevention region I5 is as shown in FIG.
A plurality of six electrode films may be provided on the element region, and the electrode film 18 of a predetermined IP turn may be formed on each of the six electrode films. Further, the insulation film breakdown prevention region 19 may be formed by thinning a predetermined area of the electrode insulation film 12 by etching or the like, as shown in FIG. 4(A). Alternatively, as shown in FIG. 4 @), ion implantation or etching may be selectively performed in a predetermined region of the electrode insulating film 12 to form an electrostatic breakdown inducing region 20, which may also be used as an insulating film breakdown prevention region. .
以上説明した如く、本発明に係る半導体装置によれば、
電極絶縁膜の破壊を防止することができるものである。As explained above, according to the semiconductor device according to the present invention,
This can prevent destruction of the electrode insulating film.
第１図（Ａ）は、本発明の一実施例の断面図、同図＠）
は、同実施例の半導体装置の作用を示す説明図、第２図
は、実施例及び従来例の半導体装置の絶縁膜破壊に対す
る良品歩留りを示す特性図、第３図及び第４図（Ａ）
０３）は、本発明の他の実施例を示す断面図、第５図は
、従来の半導体装置の構成を示す断面図である。
１０・・・半導体基板、１１・・・フィールド酸化膜、
１２・・・電極絶縁膜、１３・・・開口部、１４・・・
電極膜、１５・・・絶縁膜破壊防止領域、１６・・・レ
ジスト膜、１７・・・電荷、１８・・・電極膜、１９・
・・絶縁膜破壊防止領域、２０・・・静電破壊誘発領域
。
出願人代理人 弁理士 鈴 江 武 彦第１ 図
（Ａ）
（Ｂ）
第２図
・ＬFigure 1 (A) is a cross-sectional view of one embodiment of the present invention, the same figure @)
2 is an explanatory diagram showing the operation of the semiconductor device of the same example, FIG. 2 is a characteristic diagram showing the yield of non-defective products with respect to insulation film breakdown of the semiconductor devices of the example and the conventional example, and FIGS. 3 and 4 (A)
03) is a sectional view showing another embodiment of the present invention, and FIG. 5 is a sectional view showing the configuration of a conventional semiconductor device. 10... Semiconductor substrate, 11... Field oxide film,
12... Electrode insulating film, 13... Opening, 14...
Electrode film, 15... Insulating film breakdown prevention region, 16... Resist film, 17... Charge, 18... Electrode film, 19.
... Insulating film breakdown prevention region, 20... Electrostatic breakdown induction region. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (A) (B) Figure 2 L
Claims (3)
と、該電極膜及び前記絶縁膜の所定領域又は該電極膜及
び前記絶縁膜の近傍の前記半導体基板上に形成された絶
縁膜破壊防止領域とを具備することを特徴とする半導体
装置。(1) An electrode film formed on a semiconductor substrate via an insulating film, and an insulating film formed on the semiconductor substrate in a predetermined region of the electrode film and the insulating film or in the vicinity of the electrode film and the insulating film. A semiconductor device characterized by comprising a destruction prevention region.
特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the insulation film breakdown prevention region is an electrostatic breakdown inducing region.
請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the insulation film breakdown prevention region is a charge neutralization region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3566685A JPS61194873A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3566685A JPS61194873A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61194873A true JPS61194873A (en) | 1986-08-29 |
Family
ID=12448194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3566685A Pending JPS61194873A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61194873A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129982A (en) * | 1977-04-19 | 1978-11-13 | Matsushita Electric Ind Co Ltd | Production of mos type semiconductor devices |
| JPS55165681A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Preparation of semiconductor device |
-
1985
- 1985-02-25 JP JP3566685A patent/JPS61194873A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53129982A (en) * | 1977-04-19 | 1978-11-13 | Matsushita Electric Ind Co Ltd | Production of mos type semiconductor devices |
| JPS55165681A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Preparation of semiconductor device |
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