JPS61194765A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To fix substrate potential in the vicinity of an N-type resistor stably at minimum supply potential, to inhibit the rise of substrate potential and to prevent the triggering of a parasitic thyristor formed between the N-type resistor and an input transistor by the inhibition of the rise of substrate potential by shaping the N-type resistor and an electrode for a connection with minimum supply potential extending over a P-type semiconductor substrate section. CONSTITUTION:The potential of a P<-> type substrate 1 under an N-type resistor R3 is fixed at approximately stable -Vee potential because -Vee potential connected at one terminal P2 of the resistor is transmitted through a P<++> layer 51 shaped adjoined to the N-type resistor R3 and a P<+> layer 20. That is, even when an input transistor Q1 for an ECL (an emitter coupled logic) is saturated and a parasitic P-N-P transistor Qp is turned ON and currents I0 flow, the I0 is absorbed to a -Vee line connected at one terminal P2 of the N-type resistor R3, the P<-> substrate and an N<-> epitaxial layer under the N-type resistor R3 are not forward-biassed, and a parasitic N-P-N transistor Qn is not turned ON. Another sub-contact region A1 is also shaped to a section extremely near to the N-type resistor R3, thus also resulting in contribution to a stable holding at a -Vee level of substrate potential.

Description

[Detailed description of the invention] (Technical field〕 The present invention relates to a semiconductor integrated circuit device.

[Background technology]

Demand for systems in the diversified market has a strong tendency for higher-speed functions, and ECL (emitter coupled logic) is one of the high-speed logic ICs that has been successful in the market.

The basic circuit configuration of ECL is shown in FIG.

As shown in the figure, ECL consists of npn bipolar transistors Q1. Q2. It is composed of Q3 and resistors R1, R2, and R3. Transistor Q1. Q2 forms a differential pair. The base of one of them (Ql) is connected to the input in, and the base of the other (Q2) is connected to the reference potential vbb. Also, Ql.

Each collector of Q2 is connected to the positive power supply potential (ground potential GND) Vcc via load resistors R1 and R2, respectively. Further, the emitters of Ql and Q2 are commonly connected, and this common connection point is connected to the negative power supply potential VeeK through a transistor Q3 and a resistor R3, respectively. Q3 and R3 constitute a constant current circuit. Q3 is given a constant control voltage Vcs to its base, thereby causing a constant current determined by Vcs and R3 to flow. As a result, Ql and Q2 perform complementary switching operations depending on the voltage applied to the input in. And its operating output o
u t is taken out from each collector Ql and Q2. Here, pl and p2 are terminals of resistor R3, and -10,000 (pl) is connected to the emitter of Q3,
The other side (p2) is the lowest potential, the negative power supply potential -Ve
connected to e. Further, Iee indicates a circuit current flowing through the ECL.

Regarding ECL, for example, "Integrated Circuit Engineering (2)" published by Corona Publishing, Hisayoshi Yanai, Ei 1) Adhesion, June 1970.
Published on May 20th, pages 77-87.

By the way, as shown in FIG. 6, the inventor has determined that Q3 and v
We have considered forming the resistor R3 connected between the ECL and ee of an n-type diffusion layer to reduce its resistance value and increase the amount of constant current flowing through the ECL, thereby increasing the operating speed of the ECL.

FIG. 6 shows a portion of a semiconductor integrated circuit device in which the above-mentioned ECL is formed.

This figure shows the transistor Q1 and resistor R3 in the ECLO shown in FIG. In FIG. 6, 1 is a p- type semiconductor substrate, 2 is a p+ type isolation diffusion layer,
31.32 is an n-type epitaxial layer, 4 is an n+-type buried layer, 5 is a p+"-type diffusion layer for substrate connection, 6 is a p-type base diffusion layer, 7 is an n+-type collector diffusion layer, and 8 is an n+-type emitter. A diffusion layer, 9.10 an n+ type diffusion layer for resistance connection, 11 an oxide film, and 12 a connection electrode.
, E are the collector and base of the transistor Ql.

Each emitter is shown.

Here, the n-type resistance R3 is the n″″ type epitaxial layer 3
2, and is formed using the resistance of the epitaxial layer 32. pl and p2 are terminals of the resistor R3, one side (p2) of which is connected to the lowest potential, the negative power supply potential -Vee, via the connection electrode 12 and wiring on the substrate 1 (not shown). .

In addition, the p-type semiconductor substrate 1 includes, apart from the resistor R3,
The negative side power supply potential V, which is the lowest potential, is applied via the p+ type isolation diffusion layer 2, the p++ type connection diffusion layer 5, and the connection electrode 12.
connected to ee. A indicates the connection point. This connection point A was arranged regardless of the position of the n-type resistor R3.

However, in the above-mentioned semiconductor integrated circuit device, as shown in FIG. 7, when the negative power supply potential -Vee increases to the negative side and its value exceeds a certain value, the circuit current Iee rapidly increases. Furthermore, the increased circuit current Iee is Vee
Even if it returns to the normal range, it does not return to the normal value, and this causes the circuit to go into a thermal runaway state and be destroyed.
The inventor has found that this problem arises.

Furthermore, the above-mentioned problems can be overcome as discussed below.

The inventor has clarified that this is caused by the n-type resistor R3.

That is, as shown in FIG. 6, the n-type epitaxial layer 32 in the region of the n-type resistor R3 and the p-type semiconductor substrate 1
, a parasitic pnp bipolar transistor Qp and a parasitic npn bipolar transistor Qn are generated by the n-type epitaxial layer 31 which becomes the collector region of the npn bipolar transistor Q1, and the p-type base diffusion layer 6 of the transistor Q1, and these two parasitic bipolar transistors Qp and Qn constitute a parasitic thyristor. When the transistor Q1 becomes saturated even temporarily, carriers are injected from the base to the collector, turning on the parasitic PNP transistor Qp, and the current IO flows from the base of the transistor Q1 through the collector to - It starts to flow towards Vee. When current ■0 flows, a voltage drop occurs by IO, Rs due to the existence of the equivalent resistance Rs of the substrate, and the substrate potential rises by this voltage drop,
When this IO, Rs reaches the base-emitter voltage of the parasitic npn transistor Qn, it turns on. As a result, parasitic transistors Qp and Qn shown by thick lines in FIG.
A parasitic thyristor consisting of is triggered. As a result, an abnormal circuit current Iee with hysteresis as shown in FIG. 7 begins to flow.
This was clarified by the inventor. As described above, the present invention was created in the process of increasing the speed of ECL by discovering a failure mode in which abnormal current flows, and in the process of taking countermeasures against this failure mode.

OBJECT OF THE INVENTION The object of the invention occurs when the operating current of the ECL is increased as described above. The object of the present invention is to provide a high-speed ECL that can reliably prevent the generation of parasitic thyristors and can reliably operate over a wide power supply range.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

(Summary of the Invention) A brief overview of typical inventions disclosed in this application is as follows.

That is, when an IC uses an n-type resistor and one end of the n-type resistor is connected to the lowest potential line, the substrate contact region and the contact region of the n-type resistor are integrally formed.
By forming the electrode that connects the type resistor and the negative power supply potential across the substrate part, the substrate potential near the n-type resistor is stably fixed at the lowest power supply potential, suppressing the increase in the substrate potential. This makes it difficult for the parasitic thyristor formed between the n-type resistor and the input transistor to be triggered, thereby achieving the above object.

Embodiments] Representative embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device according to the present invention.

2 shows a planar layout state of the semiconductor integrated circuit device shown in FIG. 1, and the II portion corresponds to the portion shown in FIG.

First, in FIGS. 1 and 2, the transistor Q1 and resistor R3 in the ECL shown in FIG. 3 are shown. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is a p+ type isolation diffusion layer, 31.32 is an n-type epitaxial layer, 4 is an n+ type buried layer, and 5 is a p-type substrate connection layer.
+" type diffusion layer, 6 is a p type base diffusion layer, 7 is an n medium collector diffusion layer, 8 is an n + type emitter diffusion layer, 9 and 10 are n" type diffusion layers for resistance connection, 11 is an oxide film, 12. Reference numeral 12a indicates connection electrodes. Further, C, B, and E indicate the collector, pace, and emitter of the transistor Q1, respectively.

The n-type resistor R3 is formed on an island of the n-type epitaxial layer 32, and is formed for the n'''' type diffusion layer 10. This n-type resistor R3 does not necessarily need to be formed using an n-type diffusion layer, and may be formed using the resistance of an implant resistance layer or epitaxial layer 32. pi and p2 are terminals of the resistor R3, and one side (p2) of the terminal is connected to a connecting electrode 12 made of aluminum or the like.
a and a wiring (not shown) on the substrate 1 to be connected to the negative power supply potential -VeeK, which is the lowest potential.

In addition, the p-type semiconductor substrate l has, apart from the above-mentioned resistor R3,
p+ type separation diffusion layer 2. The negative side power supply potential V, which is the lowest potential, is applied via the p+“ type connection diffusion layer 5 and the connection electrode 12.
connected to ee. A indicates the connection point.

FIG. 3 shows an ECL constructed using the n-type resistor R3 and transistor Q1 shown in FIGS. 1 and 2.

The ECL shown in the same figure is similar to that shown in FIG.
n bipolar transistor Q1. It is composed of Q2°Q3 and resistors R1, R2, and R3. transistor Q
1. Q2 forms a differential pair.

One pace (Ql) is connected to the input in, and the other pace (Q2) is connected to the reference potential vbb. In addition, the collectors of Ql and Q2 are connected to load resistances R1 and R, respectively.
2 to the positive power supply potential (ground potential GND) Vcc
LC connection salel. The emitters of the transistors Q1, Q2, and Q2 are commonly connected, and this common connection point is connected to the negative power supply potential Vee through the transistor Q3 and the resistor R3, respectively. Q3 and R3 constitute a constant current circuit. Q3 is
By applying a constant control voltage Vcs to the pace, a constant current determined by Vcs and R3 flows.

From this K, Ql and Q2 perform complementary switching operations depending on the voltage applied to the input in. The operational output out is taken out from each collector of Ql and Q2. Here, pl.

p2 is the terminal of resistor R3, one of which (pl) is Q
The other (p2) is connected to the negative power supply potential Vee, which is the lowest potential.

Furthermore, Ice indicates the circuit current flowing through the ECL.

Furthermore, in addition to the configuration described above, as shown in FIGS. 1 and 2, K, the negative voltage potential side terminal p2 of the n-type resistor R3,
A connection electrode 12a is formed across the p-type semiconductor substrate 10 portion. In the part of the substrate 1 below the electrode 12a, there is an sp1 type separation diffusion layer 2 and a p++ for connection.
A type diffusion diffusion layer is formed. As a result, a connection point A between the substrate 1 and the negative power supply potential Vee is also formed at the electrode 12a. Note that the connection p++ type diffusion layer may be formed at the same time as the p type base diffusion layer 6 of the transistor Q1.

With the above structure, the potential of the p-type substrate 1 under the n-type resistor R3 is the same as that of the one Vee connected to one end p2 of the resistor.
A p+1 layer 51 whose potential is provided close to the n-type resistor R3
．． It is transmitted through the p+ skin 20 and is fixed at a nearly stable −Vee potential. That is, even if the input transistor Q1 of the ECL is saturated and the parasitic pnp transistor Qp is turned on and current IO flows, this IO is connected to one end P2 of the n-type resistor R3 as shown in Figure 1. As a result, the p-substrate and n-epitaxial layer under the n-type resistor R3 are not forward biased, and the parasitic npn transistor Qn is not turned on. Therefore, the parasitic thyristor does not operate.

Furthermore, as can be seen from FIG. 2, another sub-contact region A1 is also provided very close to the n-type resistor R3, which also contributes to stably maintaining the substrate potential at the -Vee level. There is.

From the above explanation, in this embodiment, a contact region A2 with the -Vee line is provided in the same island region where the n-type resistor R3 is formed, and a contact region A2 with another -Vee line is also provided in the vicinity of the n-type resistor R3. It can be seen that the contact region A1 is provided, and the increase in sub-potential is doubly suppressed.

However, the present invention is not limited to this embodiment, but is effective in keeping the substrate potential stably at the lowest potential so that the voltage between the base and emitter of the parasitic npn (npn) transistor does not exceed a certain level. It goes without saying that many variations are possible from the idea of the present invention of providing a contact region between the lowest potential line and the substrate.

According to the present invention, as shown in FIG. 4, the circuit current Iee generated when the negative power supply potential Vee is increased to the negative side.
Even if the abnormality of V is reduced and Ice increases greatly, V
By lowering ee, it becomes possible to immediately return it to its original normal value. Therefore, it becomes possible to prevent thermal runaway accompanied by circuit destruction.

(Effect) By forming an electrode connecting the n-type resistor and the negative power supply potential side across the substrate portion, the substrate potential near the n-type resistor can be brought closer to the negative power supply potential, This has the effect of making it difficult to trigger the parasitic thyristor formed around the n-type resistor, and making it possible to prevent circuit current abnormalities that occur when the negative side power supply potential is raised to the negative side. is obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

(Field of Application) In the above explanation, the invention made by the present inventor was mainly applied to the ECL technology, which is the field of application that forms the background of the invention, but it is not limited to this, and for example, analog technology, etc. It can also be applied to devices that have at least a diffusion layer resistance, and one end of this resistance is connected to the same minimum electric potential as the substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view of essential parts showing an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a diagram showing a planar layout state of the semiconductor integrated circuit device shown in FIG. 1, and FIG. ECL including the parts shown in Figures and Figure 2
4 is a characteristic diagram showing the relationship between the power supply voltage and current of the ECL shown in FIG. 3, FIG. 5 is a circuit diagram showing the ECL formed in a semiconductor integrated circuit device, and FIG. FIG. 7 is a partial cross-sectional view showing the configuration of a conventional semiconductor integrated circuit device. FIG. 7 is a characteristic diagram showing the relationship between power supply voltage and current of the conventional semiconductor integrated circuit device. Ql, Q2. Q3...npn bipolar transistor constituting ECL (emitter couple or logic), R1, R2... load resistance, R3... n-type resistance,
Vcc (GND)...Positive power supply potential, vbb...
Reference voltage, Vcs...control voltage, in...input, o
ut...output, pl+p2...terminal of n-type resistor R3, 1...p'''' type semiconductor substrate, 2...da-type isolation diffusion layer, 31...32...n-type epitaxial layer, 4
. . . n++ buried layer, 5.51 . . . p+ p+ type diffusion layer for substrate connection 6 .
Collector diffusion layer, 8...n++ emitter diffusion layer, 9,
10... N-type diffusion layer for resistor connection, 11... Oxide film, 12, 12a... Electrode, A... Substrate connection point, Q
p, Qn...parasitic bipolar transistor constituting a parasitic thyristor, Vee...substrate potential near n-type resistor R3. Agent Patent Attorney J, Jll, Kado-1/Mata-
2 Figure 2 Figure 3 ee - Figure 4 Figure 5

Claims (1)

[Claims] 1. A resistor consisting of an npn bipolar transistor and an n-type impurity doped region is formed on a p-type semiconductor substrate, and one end of the p-type semiconductor substrate and one end of the n-type resistor are each connected to a lowest power supply potential. 1. A semiconductor integrated circuit device characterized in that an electrode for connecting the n-type resistor and the lowest power supply potential is formed across the p-type semiconductor substrate portion. 2. The semiconductor integrated circuit device according to claim 1, wherein the npn bipolar transistor and the n-type resistor form a part of ECL (emitter coupled logic).