JPS61193498U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the diagonal line image data generating device according to the present invention, FIG. 2 is a block diagram showing an example of the internal configuration of the dot address correction circuit of the device according to the embodiment, and FIG. 4 is a graph showing an example of the output value of the dot address correction circuit, and FIG. 5 is a graph showing an example of the output value of the dot address correction circuit. FIG. 6 is a diagram showing an example of diagonal line image data obtained by a conventional device. 10... Input buffer register, 20... Dot address correction circuit, 30... Image data generation section,
42...address calculation section, 50...pattern memory,
60...Line battle.

Claims (1)

[Claims for Utility Model Registration] (1) In a diagonal line image data generation device that generates diagonal line image data based on a predetermined font pattern read from a pattern memory, random number generation means that generates a predetermined binary random number pattern; A standard increment value for updating the coordinates indicating the arrangement position in the main scanning direction of the font pattern every main scanning and a binary random number pattern sequentially output from the random number generating means are repeated every main scanning. Diagonal line image data generation comprising: an adding means for adding; and a diagonal image generating means for generating diagonal line image data by sequentially shifting the font pattern read from the pattern memory in the main scanning direction based on the addition result of the adding means. Device. (2) The random number generation means is a predetermined bit adder that repeatedly adds a predetermined set value, and the binary random number pattern is obtained from the carry signal output from the adder. The diagonal line image data generator described in item 1).