JPS61192582A - Ink jet recording apparatus - Google Patents

Abstract

PURPOSE:To prevent the filling of two buffers of transmission exclusive LSI, by providing a buffer circuit to the front stage of the receiving buffer of transmission exclusive LSI and changing the receiving speeds of the transmission exclusive LSI and the buffer circuits during the processing and non-processing of apparatus internal control by an ink jet recording apparatus. CONSTITUTION:CPU1 takes in each signal of PIA4 performs not only internal processing such as the control of ink density or the checking of the abnormality of each part of the apparatus but also the giving and receiving of the printing data with external CPU through transmission exclusive LSI (hereinafter referred to as UART). When the internal processing of an ink jet recording apparatus is not performed, CPU1 can instantaneously correspond to data take-in demand from UART5. When the internal processing is performed, because CPU1 can not correspond to the data take-in demand from UART5, the transmission data from external CPU is successively transmitted to external buffers 8, 9 in series at the same speed as the transmission speed from from external CPU to prevent the filling of receiving buffers of UART5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a transmission means for transmitting and receiving a group of information printed by an inkjet recording apparatus to and from an external device, and particularly relates to reception control of an inkjet recording apparatus.

[Background of the invention]

In recent years, serial transmission, which aims to reduce the number of transmission lines, has been widely used as a means of transmitting information, and there are many types of LSIs dedicated to serial transmission on the market.

What these LSIs have in common is that they employ a double buffer system in which there are two buffers each for transmission and reception within the LSI. The purpose of the V.21 buffer system is to reduce the load on the CP TJs on the transmitting side and the receiving side, and to smoothly exchange information.

When transmitting information, the receiving side generally concentrates on receiving after confirming the transmission request from the sending side.
By effectively utilizing the heavy buffer system, it is possible to transmit information at a speed close to the processing speed limit of the CPU. In addition, rounding is possible so that the receiving side can concentrate on receiving the transmitted information from the transmitting side.

However, with inkjet recording devices, it is necessary to process and execute processes such as managing the ink droplet creation status, managing ink density, and checking for abnormalities in each department of the device at regular intervals. ), it is impossible to concentrate on reception since the above-mentioned processes are performed at regular intervals. This places a limit on the reception speed (transmission speed) when the inkjet recording apparatus receives information (print data) from an external CPU. That is, during the time when the CP Tl of the inkjet recording device is performing internal control processing, information (print data) from the external CP TJ is stored in the two reception buffers dedicated to transmission, I and 81.
The transmission speed must be such that the storage is not completed. When the information (print data) from the external CPU is completely stored in the two reception buffers of the transmission-only L8I, the transmission-only L8I
An error message interrupts the CPUK of the inkjet recording apparatus, informing that there is a problem with information transmission, and subsequent transmission becomes meaningless.

Regarding the double buffer system of LSI dedicated to serial transmission, Appendix C (General Purpose Asynchronous Transmitter/Receiver), "Revised Computer Data Communication Technology" by John E. McNamara, translated by Hiroyuki Watabe, published on July 15, 1980. It is described in.

Japanese Patent Publication No. 58-24277 is an example of internal control of an inkjet recording apparatus at regular intervals.

[Purpose of the invention]

An object of the present invention is to provide an inkjet recording apparatus capable of high-speed transmission by increasing the transmission speed limit to the inkjet recording apparatus when viewed from the sending side.

[Summary of the invention]

As mentioned in the background section of the present invention, inkjet recording devices, even when receiving information from an external CPU,
It is necessary to manage the inside of the inkjet recording apparatus at regular intervals. If there is a time delay for storing information in the receive buffer of the transmission-only LSI for the time it takes to process this internal management, the two buffers of the transmission-only LSI will not become full, and information transmission will be hindered. It is thought that this will no longer occur.

In order to minimize the above-mentioned time delay, the present invention provides a transmission-only L
This paper proposes a ``multiple buffer system'' that provides the same effect as expanding the receive buffer by providing a buffer circuit before the SI receive buffer.

Furthermore, inkjet iIP! The sickle device changes the reception speed of the transmission-only LSI and the buffer circuit between processing and non-processing of internal management of the device, thereby preventing the two buffers of the transmission-only LSI from becoming full.

[Embodiments of the invention]

An embodiment of the present invention will be explained with reference to FIG.

CP TJ 1 connects to ROM2゜RA via the pass line.
This is a unit that reads and executes programs and data from M3. ROM2H read-only memory, RAM3t
1! It is readable and writable memory.

CP the recording status of PIA4i inkjet recording device
6 is a friend input/output element that reports to TJ 1.

Capture each signal of CPUIHPIA4 at regular intervals,
It performs internal processing such as managing the ink particle creation status, managing ink density, and checking for abnormalities in each part of the device, and also performs internal processing such as managing the ink particle creation status, managing ink density, and checking for abnormalities in each part of the device.
Exchanges print data with PU.

UART5H As mentioned above, there are two reception buffers 6.
It has a double buffer structure with 7.

External buffers 8, 9, and 10 extend the receive buffer 6.7 of rJAR, T5. Print data from the external CPU is transmitted to the OAR and T5 by parallel transmission from the external buffer 10 to the external buffer 9 and serial transmission from the external buffer 9 to the external buffer 8. The oscillation circuit 11 is T
J enter R'I'5. Generates basic clock CPO to be supplied to external buffer 8.9.10. Frequency dividing circuits 12, 13.
14rj: clocks CPI, CP2 . In the rounding to create CP3, the frequency divider circuit 12.13H has a fixed frequency division ratio and the frequency division circuit 14 has a variable frequency division ratio. The reason for making the division ratio of the frequency dividing circuit 14 variable will be described in detail later.

The timer circuit 15 is a circuit that detects the falling edge (start bit shown in FIG. 3) of the beginning of the print data from the external CP N and turns on the output for a certain set time. , is set according to the data format and transmission speed shown in FIG. The AND circuit 16 includes the output T of the timer circuit 15 and the output CP of the frequency divider circuit 12.
3 is input, and its output CP31j: external buffer 10
is input. The role of this AND circuit 16
A clock pulse CP for the external buffer 10 to take in one unit (one data format) of print data from
aA, and the output T of the timer circuit 15
If the clock pulse CPaA is turned off, the supply of the clock pulse CPaA is stopped.

UARTS&! Clock pulse CP from frequency dividing circuit 14
Print data from the external buffer 8 is taken into the reception buffer 6 using I as a reference. Figure 2 shows the time chart. When the falling edge (start bit) of the TJ4R, Tsa print data signal is detected, the basic clock CPI starts counting from that point, and generally the level of the print data signal (H or L) is detected at the falling edge of the 8th clock. ), and thereafter execute the capture while checking the print data signal every 16 clocks. FIG. 3 shows an example of the format of transmission data used in serial transmission.

A transmission take has a start bit (L level) at the beginning, a stop bit (H level) at the end, and data bits and parity bits between the bits.

As mentioned above, since the start bit tfL and the stop bit are at H level, it is possible to recognize from the fall of the print data signal that the print data signal has been transmitted from the external CPU through the UART5. In addition, each bit of the data format shown in Figure 3 is generally configured with a cycle that is 16 times the basic clock CPI shown in Figure @2, and as described above, <OAR, T5 is the 8th clock of the basic clock CPI. The reason why the printer checks the level of the print data signal and captures it at the 16th clock is based on the above reason.
.

Next, the process (operation of each circuit) until the UART 5 receives the print data signal from the external CPU will be explained.

When a print data signal is issued from the external CPU, the timer circuit 15 detects the beginning (falling edge) of the print data signal as described above, and outputs the output T for a certain set period of nine hours.
N, and the output T is input to the input terminal of the AND circuit 16. The basic clock CPO from the oscillation circuit 11 and the clock CP3 via the frequency dividing circuit 12 are input to other input terminals of the AND circuit 16. The AND circuit 16 outputs the clock CP3 from the frequency dividing circuit 12 as clock CPaA to the external buffer 10 only while the output T of the timer circuit 15 is ONL.
I Take in the print data signal from the external CP Tl internally according to the clock CPaA. As mentioned above, the 08 hours of the output T of the timer circuit 15 is set according to the data format and transmission speed, and corresponds to one unit of the print data signal.
That is, it is set to remain ON while the external buffer 10 takes in the data from the start bit to the stop bit shown in FIG. Therefore, at 9 o'clock when the second print data signal is issued from the external CP TT, the timer circuit 15 starts operating again and takes in the second print data signal into the external buffer 10 through the same process as described above.

When the capture of the print data signal into the external buffer 10 is completed, the output T of the timer circuit 15 is turned off, and parallel transmission of the print data signal from the external buffer 10 to the external buffer 9 is executed in synchronization with this timing. The output Tt- of the timer circuit is used as the next signal that the external buffer 9 takes in the print/character data signal from the external buffer 10, and the parallel transmission is performed at the timing when the output T turns OFF.

The print data signal taken into the external buffer 9 is sent to the external buffer 8 according to the output clock CP2 from the frequency dividing circuit 13.
is transmitted in series.

To summarize the operations described above, the timer circuit 15 divides the print data signal from the external CPU into one data format unit and captures it into the external buffer 10, and transmits it to the external buffer 9 external buffer BrJART5. .

Next, we will discuss the relationship between the internal processing of the inkjet recording device and the transmission speed of the print data signal (transmission data) in the fourth section.
This will be explained with reference to FIG. FIG. 4 shows a case where the transmission data transmission time T3 is longer than the internal processing time Tz of the inkjet recording apparatus. In the case of the conditions shown in FIG. 4, if the reception buffer 6 of the UART 5 has not completed receiving the transmission data from the external CPU, no problem will occur if the reception continues. Also, even if the inkjet recording device completes the acquisition of transmission data from the external CPU to the reception buffer 6 of the UART 5 during internal processing, the transmission data dUAR, T5 is automatically transmitted from the reception buffer 6 to the reception buffer 7. Since the receiving buffer 6 becomes empty, it is now possible to receive the second transmission data. Under the conditions shown in FIG. 4, the internal processing of the inkjet printing apparatus is completed by the time the receiving buffer 6 of the rJA standard 5 completes receiving the second transmission data. Both will not become full and the above-mentioned overrun error will not occur. Therefore, under the conditions shown in Figure 4, the external CP
The double buffer structure of the UART 5 can be effectively used to take in the transmission data from U, and the transmission data can be taken in without interfering with the internal processing of the inkjet recording apparatus.

However, as shown in FIG. 5, the transmission speed of the transmitted data is fast compared to the internal processing time T2 of the inkjet recording apparatus, and in particular, two or more units of transmitted data are transmitted from the external CPU within the internal processing time T2. In this case, when both the TJxRTs receive buffers 6 and 7 become full, the above-mentioned overflow error will occur, which will impede transmission data exchange with the external CPIJ.

FIG. 6 shows the transmission data acquisition status of the reception buffer 6.7 of the UART5 under the conditions shown in FIG.
The figure shows the transmission data acquisition status of the reception buffer 6.7 of the UART 5 under the conditions shown in FIG.

In the present invention, even under the conditions shown in FIG. 5, the receiving speed of the UART 5 is changed between when the internal processing of the inkjet recording apparatus is being executed and when it is not being executed so that the transmission data can be exchanged smoothly. .

The operation will be explained below.

The process until the UATLT 5 receives the data transmitted from the external W15 CPU has already been described, so it will be omitted here.

(1) Executing internal processing of the inkjet recording device (
2) Internal processing of the inkjet recording device is not being executed [
cpo:cpt=t:t CPO:CP2=16: I CPO:CF2 (CPaA)=32: In the case of 1 (2), that is, when the internal processing of the inkjet recording device is not being executed, CF2:CP3=2= It was set to 1. This allows transmission data from the external CPU to be transferred to external buffer 1.
0 is taken in and transmitted in parallel to the external buffer 9, the external buffer 9 is transferred at twice the transmission speed from the external CPT 7.
→Serial transmission to 8UART5. At 9 o'clock, when the external buffer 10 completes taking in the second transmission data, the transmission of the first transmission data H1UAR, T5 into the reception buffer 6 is completed. The situation is shown in graves 1 to 44 in Figure 8. That is, when the internal processing of the inkjet recording apparatus is not being executed, the external buffer 8, 9.1 according to the present invention
In order to suppress the transmission time delay due to the acquisition of transmission data to 0, the transmission speed is made to differ.

Next, in the case of (1) above, that is, when the internal processing of the inkjet recording device is being executed, CF2:CP3=1:1
Then, all transmission data from the external CPU is serially transmitted to the external buffer 8.9 at the same speed as the transmission speed from the external CPU, and a time delay is applied so that the reception buffer 6.7 of the UA r5 does not become full. to prevent the overrun error from occurring. The block diagram of each buffer shown at 45 to 48 in FIG. 8 shows the worst case, where the start of execution of internal processing of the inkjet printing apparatus and a request to take in data from the rJART 5 occur simultaneously. The part surrounded by the dotted line in FIG. 8 is the external buffer 8°9.10 according to the present invention.
Even when the internal processing of the inkjet printing apparatus is being executed, the receiving buffer 6.7 of Ul(,'r5 will not become full, and therefore no overrun error will occur. As a result, as shown in FIG. Even in the case of conditions, external C
Transmission data from the PU can be smoothly sent and received. Started executing the internal processing of the inkjet recording device, and then checked whether the internal processing was completed or not.H1P
It can be detected by the IRQ signal of IA4, and this IR,
The Q signal is taken into the frequency dividing circuit 14, and the division ratio is changed, that is, the transmission speed is changed.

The operations of the external buffers 8, 9, and 10 and the above-mentioned operations for switching the transmission speed according to the present invention can be summarized as follows.

(1) When the internal processing of the inkjet recording device is not being executed, CP Tyl can immediately respond to data import requests from UAR and T5, and transmit data from external CP Ti as early as <tJ4RTs. Set the serial transmission speed between external buffers 8 and 9 to twice the transmission speed from the external CPU.

(2) When the internal processing of the inkjet recording device is being executed, the CPU 1 responds to the data import request from the UA T5 and transfers the transmitted data from the external CPU to the external buffer 8.9. Sequential serial transmission is performed at the same speed as the transmission speed from the CPU to prevent the reception buffers 6.7 of TJ/LR and T5 from becoming full.

〔Effect of the invention〕

According to the present invention, while the inkjet recording apparatus is performing internal processing such as managing the ink droplet creation status, managing the ink density, and checking for abnormalities in each section of the inkjet recording apparatus, Even if two or more units of print data are transmitted from an external CPU, there is no problem in sending and receiving print data, and the transmission speed to the inkjet recording device from the sending side can be increased, supporting high-speed transmission. can.

Further, according to the present invention, there is no need to add a CPU dedicated to transmission control, and it is possible to prevent the program from becoming complicated. The control of the external buffer and frequency dividing circuit of the present invention can be handled entirely by hardware, and there is no increase in processing in the CPU of the inkjet recording apparatus.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the inside of an inkjet recording apparatus according to the present invention, FIG. 2 is a time chart of reception control of HUAR, T, FIG. 3 is a diagram showing an example of a data format used in serial transmission, and FIGS. Fig. 5 shows the relationship between the internal processing time of the inkjet recording device and the transmission speed of the transmitted data, Figs. 6 and 7 show the data acquisition status of the reception buffer in the UART, and Fig. 8 shows the relationship between the internal processing time of the inkjet recording device and the transmission speed of the transmitted data. FIG. 2 is a diagram illustrating data acquisition status of a reception buffer in the UART and an external buffer. 1...CPU, 2...ROM, 3...RAM, 4
...Pl. 5...Transmission LSI (UλRT), 6...Reception buffer (UAR, inside T), 7...Reception buffer (UA
RT internal χ8.9.10...external buffer, 11...
Oscillation circuit, 12.13.14... Branch circuit, 15...
・Timer time Figure 1 II /Z Figure 2 fJ30'! J6 figure 70th 80th

Claims (1)

[Claims] While information is exchanged with the outside via a single- or double-buffered UART, the device internally manages the ink droplet creation status and checks for abnormalities in each department at regular intervals. process,
In an inkjet recording device that has a built-in CPU, a buffer circuit is provided before and after the UART reception buffer, and information from the outside is temporarily stored in this buffer circuit even when the CPU is performing processing inside the device. An inkjet recording device characterized by avoiding a buffer becoming full. 2. In claim 1, a clock circuit that changes the speed at which the UART and the added buffer circuit receive data from the outside, depending on whether the CPU is performing internal processing or exchanging information with the outside. An inkjet recording device comprising: