JPS61190650A - Dma transfer possibility/impossibility reporting system - Google Patents

Dma transfer possibility/impossibility reporting system

Info

Publication number
JPS61190650A
JPS61190650A JP3102285A JP3102285A JPS61190650A JP S61190650 A JPS61190650 A JP S61190650A JP 3102285 A JP3102285 A JP 3102285A JP 3102285 A JP3102285 A JP 3102285A JP S61190650 A JPS61190650 A JP S61190650A
Authority
JP
Japan
Prior art keywords
dma
transfer
unit part
host computer
image information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3102285A
Other languages
Japanese (ja)
Inventor
Toshiro Yagi
矢儀 俊郎
Akio Munakata
昭夫 宗像
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3102285A priority Critical patent/JPS61190650A/en
Publication of JPS61190650A publication Critical patent/JPS61190650A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To perform DMA transfer efficiently by receiving a DMA transmission transfer permitting signal from an IP unit part, which is connected between a facsimile terminal and a host computer, by a communication processor after the end of DMA transmission and DMA-transferring picture information of the following page. CONSTITUTION:A connecting device between the host computer and the facsimile terminal consists of the communication processor and the IP unit part, and this unit part is provided with a DMA transmission transfer permitting signal generating means. Every one block consisting of parts F, M, and L of one-page components of picture information stored in the communication processor is transmitted to the IP unit part and is expanded and developed, and thereafter, a following page indicating command PMC is transmitted from the host computer to the IP unit part to store compressed picture information in the idle area of an image memory, and a DMA reception transfer request signal DR from the communication controller is received by the unit part, and the compressed information is transferred following a DMA reception transfer permitting signal PWK.

Description

【発明の詳細な説明】 〔概要〕 本発明は複数ファクシミリ端末へ画情報を伝送するため
、ファクシミリ接続装置を介して行うとき、イメージメ
モリに一旦格納し、圧縮・伸張・DMA転送などの処理
がなされ、そのときDMA転送の可否を通知し、転送制
御を有効に行う方式に関する。
[Detailed Description of the Invention] [Summary] In order to transmit image information to multiple facsimile terminals, the present invention temporarily stores it in an image memory and processes such as compression, expansion, and DMA transfer when transmitting image information to multiple facsimile terminals via a facsimile connection device. The present invention relates to a method for effectively controlling transfer by notifying whether DMA transfer is possible or not at that time.

産業上の利用分野〕 本発明はホスト計算機の制御により、複数のファクシミ
リ端末へ画情報を伝送するとき使用するファクシミリ接
続装置内でDMA転送を行う場合に転送制御を有効に行
う方式に関する。
INDUSTRIAL APPLICATION FIELD The present invention relates to a method for effectively controlling transfer when performing DMA transfer within a facsimile connection device used to transmit image information to a plurality of facsimile terminals under the control of a host computer.

[従来の技術] ファクシミリ端末ヘデータを送出するとき第2図に示す
構成が採用されている。第2図においてlはホスト計算
機、2はファクシミリ接続装置を全体的に示すもの、3
は回線接続装置NCU、4は交換網NW、51 、 5
2−=5 nはファクシミリ端未FAX、20は通信処
理装置LCAの1つを示し、この例では他に3個の同様
な通信処理装置を有する。符号21以下のものは通信処
理装置20における各構成部を示し、21はホスト計算
機1とのインクフェース、22はマイクロプロセッサM
PU、23は主記憶部MM、24はファクシミリ端末5
1等とのインタフェース、25はバッファ、26はDM
A転送制御部、27はIPユニット部を全体的に示す。
[Prior Art] When sending data to a facsimile terminal, the configuration shown in FIG. 2 is employed. In Fig. 2, l indicates the host computer, 2 indicates the facsimile connection device as a whole, and 3
is line connection device NCU, 4 is switching network NW, 51, 5
2-=5 n indicates a facsimile terminal FAX, 20 indicates one communication processing device LCA, and in this example, there are three other similar communication processing devices. The numbers 21 and below indicate each component in the communication processing device 20, 21 is an ink interface with the host computer 1, and 22 is a microprocessor M.
PU, 23 is the main memory section MM, 24 is the facsimile terminal 5
Interface with 1st class, 25 is buffer, 26 is DM
A transfer control section 27 generally indicates the IP unit section.

IPユニット部部子7おいて、31はマイクロプロセッ
サμP、32は主記憶部MEM、33はCG変換器、3
4は伸張・圧縮器、35はメモリ制御器、36はイメー
ジメモリを示している。ホスト計算fitから各ファク
シミリ端末へ同一画情報を順次送出する場合、1頁の画
情報が第1ブロツク(F)、第2ブロツク(M)、第3
ブロツク(L)のようにブロック分けされているとして
、ファクシミリ接続装置3内の主記憶部23(MM)に
一旦格納する0次に該Iブロックから読出し、DMA転
送方式でIPユニット部部子7画情報を転送する。第3
図はブロック毎の転送とIPユニット部部子7主記憶部
32・イメージメモリ36における格納・読出し状況を
説明する図である。即ち通信処理装置20(LCA)の
側からはDMA送信要求信号D−Wに続き第1ブロツク
 (F)が送出される。(太い矢印41)次にDMA終
了信号D−EとDMA送信要求信号D−Wに続き、第2
ブロツク(M)が送出される。(太い矢印42゜)そし
てDMA終了信号D−EとDMA送信要求信号D−Wに
続き第3ブロツク(L)(太い矢印43)とDMA終了
信号D−Eが送出される。主記憶部32に第3ブロツク
(L)まで格納されると、マイクロプロセッサ31の制
御により、伸張・圧縮器34が起動され、情報はイメー
ジメモリ36に伸張、展開される。
In the IP unit section 7, 31 is a microprocessor μP, 32 is a main memory MEM, 33 is a CG converter, 3
4 is an expansion/compressor, 35 is a memory controller, and 36 is an image memory. When the same image information is sequentially sent from the host calculation fit to each facsimile terminal, the image information of one page is sent to the first block (F), the second block (M), and the third block.
Assuming that the data is divided into blocks like block (L), the 0 block is temporarily stored in the main memory 23 (MM) in the facsimile connection device 3, and then read from the I block and transferred to the IP unit section 7 using the DMA transfer method. Transfer image information. Third
The figure is a diagram illustrating the transfer of each block and the storage/reading situation in the main storage section 32 and image memory 36 of the IP unit part 7. That is, the first block (F) is sent from the communication processing device 20 (LCA) following the DMA transmission request signal D-W. (Thick arrow 41) Next, following the DMA end signal D-E and the DMA transmission request signal D-W, the second
Block (M) is sent out. (Thick arrow 42°) Then, following the DMA end signal DE and DMA transmission request signal D-W, a third block (L) (thick arrow 43) and a DMA end signal DE are sent out. When the third block (L) is stored in the main memory 32, the decompressor 34 is activated under the control of the microprocessor 31, and the information is decompressed and developed in the image memory 36.

伸張、展開終了のとき、次頁指示コマンドPMCがホス
ト計算機からIP%ニット部27のマイクロブ(・セッ
サ31μPに向けて送出される。このコマンドはIPユ
ニット部部子7おいて処理すべき画情報の頁が最終頁で
あるか、次頁があるかの情報、画素密度を変える必要が
あるかどうか等をを指示する。マイクロプロセッサ31
μPはここでイメージメモリ37内に展開されている1
頁目の画情報を読出し、伸張・圧縮器34の圧縮処理部
を起動し、第3図の右側中段に記載のように圧縮された
画情報をイメージメモリ37内の空き領域に格納する。
When decompression and expansion are completed, a next page instruction command PMC is sent from the host computer to the microb (processor 31μP) of the IP% knit section 27. The microprocessor 31 instructs whether the page is the last page, whether there is a next page, whether the pixel density needs to be changed, etc.
μP is 1 expanded in the image memory 37 here.
The image information of the page is read out, the compression processing section of the expansion/compressor 34 is activated, and the compressed image information is stored in the free area in the image memory 37 as shown in the middle row on the right side of FIG.

次にホスト計算機はIPユニット部部子7対しDMA受
信転送要求信号D−Rを送出するので、マイクロプロセ
ッサ31μPの制御により、イメージメモリ内の画情報
が1ブロツクずつ、通信処理装置の主記憶装置23に転
送される。DMA終了信号D−Eと、DMA受信転送要
求信号D−Rとは、画情報の転送毎に繰り返し送出され
ている。
Next, the host computer sends a DMA reception transfer request signal D-R to the IP unit section 7, and under the control of the microprocessor 31μP, the image information in the image memory is transferred one block at a time to the main memory of the communication processing device. Transferred to 23. The DMA end signal D-E and the DMA reception transfer request signal D-R are repeatedly sent every time image information is transferred.

[発明が解決しようとする問題点] IPユニット部のイメージメモリ36の容量は1頁の画
情報について伸張と圧縮したものを両者格納できる量を
準備するため、比較的大きなものを必要とする。且つD
MA転送の処理は送信・受信を順次に行うから、処理速
度はあまり速くはなかった。
[Problems to be Solved by the Invention] The capacity of the image memory 36 of the IP unit section is required to be relatively large in order to store both expanded and compressed image information for one page. And D
Since MA transfer processing involves sequential transmission and reception, the processing speed was not very fast.

本発明の目的はイメージメモリ36について大容量のも
のを使用せず、効率良く使用でき、且つ高速処理ができ
るようなりMA状態通知方式を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an MA status notification system that does not use a large capacity image memory 36, can be used efficiently, and can perform high-speed processing.

[問題点を解決するための手段] IPユニット部の圧縮された画情報について、その1ブ
ロツクをホスト側へ送出したとき、IPユニット部はイ
メージメモリ内に空き領域ができることを認識すると、
DMA送信転送可能信号(R−W−K)をホスト側へ送
信する。通信処理装置はその信号を受信して、1頁の第
1ブロツクについて受信をし、ついで2頁の当初ブロッ
ク送信をDMA転送方式で行う。
[Means for solving the problem] When the IP unit unit recognizes that a free space is created in the image memory when one block of compressed image information is sent to the host side,
Sends a DMA transmission transfer enable signal (R-W-K) to the host side. The communication processing device receives the signal, receives the first block of the first page, and then transmits the first block of the second page using the DMA transfer method.

[作用〕 通信処理装置とIPユニット部はイメージメモリ内の空
き領域に関する情報を得ることができるため、その空き
領域を利用して、DMA転送を効率良く行うことができ
る。
[Operation] Since the communication processing device and the IP unit can obtain information regarding the free space in the image memory, the free space can be used to efficiently perform DMA transfer.

[実施例] 第1図は本発明の実施例としてのDMA送・受信転送動
作に関する説明図である。また第1図に示す処理動作を
行う構成は、従来の第2図と同様であり、第2図のイメ
ージメモリ27側にDMA送信転送可能信号を発する手
段として所定のプログラムを組込んだマイクロプロセッ
サ31を具備している。即ち第2図に示されるハードウ
ェアは、従来と略同様であり、内蔵のプログラムが異な
るため、動作も第3図に示す処理動作の処理動作の中段
以降において変わってくる。
[Embodiment] FIG. 1 is an explanatory diagram regarding DMA transmission/reception transfer operations as an embodiment of the present invention. The configuration for performing the processing operation shown in FIG. 1 is the same as the conventional one shown in FIG. It is equipped with 31. That is, the hardware shown in FIG. 2 is substantially the same as the conventional one, but since the built-in program is different, the operation also changes after the middle stage of the processing operation shown in FIG. 3.

即ちホスト計算機からの1頁画情報についてイメージメ
モリ37に圧縮・格納されたとき、通信制御装置からD
MA受信転送要求信号D−Rをイメージメモリ側へ送信
し、マイクロプロセッサ31からはDMA送信転送可能
信号(R−W−K)をDMA受信転送要求信号D−Rの
準備ができた旨の信号に引続き送出する。これら信号は
DMA転送が所定のとおり動作し、圧縮された情報を通
信制御装置側へ送出すれば、その空き領域となった場所
へ新たにDMA送信転送の書込み可能であることを意味
する。そのため、R−W−に信号を受信した通信処理装
置側では、次に1頁の圧縮情報第1ブロツク(F)(ハ
ツチング矢印51)を受信する。その後通信処理装置側
からはDMA終了信号D−Eを送出し、次の2頁画情報
の当初ブロック0を送出する。(太い矢印44゜)以後
DMA送信終了信号D−E DMA送信転送要求信号D−R DMA送信転送可能号R−W−K が前述のように送受信され、ハツチング矢印52のよう
に第2ブロツク(M)が通信処理装置側で受信される。
That is, when one page image information from the host computer is compressed and stored in the image memory 37, the communication control device
The MA reception transfer request signal D-R is sent to the image memory side, and the microprocessor 31 sends a DMA transmission transfer enable signal (R-W-K) as a signal indicating that the DMA reception transfer request signal D-R is ready. will continue to be sent. These signals mean that if the DMA transfer operates as prescribed and the compressed information is sent to the communication control device side, it is possible to write a new DMA transmission transfer in the vacant area. Therefore, the communication processing device that has received the RW- signal next receives the first block (F) of compressed information of one page (hatched arrow 51). Thereafter, the communication processing device sends out a DMA end signal D-E, and sends out the initial block 0 of the next two-page image information. (Thick arrow 44°) After that, the DMA transmission end signal D-E, DMA transmission transfer request signal D-R, and DMA transmission transfer enable signal R-W-K are transmitted and received as described above, and as shown by the hatched arrow 52, the second block ( M) is received by the communication processing device.

その後2頁の画情報の以後のブロックFl、Llがイメ
ージメモリ側へ送信され、また1頁の画情報の第3ブロ
ツク(L)が通信処理装置側で受信される。
Thereafter, the subsequent blocks Fl and Ll of the image information of the second page are transmitted to the image memory side, and the third block (L) of the image information of the first page is received by the communication processing device side.

[発明の効果] このようにして本発明によると、イメージメモリ部にお
けるメモリ容量を有効に使用できるから、準備するメモ
リを格別大容量とすることなく、且つ動作速度の速い処
理が達成できる効果を有する。
[Effects of the Invention] In this way, according to the present invention, since the memory capacity in the image memory section can be used effectively, it is possible to achieve the effect of achieving high-speed processing without requiring a particularly large capacity of the memory to be prepared. have

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の動作説明図、第2図は本発明
及び従来のファクシミリ端末とホスト計算機間の画情報
送受信接続構成図、第3図は従来の動作説明図である。 1−ホスト計算機 2−−−ファクシミリ接続装置 51.52−−−ファクシミリ端 末20−−−通信処理装置 23・−−−主記憶部 27−I Pユニット部 31−マイクロプロセッサ 32・−主記憶部 36・・−イメージメモリ 特許出願人    富士通株式会社 代理人     弁理士 鈴木栄祐 LCAメモリ                IP部
 メモリ第1図
FIG. 1 is an explanatory diagram of the operation of an embodiment of the present invention, FIG. 2 is a diagram of the configuration of the image information transmission/reception connection between a facsimile terminal and a host computer according to the present invention and a conventional one, and FIG. 3 is an explanatory diagram of the conventional operation. 1-Host computer 2--Facsimile connection device 51.52--Facsimile terminal 20--Communication processing device 23---Main storage section 27-IP unit section 31--Microprocessor 32--Main storage section 36... - Image memory patent applicant Fujitsu Ltd. agent Patent attorney Eisuke Suzuki LCA memory IP department Memory Figure 1

Claims (1)

【特許請求の範囲】 複数のファクシミリ端末(51)(52)−−−との接
続を切換える交換網(4)と、ホスト計算機(1)との
間に接続されたファクシミリ接続装置(2)を有し、該
ファクシミリ接続装置(2)は通信処理装置(20)と
IPユニット部(27)とを具備し、更に通信処理装置
(20)はホスト計算機(1)からの画情報を一時格納
する主記憶部(23)と、該主記憶部(23)に格納さ
れた画情報をDMA転送によりIPユニット部(27)
へ格納させるDMA転送制御部(26)とを具備し、D
MA転送を行う方式において、IPユニット部(27)
にはDMA送信転送可能信号を発する手段(31)を具
備し、 通信処理装置(20)は前ページの画情報をDMA送信
終了後に、IPユニット部からのDMA送信転送可能信
号を受信してから、次ページの画情報をDMA転送する
こと を特徴とするDMA転送可否通知方式。
[Claims] A facsimile connection device (2) connected between a switching network (4) for switching connections with a plurality of facsimile terminals (51) (52) and a host computer (1). The facsimile connection device (2) includes a communication processing device (20) and an IP unit section (27), and the communication processing device (20) temporarily stores image information from the host computer (1). The main memory section (23) and the image information stored in the main memory section (23) are transferred to the IP unit section (27) by DMA transfer.
and a DMA transfer control unit (26) for storing data in the D
In the method of performing MA transfer, the IP unit section (27)
is equipped with means (31) for emitting a DMA transmission transfer enable signal, and the communication processing device (20) transmits the image information of the previous page after the DMA transmission is completed and after receiving the DMA transmission transfer enable signal from the IP unit section. , a DMA transfer permission notification method characterized by DMA transfer of image information of the next page.
JP3102285A 1985-02-19 1985-02-19 Dma transfer possibility/impossibility reporting system Pending JPS61190650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3102285A JPS61190650A (en) 1985-02-19 1985-02-19 Dma transfer possibility/impossibility reporting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3102285A JPS61190650A (en) 1985-02-19 1985-02-19 Dma transfer possibility/impossibility reporting system

Publications (1)

Publication Number Publication Date
JPS61190650A true JPS61190650A (en) 1986-08-25

Family

ID=12319889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3102285A Pending JPS61190650A (en) 1985-02-19 1985-02-19 Dma transfer possibility/impossibility reporting system

Country Status (1)

Country Link
JP (1) JPS61190650A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157687A (en) * 1981-03-09 1982-09-29 Ibm Data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157687A (en) * 1981-03-09 1982-09-29 Ibm Data processing system

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