JPS61190633A - Program operation management system - Google Patents

Abstract

PURPOSE:To perform easy and efficient processing by generating interrupts at intervals of a prescribed time to process the level of a block divided in a pertinent time with respect to the operation management of a divided program which is processed on time division basis. CONSTITUTION:When the interrupt from a timer circuit occurs, the processing of operation management is executed, and contents of, for example, a level C for which the processing is executed before the occurrence of this interruption are stored in a memory MC. Next, a display execution block from a sequence memory MO is checked, and contents of, for example, a level A of the displayed execution block, namely, an interrupted level are read from a memory MA, and the display execution block of the sequence memory MO is updated to a following execution block, and the processing of the level A read from the memory MA is executed. The interruption from the timer circuit occurs when the prescribed time elapses after the processing of the level A is started, and the similar processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program operation management system for executing a large number of processes in a switching equipment in parallel.

(Prior art) Regarding this type of program operation management, for example, [D1
0 type automatic exchange [■] Software J (51RL82
).

It is described in "3. Execution Management", revised version published on April 1, 1980, Telecommunications Mutual Aid Association, pp. 90-133.

A switch is a collection of many different independent processes.
There are many processes that must be executed in real time. However, the processing device (CP) that executes the processing
Since there is only one, only one process can be performed at one time. In the exchange, there are various processing requests from a large number of subscribers, and the processing for each subscriber must be executed simultaneously. Therefore, each processing is divided into many blocks, and the processing unit (CP) By processing each block in a time-sharing manner, it is as if multiple processes were being performed simultaneously.

Conventional examples will be explained with reference to FIGS. 2, 3, 4, and 5. Figure 2 is an example of the execution state of each temporal level of the process, Figure 3 is the flowchart of the process, and Figure 4 is the third
FIG. 5 is a flowchart of operation management at the H level in FIG. 3, and FIG. 5 is a flowchart of operation management at the B/L level in FIG. For the sake of simplicity, a large number of processes will be divided into three blocks. Processing is divided into blocks in descending order of real-time requirements: H level, L level/I/, and BL/bell (Fig. 2). Note that switching equipment failure and diagnosis processing is not considered.

A timer circuit is provided outside the processing device (CP) to run for a certain period of time (
An interrupt is generated to the processing unit (cp) every 4 ms). When an interrupt occurs, the operation management process starts execution, stores the contents of the process being executed in memory, and executes the H level process (FIGS. 3 and 4). The H level process is executed, and when there is no more process to do, the L level process is executed next. Thereafter, when there is no more L level processing, B level processing is executed (FIG. 3). If an interrupt from the timer circuit occurs while executing L-level and B-level processing, the processing unit (cp) interrupts the processing and executes H-level processing (Figs. 2 and 3). figure). By repeating this process, a large number of processes are executed. After executing the H level process, if there is no process to be executed at the L level or B level, the processing unit (c
p) is not processed. In addition, when execution of one process at each level is completed, takeover information for performing the next process,
The processing request display and the like are stored in the memory (FIG. 5 (not shown in FIG. 4)). This is checked by operation management processing (Figures 4 and 5).

(Problem to be solved by the invention) In the above-described operation management system, processing by interrupts from the timer circuit, memory for processing to detect execution requests within each level, and processing by interrupts from the timer circuit and The amount of memory for storing large-scale, complex, and difficult-to-understand execution contents such as the memory for restarting L-level and B-level processing where processing is interrupted becomes extremely large.

In particular, for small-scale exchanges with few subscribers, it is not economical and difficult to maintain.

(Means for Solving the Problems) The present invention is an operation management method for divided programs that are processed in a time-sharing manner, and includes the following steps: dividing a plurality of different processes into blocks for each process of the same type; generating an interrupt, storing the contents of which the execution of the processing of the block was interrupted by the interrupt in a memory provided for each block; and displaying the next execution order of the block using a rule display means. This is a program operation management method consisting of executing the interrupt processing.

(Operations and Examples) FIG. 1 is a flowchart of the embodiment, FIG. 6 is an example of the execution state of each temporal level of processing in the embodiment, and FIG. 7 is an example of a flowchart showing the execution order in the embodiment. FIG. 8 is a circuit diagram for realizing the embodiment.

A large number of processing blocks are divided into three blocks.

Processing blocks are divided into similar types of processing, tentatively named A level, B level, and C level (Figure 6).
. The priorities among each level can be classified as processing, switching connection processing, time processing, billing processing, etc.

A timer circuit TM is provided outside the processing device cp to generate an interrupt to the processing device cp at predetermined intervals (Figs. 6 and 8).
figure). First, an interrupt from the timer circuit TM occurs, and A
Assume that execution of the level adjustment process is started (FIGS. 6 and 7). At this time, the level at which the execution of the process starts may be B or C level. For convenience of explanation, processing execution starts from the A level.

When an interrupt occurs in the timer circuit TM, the operation management process is executed as shown in Figure 1, and the process that was being executed before the interrupt occurred, that is, the interrupted contents of the C level, is stored in the memory M.
Store in C. Then, it checks the displayed execution block from the order memo IJMO that is stored in advance and changes the display of the execution order of blocks for each interrupt, and memoizes the displayed execution block, that is, the contents of the interrupted A level, from the memo IJMA. Raise (read) order memo IJMO
The display is updated to display the next execution block, that is, the B level, and the A level processing raised from the memo IJMA is executed.

As the A-level processing is executed, an interrupt occurs in the timer circuit TM after a predetermined period of time has passed, and the A-level processing is interrupted due to the execution of the operation management processing. , memo IJ of the execution interruption details of A-level processing.
Store it in M Execute processing. Timer circuit TM again
When an interrupt occurs, the execution of the B-level process is interrupted, its contents are stored in the memory MB, and the previously interrupted C-level process is started, and the interrupted contents are memorized. Pick up IJ M C, order memo I
Indicates to JMO that A level will be executed next, and executes C level processing. Then, an interrupt is generated from the timer circuit TM, and the A level processing is executed by the same processing as described above. By repeating these actions,
Processing at each level is A −+ B-+C-+ A −+
13-+C-+A..., and the processing of the exchange is executed, and the real-time processing of the exchange is also realized.

In addition, regarding the execution order of each level, A-4-B → A
-+ C-* A -+ B -+ A 4 C...
・Or in any other order. For each switch, including the number of processing blocks,
Can be selected arbitrarily.

Although the timer circuit in the embodiment is provided outside the memory IJMO, it may be provided inside the memory MO.

Furthermore, the time for interrupts from the timer circuit can also be made variable.

(Effects of the Invention) As explained above, according to the present invention, an interrupt is generated at a predetermined time interval, and processing is performed at the level of the divided blocks within the time, so that simple and efficient processing can be performed. can be done.

[Brief explanation of drawings]

Fig. 1 is a 70-chart of the embodiment, Fig. 2 is an example of the execution state of each temporal level of processing in conventional program operation management, Fig. 3 is a flowchart of conventional processing, and Fig. 4 is a 5 is a B/L level operation management flowchart in FIG. 3, FIG. 6 is an example of the execution state of each level of processing in the embodiment, and FIG. An example of a flowchart showing the order of execution in the embodiment, FIG. 8 is a circuit diagram for realizing the embodiment. Patent Applicant: Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Public Corporation Figure 1: Flow Naito of Ryozo MIG+1 Figure 2: aλ Accounting 9-Route Simple Seven-B Level R Hagi V
1 Fig. 3 Role kume-\170-ke-to Fig. 4 H'v＜+'J'Q JUk tongue f17o
-Figure 5 M pal's S guy? ! Sato 70- Figure 6 1 Harm removed 11 se 1 Hari 1 (欝1 Ouchi 0 each + bell kusai 61 Bunma no meeting Figure 8 % times procedural amendment (Mutsu) Incident display 1985 Relationship between the title case and the title case of invention of patent number 030471 Patent application Human Body Institute (
Address: 105) 1-7-12 Toranomon, Minato-ku, Tokyo
Address (105) 1-7-12 Toranomon, Minato-ku, Tokyo Contents of the amendment in the column "Detailed Description of the Invention" in the specification subject to the amendment As shown in Attachment 6, Contents of the amendment (1) Page 3 of the specification In the 10th line, "every time (assumed to be 4 ms)" is corrected to "every time". that's all

Claims (1)

[Claims] In an operation management method for divided programs that are processed in a time-sharing manner, (a) dividing a plurality of different processes into blocks for each process of the same type; (b) interrupting at predetermined time intervals; (c) storing the contents of the interruption of the execution of the processing of the block in a memory provided for each block; (d) displaying the next execution order of the block by a rule display means; and executing the interrupt processing.