JPS61189662A - Semiconductor ic for coil load drive - Google Patents

Abstract

PURPOSE:To obtain the titled device generating no latch-up even when the first and second island regions are made adjacent, by a method wherein the third island region is provided between the first and second island regions are biased at high potential, in this device whose output transistor is an open collector. CONSTITUTION:The third island region 38c is provided between the first and second island regions 38a and 38b and reversely biased by impressing the power source potential Vcc. In this structure, even if a parasitic thyristor structure is formed, the island region 38c must be bypassed in order that current flows from anode A to cathode K. An isolation region 37 serving as the current path at this time becomes considerably longer, which is followed by the increase in resistance. In other words, a considerably large resistance is interposed between the collector of a PNP transistor 30 and the base of an NPN transistor 31 in an equivalent circuit; therefore, even if the transistor 30 turns on, collector current does not flow. Besides, the parasitic thyristor cannot turn on because of losing self-bias and therefore falls into no latch-up.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to prevention of latch-up caused by a parasitic thyristor in a semiconductor integrated circuit for driving a coil load.

(B) Prior Art A conventional drive circuit for a coil load, such as a small motor, is described in, for example, Japanese Utility Model Application Publication No. 59-23296.

Figure 2 shows a circuit equivalent to this, where (1) is a constant current source,
(2) is a Zener diode as a reference voltage generating element, (3) is a comparator, (4) is a constant voltage transistor, (5
1 (6) is an output transistor, and (6) is an open collector at the final stage. (M) is a small motor as a coil load, (Vcc) is a power supply potential, (SW) is a switch, (71 (8) is a resistor and variable resistor that constitutes a voltage divider, (9) is an emitter resistance, and a mouse is an integrated IC block when converted into a circuit (IC), (lla) (llb) -- (li
e) is an external terminal derived from IC block 4, (R1
)(Rz)(Rs) is a resistor biased to a high potential relatively close to the power supply potential (Vcc).

Figure 3 is a cross-sectional view of the above drive circuit when integrated into an IC, showing the output transistor (6) which becomes an open collector and (R8) of the resistors (R1) (R1) (R3). .

Here, α9 is a P-type semiconductor substrate, a is an N+ type buried layer, 1
7) is a P+ type isolation region, (18a) and (18b) are first and second island regions separated into island shapes by isolation region αD,
(19a) (19b) are P-heavy diffusion regions, (20a) (2
0b) is an N+ type diffusion region, 121) is an oxide film, ■...
...(A) is an electrode provided on each region.

Then, an NPN type output transistor (6) is constructed with the first island region (18a) as the collector, the P heavy diffusion region (19a) as the pace, and the N+ type diffusion region (20a) as the emitter. A resistor (R3) using the diffused resistor of the P-heavy diffused region (19b) is formed in the island region (18b). The N+ type diffusion region (20a), the isolation region aη and the substrate − are biased to ground potential (GND) via the external terminal (lie) of the emitter electrode, and the electrode (H) is biased at one end of the P heavy diffusion region (19b). ) connects the external terminal (l
lb) to a relatively high potential. Furthermore, the collector electrode (241ttN+ type diffusion region (20b)
) is derived as a contact, and the external terminal (li
d) is connected to a small motor (M).

However, as mentioned above, both are adjacent island areas (1
8a) (18b) is virtually impossible. The reason is explained below.

A small motor (M) serving as a coil load is an actuator that rotates when a voltage is applied from the outside, but conversely, it is also a generator that generates an induced voltage when rotation is applied. Due to these characteristics, the switch (SW) is 0N-
When OFF is repeated, the collector of the output transistor (6) goes to ground potential (GND) at the moment the switch (SW) is turned ON.
A lower condition occurs. Then, the ground potential (GND
) A Km flow flows from the separated region (1?) which is biased by K to the first island region (18a) which is the collector, and this serves as a trigger to form a parasitic thyristor as shown in FIG.

The parasitic thyristor uses the P-heavy diffusion region (19b) as the emitter,
PNP with the second island region (18b) as the pace and the separation region value η as the collector) run lister (to), the second island region (18b) as the collector and the separation region (17) as the base,
It has a PNPN junction structure in which an NPN (npn) run lister Gυ is combined with the first island region (18a) as an emitter, the P heavy diffusion region (19b) is an anode, and the separation region C1
7) as a gate (G) and the first island region (18a) as a cathode (K), which operates under self-bias. To explain the operation, when a trigger is applied to the gate (G), the NPN) run lister (31) is turned on, and its collector current becomes PNP.
) By pulling in the base of Runlister (to) P
NP ) run lister (to) is ONL, once both transistors (to) Gυ are ON, PNP) run lister (
The collector current of NPN) works to deepen the bias of NPN) run lister Gυ, and the collector current of NPN) run lister 01
Since the collector current of ) works in the direction of deepening the bias of the PNP run lister (to), a large current flows from the anode (A) to the cathode (K) as a result.

If the output transistor (6) is in the ON state when the parasitic thyristor is formed, the current that is about to flow due to the above operation is drawn to the ground potential (GND), and as a result, from the P-type diffusion region (19b). N+ type diffusion region (2
A latch-up occurs in which a large current flows to 0a).

While the operating current in the steady state is 100 to 200 mA, the current in the latch-up state is around 1 A, which not only causes malfunction of the drive circuit but also destroys the IC.

For the above reasons, it has conventionally been impossible to arrange the output transistor (6) and the resistors (R1) (Rt) (R3) adjacent to each other.

(c) Problems to be solved by the invention However, being subject to the above restrictions causes inconveniences in pattern design, and since wiring must be placed far apart from each other, the wiring becomes long and complicated, making it difficult to achieve high integration. However, the disadvantage was that the chip area was too large and the cost was high.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and provides a method for driving a coil load that does not cause latch-up even when the first and second island regions (38a) and (38b) are adjacent to each other. A first island region (38a) in which an output transistor (6) is formed and a second island region in which a resistor (R8) biased to a relatively high potential is formed, the purpose being to provide a semiconductor integrated circuit. (38b) and is characterized by providing a third island region (38c) and reverse biasing at a high potential, such as a power supply potential (cc).

(E) Effect According to the present invention, if the anode (A) is connected to the cathode (
K) to 1! If the current is about to flow, the third island area (38c
) must be bypassed. At this time, the length of the isolation region G, which becomes a current path, becomes considerably long, and the resistance also increases accordingly. That is, in the circuit shown in Fig. 5, a considerably large resistance intervenes between the collector of the PNP transistor ■ and the pace of the NPN transistor 6υ, so that the PNP) run lister ■ is ONt,
However, no collector current flows, and the parasitic thyristor loses its self-bias and cannot turn on. Therefore, it becomes possible to arrange the resistor (Rt) (Rt) (Rs) near the output transistor (6), which was previously impossible.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

1 and 2 are a plan view and a sectional view, respectively, showing an embodiment of the present invention, and in the drive circuit shown in FIG. 3, an output transistor (6) serving as an open collector and a resistor (R+) are shown.
Of (Rz) (Rs), (R8) is shown.

Here, (to) is a P-type semiconductor substrate, (to) is an N+ type buried layer, Gη is a P+ type isolation region, (38a) (38b) (38
(39a) and (39b) are the first, second, and third island regions separated into islands by the separation region (7), respectively;
Type diffusion regions, (40a), (40b, and 40c) are N-type diffusion regions, Cυ is an oxide film, and (4η) is an electrode provided on each region.

Then, an NPN type output transistor (6) is configured with the first island region (38a) as the collector, the P type diffusion region (39a) as the pace, and the N+ type diffusion region (40a) as the emitter. (38b) has a P-type diffusion region (3
A resistor (R8) using the diffused resistor of 9b) is formed. An external terminal (11e
), and one end of the P-type diffusion region (39b) is biased to a relatively high potential by an electrode (4bl) via an external terminal (llb).Furthermore, a collector electrode ( 44) is an N+ type diffusion region (
40b) as a contact, and the external terminal (
It is connected to a small motor (M) via a small motor (M).

Furthermore, a first island area (38a) and a second island area (38b)
) A third island region (38c) is provided between the N+ type diffusion region (40c) and the power supply voltage (cc).
is applied, and its size is set to be more elongated than the island region (38a) in which the output transistor (6) is formed.

The most distinctive feature of the present invention is that the first island region (38a)
and the second island area (38b).
c) is provided and reverse biased by applying a power supply potential (VC, , ). According to this structure, even if a parasitic thyristor structure is formed, the current must bypass the island region (38c) in order to flow from the anode (A) to the cathode (K). At this time, the length of the separation region Gη, which becomes a current path, becomes considerably long, and the resistance also increases accordingly. That is, in the circuit shown in Fig. 5, PN
Since a considerably large resistance intervenes between the collector of the P) run lister (to) and the pace of the NPN) run lister B, even if the PNP) run lister (to) is turned on, the collector current will not flow, and the parasitic thyristor will Since it loses bias and cannot turn on, it does not fall into latch-up. Therefore, resistance (R1) (R2) that was previously impossible
(R8) can be placed near the output transistor (6).

The manufacturing method of this example will be described below.

First, an N-type impurity, such as phosphorus (Pl), is doped by selective diffusion into a region of a P-type semiconductor substrate (c) that is to become an N+ type buried layer circle.

Next, an N- type epitaxial layer is formed using an epitaxial growth method, and at the same time, the previously doped phosphorus (Pl) is driven in to form an N+ type buried layer.

Next, a P type impurity such as boron (B+) is doped by selective diffusion to form a P+ type isolation region 071 that reaches from the surface of the epitaxial layer to the substrate.
, second and third island areas (38a) (38b) (38C)
will be established.

Next, KP type diffusion regions (39a) (39b) and N+ type diffusion regions (40a) (40b) (40c) are sequentially formed by double diffusion.

Thereafter, a contact hole is provided in the oxide film (41) on each region, and aluminum is deposited by a well-known vapor deposition technique to form each electrode (4B (43...Cη), thereby completing the process.

(G) Effects of the Invention According to the present invention, it is possible to arrange the resistors (L), (Rt), and (Ra) near the output transistor (6), which increases the degree of freedom in pattern design and improves wiring. It has the advantage that the routing can be shortened, high integration is facilitated, and the chip size can be reduced, resulting in cost reduction.

[Brief explanation of the drawing]

1 and 2 are a plan view and a cross-sectional view showing an embodiment of the present invention, respectively. FIG. 3 is a circuit diagram showing a drive circuit for a small motor, and FIGS. 4 and 5 each illustrate a conventional example. FIG. 2 is a cross-sectional view and an equivalent circuit diagram. Explanation of the main drawing numbers (6) is the output transistor, (M) is the small motor, (R
1) (Rt) (us) are resistors biased to a relatively high potential, (38a) (38b) (38c) are the first resistors, respectively.
, the second and third island regions, (39a) and (39b) are P type diffusion regions, and (40a), (40b) and (40c) are N+ type diffusion regions. Applicant Sanyo Electric Co., Ltd. and 1 other agent Patent attorney Sano Shizuo No. 4r: tJ

Claims (1)

[Claims] (1) Having multiple island regions electrically isolated from each other,
A semiconductor integrated circuit for driving a coil load, comprising an NPN output transistor formed in a first island region and a resistor biased to a relatively high potential formed in a second island region, the output transistor being an open collector. A coil load drive characterized in that a third island region is provided between the first island region and the second island region and biased to a high potential to prevent latch-up due to a parasitic thyristor. Semiconductor integrated circuits.