JPS6118889B2 - - Google Patents
Info
- Publication number
- JPS6118889B2 JPS6118889B2 JP11466577A JP11466577A JPS6118889B2 JP S6118889 B2 JPS6118889 B2 JP S6118889B2 JP 11466577 A JP11466577 A JP 11466577A JP 11466577 A JP11466577 A JP 11466577A JP S6118889 B2 JPS6118889 B2 JP S6118889B2
- Authority
- JP
- Japan
- Prior art keywords
- winding
- circuit
- load
- output
- pulse transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims description 41
- 238000001514 detection method Methods 0.000 claims description 23
- 230000004907 flux Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 9
- 230000005856 abnormality Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、通信機または電子計算機等に適する
駆動回路の改良に関する。特にトランジスタスイ
ツチにより電源を開閉する駆動回路の障害検出回
路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in drive circuits suitable for communication devices, electronic computers, and the like. In particular, the present invention relates to a failure detection circuit for a drive circuit that opens and closes a power supply using a transistor switch.
駆動回路と負荷を接続する駆動線路対をパルス
トランスに一次巻線として巻回して、正常な負荷
駆動時には磁束が互いに打ち消されるようにして
異常を検出する負荷側障害検出回路において、
外部からトリガ信号を入力する走査巻線を備え
て、トリガ入力のときの出力巻線の出力と外部か
らのストローブ信号との論理積をとることによ
り、
ノイズに強く、また経済性の高い障害検出回路
を実現するものである。
In the load-side fault detection circuit, which detects an abnormality by winding the drive line pair that connects the drive circuit and the load as a primary winding around a pulse transformer so that the magnetic flux cancels each other during normal load driving, a trigger signal is received from the outside. A fault detection circuit that is highly resistant to noise and highly economical is realized by providing a scanning winding that inputs the signal and performing a logical product between the output of the output winding and the external strobe signal when the trigger is input. It is something.
各種の素子や電子回路による論理回路等に電源
を供給する駆動回路では、負荷となる素子や論理
回路等が使用されるときのみ電源を供給すること
が必要であり、駆動回路にトランジスタスイツチ
が備えられ、これにより駆動電流が開閉されるよ
う構成されている。この種の回路では負荷側に短
絡障害や地絡障害があると、駆動回路のトランジ
スタスイツチが損傷したり、共通の電源により動
作中の他の負荷への駆動電圧が低下する等の不都
合があるため、負荷側障害検出回路が備えられ障
害のある負荷に対しては、駆動が行われないよう
に構成されたものが一般的である。
In a drive circuit that supplies power to various elements and logic circuits made of electronic circuits, it is necessary to supply power only when the load element or logic circuit is used, and the drive circuit is equipped with a transistor switch. The structure is such that the drive current is opened and closed thereby. In this type of circuit, if there is a short circuit or ground fault on the load side, the transistor switch in the drive circuit may be damaged, or the drive voltage to other loads operating from the common power supply may drop. Therefore, it is common that a load-side fault detection circuit is provided so that a faulty load is not driven.
このような負荷側障害検出回路としてパルスト
ランスを用い、そのトランスの磁束の不平衡を検
出して障害を検出する方式が提案されている。
〔文献 特公昭52−26090号公報〕
第１図に従来例の回路図を示す。図において、
１は駆動回路、４は負荷、５は検出回路を示す。
図に示すように、駆動回路１の出力端子の電流
は、一旦検出回路５を経由して負荷４に供給され
るよう構成されている。 A method has been proposed in which a pulse transformer is used as such a load-side fault detection circuit, and a fault is detected by detecting the unbalance of the magnetic flux of the transformer.
[Reference: Japanese Patent Publication No. 52-26090] Figure 1 shows a circuit diagram of a conventional example. In the figure,
1 is a drive circuit, 4 is a load, and 5 is a detection circuit.
As shown in the figure, the current at the output terminal of the drive circuit 1 is configured to be supplied to the load 4 via the detection circuit 5.
検出回路５には、２個の一次巻線N1，N2を有
するパルストランスＴを備え、駆動回路１の出力
端子の電流が、それぞれこの巻線N1，N2を経由
するよう接続されている。その接続方向は第１図
に黒丸で示す向きで、駆動回路１の２個の出力端
子から流出しまたは流入する電流が等しいときに
は、パルストランスＴの磁束が打ち消されるよう
構成されている。このパルストランスＴには二次
巻線N3，N4が施され、これに現れた電圧はダイ
オードD1およびD2により全波整流され、抵抗器
Ｒに供給されている。この抵抗器Ｒと並列に定電
圧ダイオードD3が接続され、全波整流された電
圧が一定の値を越えたときには、検出回路５の出
力Ｐに電圧信号が送出されるよう構成されてい
る。 The detection circuit 5 includes a pulse transformer T having two primary windings N 1 and N 2 , and the current at the output terminal of the drive circuit 1 is connected to pass through the windings N 1 and N 2 , respectively. ing. The connection direction is shown by the black circle in FIG. 1, and the configuration is such that when the currents flowing out or flowing in from the two output terminals of the drive circuit 1 are equal, the magnetic flux of the pulse transformer T is canceled out. This pulse transformer T is provided with secondary windings N 3 and N 4 , and the voltage appearing thereon is full-wave rectified by diodes D 1 and D 2 and supplied to a resistor R. A constant voltage diode D3 is connected in parallel with this resistor R, and is configured so that a voltage signal is sent to the output P of the detection circuit 5 when the full-wave rectified voltage exceeds a certain value.
このように構成された回路の動作を説明する
と、駆動回路１が負荷４を駆動するため、トラン
ジスタスイツチSWが閉じると、検出回路５のパ
ルストランスＴの一次巻線N1，N2に電流が流れ
る。いま、負荷４が正常であれば、駆動回路１の
一方の端子から流出する電流と他方の端子に流入
する電流は等しいので、２個の一次巻線N1，N2
の電流による磁束は互いに打ち消し合つて、パル
ストランスＴは磁化されない。従つて、二次巻線
N3，N4は電圧が現れない。 To explain the operation of the circuit configured in this way, since the drive circuit 1 drives the load 4, when the transistor switch SW is closed, current flows through the primary windings N1 and N2 of the pulse transformer T of the detection circuit 5. flows. Now, if the load 4 is normal, the current flowing out from one terminal of the drive circuit 1 and the current flowing into the other terminal are equal, so the two primary windings N 1 and N 2
The magnetic fluxes caused by the currents cancel each other out, and the pulse transformer T is not magnetized. Therefore, the secondary winding
No voltage appears for N 3 and N 4 .
また、負荷４の回路に地絡または混線等の異常
があると、駆動回路１の両端子の電流は等しくな
い。このため、電流立上がりの過渡時間にパルス
トランスＴの二次巻線には電圧が現れ、これが一
定の値を越えると、検出回路５の出力Ｐに出力信
号が送出される。 Further, if there is an abnormality such as a ground fault or crosstalk in the circuit of the load 4, the currents at both terminals of the drive circuit 1 will not be equal. Therefore, a voltage appears in the secondary winding of the pulse transformer T during the transition time of the current rise, and when this exceeds a certain value, an output signal is sent to the output P of the detection circuit 5.
このような従来回路では、２個の一次巻線
N1，N2の平衡性が強く要求され、構成部品のコ
スト増となつたり、駆動電流の立上がり時や立下
がり時の位相差による不平衡分が出力巻線に発生
し、正常であるにもかかわらず障害表示をしてし
まう等の欠点があつた。
In such a conventional circuit, two primary windings
Balancing of N 1 and N 2 is strongly required, which increases the cost of component parts, and causes unbalanced components in the output winding due to phase differences at the rise and fall of the drive current, which may be normal. Despite this, there were drawbacks such as displaying a failure message.
本発明はこれらを改良するもので、２個の一次
巻線の平衡性をさほど要求しなくても、過渡現象
等のノイズに影響を受けず確実に動作する負荷側
障害検出回路を提供することを目的とする。 The present invention improves these, and provides a load-side failure detection circuit that operates reliably without being affected by noise such as transient phenomena, without requiring much balance between the two primary windings. With the goal.
本発明は、二次巻線として出力巻線のほかに走
査巻線を設け、その走査巻線は外部トリガ信号に
より導通するトランジスタにより駆動され、上記
出力巻線の出力と外部からのストローブ信号との
論理積をとる構成としたことを特徴とする。
The present invention provides a scanning winding as a secondary winding in addition to the output winding, and the scanning winding is driven by a transistor that is turned on by an external trigger signal, and the output of the output winding and a strobe signal from the outside are connected. It is characterized by having a configuration that takes the logical product of .
負荷側が正常であれば、パルストランスの磁束
は打ち消されて磁化されていないので、トリガ信
号がパルストランスに入力されると、出力巻線の
出力として電圧信号が現れ、ストローブ信号との
論理積がとられると、正常であることの信号が出
力される。
If the load side is normal, the magnetic flux of the pulse transformer is canceled and it is not magnetized, so when the trigger signal is input to the pulse transformer, a voltage signal appears as the output of the output winding, and the logical product with the strobe signal is When it is removed, a signal indicating normality is output.
負荷側に異常があると、パルストランスの磁心
は飽和するため、トリガ信号が入つても出力巻線
にはトリガ信号に対応する電圧は出力されず、ス
トローブ信号との論理積がとられると、正常な信
号が出力されないので、負荷側に異常があること
が検出される。 If there is an abnormality on the load side, the magnetic core of the pulse transformer will be saturated, so even if a trigger signal is input, the voltage corresponding to the trigger signal will not be output to the output winding, and when the logical product with the strobe signal is taken, Since a normal signal is not output, it is detected that there is an abnormality on the load side.
以下に本発明の実施例を説明する。 Examples of the present invention will be described below.
第２図は本発明の実施例回路図である。この実
施例は検出回路５に検出トリガ信号とストローブ
信号を与え、駆動電流の立上がり時に雑音の妨害
なく負荷の異常を検出できるよう構成された回路
である。すなわち、トランスＴの二次巻線N3に
はトランジスタＱと電源Ｅが接続されていて、ト
リガ信号入力TRにトリガ信号が与えられると、
トランジスタＱが動作して二次巻線N3に電流が
流れるよう構成されている。また、二次巻線N4
はこのトリガ信号に応じて流れる電流により発生
する電圧を検出することができるよう、その極性
が定められストローブ信号Ｓにより制御されるア
ンド回路Ａを介して、検出回路５の出力Ｐに導か
れている。その他の部分の構成は第２図に示す例
と同様である。 FIG. 2 is a circuit diagram of an embodiment of the present invention. This embodiment is a circuit configured so that a detection trigger signal and a strobe signal are applied to the detection circuit 5, and an abnormality in the load can be detected without interference from noise when the drive current rises. That is, a transistor Q and a power supply E are connected to the secondary winding N3 of the transformer T, and when a trigger signal is applied to the trigger signal input TR,
The transistor Q is configured to operate so that current flows through the secondary winding N3 . Also, the secondary winding N 4
is guided to the output P of the detection circuit 5 via an AND circuit A whose polarity is determined and controlled by the strobe signal S so that the voltage generated by the current flowing in response to the trigger signal can be detected. There is. The configuration of other parts is the same as the example shown in FIG.
このような回路の動作を第３図に示す動作図を
用いて説明する。第３図イ〜ホは第２図に対応す
る符号を付して示す×印の点の電圧または電流波
形図である。第３図イは駆動回路１の駆動信号波
形図である。ロは検出回路５に与えられるトリガ
信号波形図である。 The operation of such a circuit will be explained using the operation diagram shown in FIG. FIGS. 3A to 3E are voltage or current waveform diagrams at points marked with an x and indicated by the symbols corresponding to those in FIG. 2. FIG. 3A is a drive signal waveform diagram of the drive circuit 1. B is a trigger signal waveform diagram given to the detection circuit 5.
いま、負荷の状態が正常であるとすれば、検出
回路５のパルストランスＴの一次巻線N1および
N2に流れる電流は等しいので、磁束が互いに打
ち消されて磁化されていない。このときトリガ信
号が第４図ロのように与えられると、これに応じ
て磁束が変化し、二次巻線N4に第３図ハのよう
な電圧が生じる。 Now, assuming that the load condition is normal, the primary winding N 1 of the pulse transformer T of the detection circuit 5 and
Since the current flowing through N2 is equal, the magnetic flux cancels each other and it is not magnetized. At this time, when a trigger signal is applied as shown in FIG. 4B, the magnetic flux changes accordingly, and a voltage as shown in FIG. 3C is generated in the secondary winding N4.
次に、負荷に異常であつてパルストランスＴの
一次巻線N1およびN2に流れる電流が等しくない
ときには、駆動電流が立ち上がるとパルストラン
スＴの磁心は飽和されてしまう。このため第３図
ロに示すトリガ信号が巻線N3に与えられても、
これによるパルストランスＴの磁心の変化はほと
んどなく、二次巻線N4には第３図ニに示す電圧
が生じる。 Next, if there is an abnormality in the load and the currents flowing through the primary windings N 1 and N 2 of the pulse transformer T are not equal, the magnetic core of the pulse transformer T will be saturated when the drive current rises. Therefore, even if the trigger signal shown in Figure 3B is applied to winding N3 ,
This causes almost no change in the magnetic core of the pulse transformer T, and the voltage shown in FIG. 3D is generated in the secondary winding N4.
第３図ホは検出回路５に対するストローブ信号
波形で、ホに示すストローブ信号に対応して、負
荷が正常ならば出力Ｐには「１」が、異常ならば
「０」が現れる。 FIG. 3E shows the strobe signal waveform for the detection circuit 5. Corresponding to the strobe signal shown in E, "1" appears at the output P if the load is normal, and "0" appears if the load is abnormal.
このような回路では、雑音の影響の少ない安定
した時間を選んでストローブ信号を与えることが
できるので、検出回路５の動作はより確実にな
る。 In such a circuit, since the strobe signal can be applied by selecting a stable time when the influence of noise is low, the operation of the detection circuit 5 becomes more reliable.
以上述べたように、本発明によればパルストラ
ンスの２個の一次巻線の平衡性はほとんど問題と
ならず、安価な部分を使用でき経済性がよい。ま
た駆動電流の立上がり時や立下がり時の過渡現象
発生時を避け、状態が安定した時点で障害検出が
実施され、かつ走査用信号の過渡現象発生時もイ
ンヒビツトしているため、非常にノイズに強いと
いう効果がある。
As described above, according to the present invention, the balance between the two primary windings of the pulse transformer is hardly a problem, and inexpensive parts can be used, resulting in good economy. In addition, fault detection is performed when the condition is stabilized, avoiding transient phenomena at the rise or fall of the drive current, and inhibiting is also performed when transient phenomena occur in the scanning signal, resulting in extremely low noise. It has the effect of being strong.
第１図は従来例の回路図。第２図は本発明実施
例の回路図。第３図は第２図に示す回路の動作波
形図。
１……駆動回路、４……負荷、５……検出回
路、Ｔ……パルストランス、TR……トリガ信号
端子、Ｓ……ストローブ信号端子、Ａ……アンド
回路、Ｑ……トランジスタ、Ｐ……出力。
FIG. 1 is a circuit diagram of a conventional example. FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is an operating waveform diagram of the circuit shown in FIG. 2. 1... Drive circuit, 4... Load, 5... Detection circuit, T... Pulse transformer, TR... Trigger signal terminal, S... Strobe signal terminal, A... AND circuit, Q... Transistor, P... …output.
Claims (1)
をパルストランスの一次側巻線として巻回し、正
常な負荷駆動時には上記二個の一次巻線による磁
束が互いに打ち消される構成の負荷側障害検出回
路において、 上記パルストランスの二次側巻線として巻回さ
れた出力巻線および走査巻線の二つの巻線と、 上記走査巻線と直列に接続され、外部からのト
リガ信号により導通するトランジスタと、 前記出力巻線の出力がその一方に入力され、他
方の入力にはストローブ信号が入力されるアンド
回路と、 を備えたことを特徴とする駆動回路の負荷側障害
検出回路。[Scope of Claims] 1. A configuration in which each drive line pair connecting the drive circuit and the load is wound as a primary winding of a pulse transformer, and magnetic fluxes from the two primary windings cancel each other during normal load driving. In the load-side fault detection circuit, two windings, an output winding and a scanning winding, are wound as the secondary winding of the pulse transformer, and the scanning winding is connected in series with the scanning winding, and a trigger from the outside is connected to the output winding and the scanning winding. A load-side fault detection for a drive circuit, comprising: a transistor that is turned on by a signal; and an AND circuit, one of which receives the output of the output winding, and the other of which receives a strobe signal. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11466577A JPS5448436A (en) | 1977-09-26 | 1977-09-26 | Failure detection circuit at load side for driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11466577A JPS5448436A (en) | 1977-09-26 | 1977-09-26 | Failure detection circuit at load side for driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5448436A JPS5448436A (en) | 1979-04-17 |
| JPS6118889B2 true JPS6118889B2 (en) | 1986-05-14 |
Family
ID=14643508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11466577A Granted JPS5448436A (en) | 1977-09-26 | 1977-09-26 | Failure detection circuit at load side for driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5448436A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0524396U (en) * | 1991-08-20 | 1993-03-30 | 重一 山内 | Blackboard for construction photo |
-
1977
- 1977-09-26 JP JP11466577A patent/JPS5448436A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0524396U (en) * | 1991-08-20 | 1993-03-30 | 重一 山内 | Blackboard for construction photo |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5448436A (en) | 1979-04-17 |
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