JPS6118872B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an integrated circuit device whose main element is a MOS transistor, and specifically,
MOS type large scale integrated circuit
Integration; hereinafter abbreviated as LSI. ) relates to the structure of an input gate protection circuit incorporated in. Generally, transistors constituting a MOS type integrated circuit are formed as shown in FIGS. 1A and 1B. In other words, those MOS type transistors 1
0, an N-type drain region 2 and a source region 3 are formed on a P-type semiconductor substrate 1, and a gate insulating film 4 having a thickness of about 1000 angstroms is formed between the source region 2 and the drain region 3. Further, contact holes 5 and 6 are formed in the source region 2 and drain region 3, and a source electrode 7, a drain electrode 8, and a gate electrode 9 are respectively formed. The MOS transistor 10 formed in this manner is formed by applying a voltage higher than a threshold voltage of several volts to several tens of volts to the gate electrode 9, thereby forming a connection between the source region 2, the drain region 2, and the drain region through the insulating film 4. A channel 12 is induced in the semiconductor substrate surface 11 surrounded by the region 3, and a transistor operates according to the MOS principle. However, these MOS transistors 10
The voltage applied to the gate electrode 9 is not only the normally applied voltage of several volts to several tens of volts, but sometimes an abnormal voltage of several hundred volts is sometimes applied. Such a voltage is applied to the transistor 10.
Applying this voltage to the gate electrode 9 exceeds the limit of the gate insulation condition of the gate insulating film 4, and dielectric breakdown occurs between the substrate 1 and the gate electrode 9, rendering the transistor 10 unusable. It had become possible. These so-called "gate breakdowns" are one type of transistor breakdown phenomenon, and those who manufacture MOS type integrated circuits must prevent such breakdowns. By the way, some simple circuits for preventing gate destruction are shown in FIGS. 1A, B, and C. That is, these gate protection circuits 18 form an N-type diffusion region 13 in addition to the MOS transistor 10, as shown in FIGS. Gate electrode 9
Electrode wirings 14 and 15 are formed between the input terminal IN and the input terminal IN. The equivalent circuit of the gate protection circuit 18 formed in this manner is shown in FIG.
It can be expressed as follows. That is, according to the gate circuit device 18, the MOS transistor 10
Gate protection is performed by the resistance of the diffusion region 13, and since the resistance region 13 structurally forms a PN junction 16 with the substrate 1, for example, the PN junction is protected at 30 volts. Since breakdown occurs, it also has a PN diode in the opposite direction between it and ground. Therefore, even if the input IN receives a rapidly rising transient voltage of, for example, several hundred volts,
Since the PN junction 16 of the resistance region 13 causes breakdown and releases the excessive voltage to the ground, the resistance R of the resistance region 13 and the gate electrode 9 of the MOS transistor 10 are connected to the source 2, the stray capacitance C between the drain 3 and the substrate 1, and the wiring electrode 15 connected to the substrate 1.
The voltage is relaxed by the time constant of the CR circuit consisting of the stray capacitance C between the MOS transistor 10 and the MOS transistor 10. However, the problem of gate destruction could be solved for the time being. However, in such a gate protection circuit 18, there is a risk that the following electrode wiring may be burnt out. In other words, in these gate protection circuits 18 _, the specific means of protection against overvoltage is simply the formation of the resistance region ₁₃ alone; Since the diodes are connected in parallel, the breakdown described above occurs from the diode _D1 with the higher input voltage, that is, from the signal input IN side of the resistance region 13. Therefore, diode _D1 is a diode
If the resistance of D ₁ is ignored, the circuit becomes a closed circuit with no resistance, so if a break town occurs, an infinite current I will flow. Furthermore, if a forward voltage is applied to the resistance region 13, the current will directly turn into a forward current and flow into the base 1, causing the electrode wiring 14
A very large current I was passed through the . Therefore, the electrode wiring 14 having a slight resistance generated heat and was eventually burnt out.
And the fact that the wiring 14 is burnt out like this,
Since the input signal to the MOS transistor 10 was lost, the integrated circuit ceased to operate. Therefore, the present invention provides an improved semiconductor device made in view of the above drawbacks,
The present invention provides a gate protection structure formed to prevent the electrode wiring from blowing out, and provides an integrated circuit device equipped with the gate protection structure. According to the present invention, a semiconductor substrate of one conductivity type, a pair of source/drain regions of another conductivity type formed within the semiconductor substrate, and a pair of source/drain regions formed between the source/drain regions. In an insulated gate field effect transistor, the insulated gate field effect transistor has a gate insulating film formed on the substrate, a gate electrode formed on the gate insulating film, and a source electrode/drain electrode formed on the source region/drain region. In order to prevent destruction of the gate electrode/insulating film of a type field effect transistor, a diffusion region having a different conductivity type is formed in the semiconductor substrate, and a contact region of an electrode taken out from the diffusion region is prevented. The impurity concentration of the diffusion region is adjusted, at least in part, to have a high ohmic contact resistance, and in particular an electrode wiring is arranged between the gate input signal source and the gate electrode through the diffusion region. The present invention provides an integrated circuit device characterized in that it has a configuration formed in such a manner as to provide an integrated circuit device. Now, in order to better understand the purpose and structure of the present invention, one embodiment of the present invention will be described using FIGS. 2A, B, and C. According to Figure 2 A and B, the base impurity concentration is 1×
A P conductivity type semiconductor substrate 21 having a density of 10 ¹⁵ pieces/cm ³ to 1×10 ¹⁶ pieces/cm ³ is prepared, and a normal MOS transistor 20 is formed as follows. That is, the P
At least a pair of source and drain regions 22 and 23 of N dielectric type with a surface concentration of 1×10 ²⁰ atoms/cm ³ are formed in a type semiconductor 21, and between the source region 22 and drain region 23, has a thin insulating film 2 of about 1000 angstroms.
A gate electrode 29 made of aluminum, for example, is formed thereon, and ohmic contact holes 25 and 26 are formed in the source region 22 and drain region 23 to form a source made of aluminum. An electrode 27 and a drain electrode 28 are formed. On the other hand, a gate protection circuit 30 is formed separately from the transistor 20 on the same semiconductor substrate 21 at a different position.
An N conductivity type diffusion region 33 is formed by simultaneous diffusion with the drain region 23 and has a surface concentration of approximately 1×10 ²⁰ atoms/cm ³ , and a surface concentration of 3×10 ¹⁹ atoms/cm 3 is formed by boron ion implantation. ³ and the aluminum wiring electrode 3.
4 and 35. A particularly notable structure here is that impurity concentration adjustment regions 33', 33'' exist under the aluminum wiring electrodes 34, 35. Such impurity concentration adjustment regions 33', 3
The reason for providing 3″ is that the aluminum wiring electrode 3
This is to provide ohmic contact resistance between 4 and 35. In selecting these ohmic contact resistors appropriately, the following conditions are taken into consideration. That is, as disclosed in various literature, ohmic contact can be created by first appropriately selecting a semiconductor material and an electrode material connected to the semiconductor material. First, in order to have ohmic contact, the work function of the semiconductor material is φ _s and the work function of the electrode material is φ _n.The relationship between the work functions is

[Table] This can be done by selecting materials as shown in the table below.
Here it is an N-type silicon semiconductor substrate 21
and aluminum wiring electrodes 34 and 35. Furthermore, in order to provide the ohmic contact with an appropriate resistance R _c , the base impurity concentration N _D of the semiconductor material and the electrode connection area are arbitrarily set. According to the inventors of the present application, the relationship between the impurity concentration of the substrate and the resistance value (R _c ) depending on the contact area is set approximately as follows. Γ surface concentration N _D 1×10 ¹⁹ pieces/cm ³ (Resistance per unit area 10 ^-1 [Ω・cm ² ]) ・Contact area 10 [μ] × 10 [μ] R _c = 10 ^-1 [Ω・cm ² ]/10×10 ^-4 [cm]・10×10 ^-4 [cm]・=100 [KΩ] ・Contact area 7 [μ]×7 [μ] R _c =10 ^-1 [Ω・cm ² ] /7×10 ^-4 [cm]・7×10 ^-4 [cm]200 [KΩ] ・Contact area 6 [μ]×6 [μ] R _c =10 ^-1 [Ω・cm ² ]/6× 10 ^-4 [cm]・6 ×10 ^-4 [cm] 300 [KΩ] Γ surface concentration N _D 2×10 ¹⁹ pieces/cm (resistance per unit area 10 ^-2 [Ω・cm ² ]) ・Contact area 10 [μ] × 10 [μ] R _c = 10 ^-2 [Ω・cm ² ] / 10 × 10 ^-4 [cm] ・10 × 10 ^-4 [cm] = 10 [KΩ] ・Contact area 7 [μ] ] × 7 [μ] R _c = 10 ^-2 [Ω・cm ² ] / 7 × 10 ^-4 [cm] ・7 × 10 ^-4 [cm] 20 [KΩ] ・Contact area 6 [μ] × 6 [ μ] R _c =10 ^-2 [Ω・cm ² ]/6×10 ^-4 [cm]・6 ×10 ^-4 [cm] 30 [KΩ] ΓSurface concentration N _D 3×10 ¹⁹ pieces/cm (unit Resistance per area 10 ^-3 [Ω・cm ² ]) ・Contact area 10 [μ] × 10 [μ] R _c = 10 ^-3 [Ω・cm ² ] / 10 × 10 ^-4 [cm] ・10 × 10 ^-4 [cm] = 1 [KΩ] ・Contact area 7 [μ] × 7 [μ] R _c = 10 ^-3 [Ω・cm ² ] / 7 × 10 ^-4 [cm] ・7 × 10 ^-4 [cm] 2 [KΩ] ・Contact area 6 [μ] × 6 [μ] R _c = 10 ^-3 [Ω・cm ² ] / 6 × 10 ^-4 [cm] ・6 × 10 ^-4 [cm] 3 [KΩ] Therefore, if the resistance value required by the gate protection device 30 shown in FIGS. 2A and 2B is selected as approximately 2 [KΩ], the The impurity concentration regions 33', 33'' have a concentration of approximately 3×10 ¹⁹ particles/cm, and the contact holes 36, 37 have an area of 10
It is sufficient to design it so that [μ]×10[μ]. That is, in the gate protection device 30 formed as described above, the diffusion region 33 can function as a gate protection diode 33D, as shown in FIG. The ohmic contact resistance 33'R that can be formed between the electrodes 34 is
1 [KΩ], and the impurity concentration adjustment region 33'' and the aluminum wiring electrode 3
The ohmic contact resistance 33''R that can be formed between the ohmic contact resistors 33'R and 33''R can be formed as 1 [KΩ], and the combined resistance 33R of the ohmic contact resistors 33'R and 33''R is 2.
[KΩ]. Therefore, if the dimensions of the diffusion region 33 are reduced so that it functions only as a diode 33D, the dimensions of the gate protection device 30 will be
It can be made very small. Also,
The electrode wiring 34 is melted by inserting an ohmic contact resistor 33'R in front of the diode 33D as shown in FIG. 2C, so the current I is limited by the ohmic contact resistor 33'R. Things that can be washed away and things that can happen are no longer something that can happen. Note that the gate protection device 30 shown in FIG.
As shown in Figures A, B, and C, impurity concentration adjustment region 3
3', 33'' may be formed in different forms by other forming methods. That is, as shown in FIG. 3A, electrode contact holes 3 of electrode wirings 34, 35
6, 37 lower impurity concentration adjustment regions 33, 33
may be formed by an impurity diffusion method such that the surface concentration is about 3×10 ¹⁹ particles/cm ³ . They may also be formed by a doped oxide method to obtain the same conditions. Also, as shown in Figure 3B, if the diode breakdown voltage can be considered,
The impurity concentration adjustment regions 33' and 33'' may be integrally formed as a region 33 which functions as a diode region.Also, as shown in FIG. Input wiring electrode ³ of diffusion region 33 of ×10 ²⁰ /cm 3
The dimension of the contact hole 36 on the 4th side is 7 [μ]
×7 [μ], and the contact hole 3
If the surface concentration of only the lower side of 6 is approximately 3×10 ¹⁹ particles/cm ³ , then the resistance 33'R of approximately 2KΩ is applied on only one side.
It is possible to form a device having exactly the same effect as the gate protection circuit device 30 shown in FIGS. 2A, B, and C. Moreover, if the present invention is explained by other examples,
It will look like Figure 4 A and B. That is, the gate protection circuit device 50 shown in FIG. 4A includes the gates 43 of the P channel MOS transistor 41, the gate 43 of the N channel MOS transistor 42, which are arranged in a complementary manner as shown in FIG. 4B.
44 from abnormal voltages of several hundred volts or more, a diffusion region 53 of N conductivity type is formed in the P-well 52 of the N-type semiconductor substrate 51, and the diffusion region Contact holes 56 and 57 having predetermined dimensions are formed to obtain a desired contact resistance value in the portions from which the wiring electrodes 54 and 55 are taken out, and furthermore, contact holes 56 and 57 are formed in the portions from which the wiring electrodes 54 and 55 are taken out.
Immediately below 57, surface concentration adjustment regions 53', 53'' are formed by boron ion implantation.
The surface concentration of 3' and 53'' is based on the gate protection device 30 shown in FIGS. 2A, B, and C, so its explanation will be omitted, but it is predicted that it will change depending on the conditions. The gate protection device 50 formed in this manner has an ohmic contact resistor 53'R formed on the input signal side IN of the PN diode 53D constituted by the diffusion region 53, as shown in the equivalent circuit shown in FIG. 4B. Therefore, even in the complementary MOS transistor circuit, the heat generating current I that would flow through the diode 53D is absorbed by the resistor 53'R.
Since the current can be limited by the current, it is possible to particularly prevent the wiring electrode 54 from burning out. The gate of the complementary MOS transistor 40 can be protected by forming a P-type diffusion region 58 in the N-type semiconductor substrate 51 and making contact with the electrode wiring 55.
8D, and its gate protection effect is
This can be made even more reliable. In addition, in these complementary MOS transistor circuits, the contact resistors 53'R and 53''R mentioned above
It also has the effect of effectively protecting against the latch-up phenomenon that occurs in complementary MOS circuits. In other words, in the complementary MOS integrated circuit device, due to its structure, P-well 52, P-well 52
A source region (not shown) formed in the substrate 58 and a source region (not shown) formed in the substrate 58 form a structurally parasitic PNPN junction or
An NPNP junction is formed, and the PNPN junction and NPNP junction constitute an N-gate type or P-gate type parasitic thyristor.
Therefore, for example, if an excessive current flows into the input, a trigger signal will be input to the P-well 52 or the base 51, so that the source of the base 51 will be A large current will flow into the area (not shown). A so-called latch-up occurs. Therefore, large currents flowed through these current paths (power lines), causing aluminum wiring to burn out. However, according to the present invention, the overcurrent from such an input is reduced by the ohmic contact resistors 53'R and 53''R as current limiting resistors, so the current is reliably reduced and latch-up does not occur. As a result, the aluminum wiring of the power supply line will not be burnt out.As described above, according to the present invention, this problem occurs because the gate protection device used to be only a diffused resistor (diode). A current limiting resistor is installed in front of the diffused resistor to replace the burnt out aluminum wiring that was previously used.In other words, an ohmic contact current limiting resistor field of, for example, several kilohms is attached to the input contact part of the diffused resistor area. The current is reduced by the current limiting resistor, making it possible to completely protect the aluminum from burning out.Furthermore, according to the present invention, the area of the gate protection device can be significantly reduced, especially for the resistor part. That is, gate protection is generally formed by a combination of a diode and a resistor, but in this application, the resistor can be formed by an ohmic contact resistor, so the area is only the contact area. Therefore, in the present invention, all the base resistance parts such as conventional diffused resistors can be removed.Furthermore, in the present invention, when the structure is mounted in a complementary MOS integrated circuit device as it is, the gate It is effective not only for protection but also against latch-up. In other words, latch-up can melt the aluminum wiring due to the on-current that flows when the parasitic thyristor turns on as mentioned above. These on-currents can be limited by contact resistance.As described above, we have been able to provide an integrated circuit device having a gate protection circuit device that exhibits numerous effects. It is clear that the present invention may be modified not only from the embodiments provided herein but also within the scope of the claims. It is suitable for sharing with other gate protection circuits, for example.

[Brief explanation of the drawing]

Figure 1A is a plan view showing the main parts of a MOS integrated circuit having a gate protection circuit device using a conventional resistor, and B is a cross-sectional view taken along -' from the plan view of A.C is an equivalent view of A and B. Circuit diagram, D is an equivalent circuit diagram pointing out the problems of the device shown in A and B, Fig. 2 A
1 is a plan view of a MOS integrated circuit device having a gate protection circuit device according to an embodiment of the present invention, B is a sectional view of A taken along the - line, and C is an equivalent circuit diagram of the device shown in A and B. , Figure 3 A, B, and C are
FIG. 4A is a partial sectional view of a partially modified version of FIGS. 2A and B, FIG. This is an equivalent circuit of A. 1, 21, 51... semiconductor substrate, 2, 22...
Source region, 3, 23...Drain region, 4, 2
4... Gate insulating film, 9, 29... Gate electrode,
7, 27... Source electrode, 8, 28... Drain electrode, 14, 15, 34, 25... Wiring electrode, 1
3, 33, 53...diffusion area, 33', 33'', 3
3, 33〓, 53', 53''...Surface concentration adjustment region, 33'R, 33''R, 53'R, 53''R...Contact resistance.

Claims (1)

[Claims] 1. A semiconductor substrate, a pair of source and drain regions formed within the semiconductor substrate, a gate insulating film formed between the source and drain regions, and a gate electrode formed on the gate insulating film. , a source electrode/drain electrode formed in the source region/drain region, a diffusion region formed in the semiconductor substrate, and a first wiring for connecting one end of the diffusion region to a gate input signal source. an electrode, and a second wiring electrode for connecting the other end of the diffusion region to the gate electrode, and a high-resistance ohmic electrode is provided in at least one of the contact regions of the first and second wiring electrodes. An integrated circuit device characterized by having a contact resistance.