JPS61187060A - Input/output controller - Google Patents

Abstract

PURPOSE:To perform the operation at a high speed by transferring data of a cache memory part or data, which is obtained by selecting an input/output device through a subordinate-side transfer part, according as data exists or does not exist in the cache memory part. CONSTITUTION:If a channel adapter CA refers to a cache memory part 3 in response to the access request of a CPU/CHL to discriminate the presence of requested data in a cache memory 4, a device adapter DA can execute another processing to a DASD during the data transfer between the cache memory 4 and the CPU/CHL. If the absence of requested data in the cache memory 4 is discriminated, a device is selected through the device adapter DA, and the device adapter DA transfers one-track components of data to the cache memory 4 by the staging operation, and another processing can be performed after requested data out of this data is transferred to the CPU/CHL; and thus, a host-side a bus and a subordinate-side bus are operated in parallel independently of each other.

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be explained in the following order.

Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Embodiment (A) Description of the configuration of the first embodiment of the input/output control device (
(Fig. 2, Fig. 3, Fig. 4, Fig. 5) (B) Explanation of the overall operation of the input/output control device (Fig. 6) CC) Explanation of the DA and device selection operation (Fig. 7) (D ) Explanation of staging operation (Figure 8) (E) Explanation of hit selection operation (Figure 9) (F) Explanation of cache operation (Figure 10, Figure 1)) (G) Description of normal read/write operation Explanation (FIG. 12) (H) Explanation of the second embodiment of the input/output control device (FIG. 13) Effects of the invention [Field of industrial application] The present invention is applicable to the upper side such as a CPU and the D A S D ( Dir
ectAccess Storage Device)
Regarding input/output control devices that are installed between multiple input/output devices such as the The present invention relates to an input/output control device that transfers data of an input/output device from a cache memory to a higher-level side without any processing.

In a computer system, data required by a central processing unit (hereinafter referred to as CPU) is held in an input/output device, and the CPU obtains data from the input/output device as necessary.

Such data exchange is performed by an input/output control device installed between the input/output device and the CPU.
In response to an access request from U, the input/output control device obtains data from the input/output device and transfers it to the CPU.

As such an input/output system, D.A.S.D.
(Direct Access Storage De
vice) subsystem is widely used, and DAS
The D subsystem is provided with a plurality of magnetic disk devices as input/output devices.

In recent years, input/output systems have been provided in which an input/output control device is provided with a cache memory to speed up access.

[Conventional technology]

Figure 14 is a configuration diagram of a conventional DASD subsystem, showing input/output control devices (hereinafter referred to as controllers) CT and DASD.
ASD9 is connected. The controller CT is composed of a pair of directors (control unit + DiR0, DIRI, and a cache memory unit CA having a cache memory CM) each connected to a channel CHL of the CPU, and each director DIRO5DIRI has an upper side (CP
U/CHL) and DASD9 and cache memory section CA
Automatic transfer mechanism ADTO, AD that transfers data between
A TI is provided for each. On the other hand, each DASD9 is connected to an adapter A connected to the director DIROSDIR1.
It consists of PO1API and n magnetic disk devices (hereinafter referred to as devices) 90 to 9n connected to both adapters APO1API by data lines 1) and j22, and each adapter APO and API is controlled by an adapter control unit C0NTO1.
CONTI, exclusive control memory MEMO1MEM1, and each device 90 to 9n and control line β3,
The E4 is configured to exchange control signals such as interrupts with the adapters APO and API.

Therefore, each device 90 to 9n has both adapters APO1A
The device 90 is configured to be so-called cross-called by the PI, that is, the director ADTO, ADT1.
~9n, the director DIRO-adapter APO path and the director DIR1-adapter API path.
accessed by one path.

In such a conventional DASD subsystem, when the upper side issues an access request to the director DrRO (or DIRI), the director DIRO (or DIRI) stores the request record of the requested device in the cache memory section CA. Also check whether the requested device is prohibited from being used by another host using the exclusive control memories MEMO and MEMO of the adapter APO1API.
Check by referring to MI, and if the use is not prohibited and there is a request reference in the cache memory section CA, the automatic transfer mechanism ADT1 of the director DIRI transfers the request from the cache memory CM of the cache memory section CA as shown by arrow Y. A so-called cache operation is performed to transfer the record to the upper side.On the other hand, when the requested record does not exist in the cache memory section CA and its use is not prohibited, for example, the director D
The automatic transfer mechanism ADTO of the IRO selects the requesting device (for example, 90) via the adapter APO, reads one track worth of data including the request record as shown by arrow X in the figure, and
Transfer to cache memory section CA, cache memory C
One track worth of data is stored in M, and only necessary requested records are transferred to the upper side as indicated by arrow X' in the figure. A so-called staging operation is performed. Therefore, the records included in the tracks stored in the cache memory CM are subsequently given to the upper side by the cache operation described above. This cache memory CM is generally composed of high-speed semiconductor memory, and its capacity is, for example, 4
If the storage capacity is set to be as large as M bytes to 32 Mbytes, the majority (for example, 80%) of access requests from the upper side will be performed by cache operation, and high-speed operation will be possible.

[Problem that the invention seeks to solve]

In an input/output system having such a cache memory CM, each of the automatic transfer mechanisms ADTO and ADTl of each director DIRO1DIRI performs upper side transfer between the cache memory CM and the upper side, and lower side transfer between the DASD9 and the cache memory CM. However, during the transfer between the upper side and the cache memory CM, the transfer between the DASD 9 and the cache memory CM is not possible, and similarly, until the transfer between the DASD 9 and the cache memory CM is completed, the transfer between the upper side and the cache memory CM is not possible. There was a problem in that high-speed operation was difficult because data could not be transferred to and from the computer. In addition, for each access request from the upper side, the exclusive control memory MEMO of the DASD9 adapter is
, MEMI, when the lower path to DASD9 is not free (that is, during staging operation),
Even if there is data in the cache memory CM, it cannot be transferred to the upper side, making it difficult to operate at higher speeds.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output control device capable of speeding up the operation by allowing the upper path and the lower path to independently transfer data.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In Fig. 1(A), the same parts as those shown in Fig. 14 are indicated by the same symbols, and 1a and 1b are upper-side transfer units, respectively, and are connected to the upper-layer side (CPU/CHL). , which are connected to a cache memory section, a lower transfer section, and a table storage, which will be described later, and transfer requested data to the upper side according to an access request from the upper side. 2a and 2b are lower transfer sections, respectively, and DASD9 adapter ap
O1API), the upper transfer units 1a and 1b, and a cache memory unit 3 to be described later, which performs data transfer by staging operation with the DASD 9 and the cache memory unit 3, and data transfer to the upper transfer units 1a and 1b; 3 is a cache memory section, 4 is a cache memory, and the upper transfer section 1a, 1b or the lower transfer section 2a, 2
The cache memory section 3 controls data reading and storage in the cache memory 4 according to the instruction b, and the table strange 5 is connected to the upper-side transfer sections 1a and 1b, and is connected to the exclusive control memory I of the above-mentioned adapter APO1 API.
It stores the exclusive control table stored in JMEMO1MEM1.

Therefore, in the present invention, compared to the conventional configuration, the transfer mechanism is divided into upper transfer units 1a, lb and lower transfer units 2a, 2b, and each transfer unit 1a, 1b, 2a, 2b has a cache memory. 4 and DASDQ
The difference is that the exclusive control table that existed in the adapter APO1API is provided in the input/output control device CT, and is placed under the control of the upper transfer units 1a and 1b.

[Effect]

In the present invention, the upper transfer unit (hereinafter referred to as channel adapter CA)
Since the lower side transfer units (hereinafter referred to as device adapters DA) 2a and 2b can perform transfer operations independently, for example, as shown in the diagram illustrating the principle operation in FIG. 1(B),
In response to an access request from the CPU/CHL, the channel adapter CA refers to the cache memory section 3 and determines that the requested data is present in the cache memory 4 (referred to as a hit).
During data transfer between cache memory 4 and CPU/CHL, device adapter DA connects DASD to
9, and in response to the access request from the CPU/CHL, the channel adapter CA refers to the cache memory unit 3 and determines that there is no requested data in the cache memory 4, which is called a miss. A device is selected via the device adapter DA, and the device adapter DA transfers one track worth of data to the cache memory 4 through a staging operation, and transfers the requested data to the CPU/CH.
The period tl in the figure after transfer to L is free and other processing (
For example, cache operations between the cache memory 4 and the CPU/CHL can be performed, and therefore, parallel operations can be performed independently on the upper path and the lower path.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

(A) Description of the configuration of the first embodiment of the input/output control device.

FIG. 2 is an overall block diagram of the first embodiment of the present invention.

Components that are the same as those shown in FIG. 1 are indicated by the same symbols, and 6 is a common bus. Device adapters 2a and 2b, the configuration of which will be described in detail in FIG. The common bus 6 is used in a time-division manner to exchange data. 40 is a driver/receiver, which is a driver for sending data from the cache memory 4 to the common bus 6, and a receiver for receiving data from the common bus 6; 41 is a shared storage control unit; The track buffer described later is connected to the common bus 6.
This is a control unit for time-divisionally multi-accessing in response to access requests from other units via the controller, and has a port unit 41a and a register group 41b, and 42 is a track buffer, which is a high-speed, large-capacity IC. It is composed of memory, and its capacity is, for example, between 4 MB and 32 MB, and the DA is
Data read from the SD9 device is stored in track units. For example, one track is stored in the HA.
(home address), RO-C (count section of record 0), RO-D (data section of record O), and the following are similarly stored as Rn C- and Rn-D. 50 is a driver/receiver, which is a driver for the table storage 5 to send data to the common bus 6, and a receiver for receiving data from the common bus 6; 51 is a table storage control section, which allows the table storage 5 to send data to the common bus 6; 52 is an ECC circuit that controls access to shared triples (described later) based on memory access requests and reads and writes tables;
53 is a sure table that performs error checking (parity check) of data to the shared triple and data from the shared table, and is composed of a memory that stores shared control information. It has tables 53a and 53b, a progress table 53c that stores the progress status of the operation of each part, and an executing command area 53d, and the selection exclusive control table indicates which device adapters 2a and 2b are currently using. module selection table 53a and DASD 9 that store control information of the device adapters 2a and 2b.
The device selection table 53b indicates whether each of the devices 90 to 9n is in use, reserved, or selected as a hit. Therefore, in this embodiment, both channel adapters 1a, 1b can select any device adapter 2a, 2b to access the device of DAS'D9, and each channel adapter 1a, 1b can access the device of DAS'D9.
1b can transfer data to and from the cache memory 4 under the control of the cache processor 3 via the common bus 6 without the intervention of the device adapters 2a and 12b, and similarly, each device adapter 2a and 2b can also transfer data without the intervention of the channel adapters 1a and 1b. Data can be transferred to and from the cache memory 4 via the common bus 6 under the control of the cache processor 3. Further, the common bus 6 is used in a time-division manner, and the channel adapters 1a, 1b and device adapters 2a, 2b can each transfer data to and from the cache memory 4 independently and in a time-division manner.

Next, the configuration of channel adapters (CA) la and b will be explained.

FIG. 3 is a block diagram of an embodiment of the channel adapter (upper transfer unit) configured in FIG. 2. In the figure, 10.15 is a driver/receiver, the driver/receiver 10 is for exchanging commands/data with the common bus 6, and the driver/receiver 15 is for exchanging commands/data with the CPU/C) (L). 1) is a bus control unit which acquires control of the common bus 6 as necessary and controls responses to and from the common bus 6; 12 is a data buffer; Driver/receiver 10. 13 is a data buffer control unit that temporarily stores commands/data from 15. 13 is a data buffer control unit that performs data transfer including buffering and controls the data buffer 12. 14 is a channel interface control unit. 16 is a microprocessor (hereinafter referred to as MPU), which controls the response of the channel interface for exchanging command data with the CPU channel (CHL). 17 is a control storage which executes a cache operation, a device adapter selection operation, etc., which will be described later, according to the program; a control program (microinstruction) necessary for the operation of the MPU 16;
It stores parameters, etc. (18 is an MPU bus, and the MPU 16 exchanges commands/data with the control storage 17, channel interface control section 14, cheetah buffer control section 13, and bus control section 1). and 19a, 19
b and 19c are internal buses, which respectively include the driver/receiver 15 and the channel interface control unit 14;
Channel interface control section 14, data buffer control section 13, driver receiver 10, data buffer control section 13, and bus control section 1)
It is for connecting.

To explain the basic operation of the configuration in Figure 3, the CPU/CHL
Commands/data from the internal bus 19a are sent to the channel interface control section 14 via the driver/receiver 15, and then sent to the MPU via the MPU bus 18.
16 and stored in the data buffer 12 from the data buffer control section 13 via the internal bus 19b. In addition, commands/data from the common bus 6 are given to the internal bus 19c via the driver/receiver 10 to the rebus control section 1) and the data buffer control section 13, and from the bus control section 1) via the MPU bus 18 to the MPU bus 18.
The information is notified to the PU 16 and stored in the data buffer 12. The MPU 16 reads commands/data supplied from the CPU/CHL stored in the data buffer 12 and the common bus 6 from the data buffer control section 13 via the MPU bus 18, analyzes them, and executes necessary processing.

On the other hand, in order to send commands/data to the CPU/CHL, the MPU 16 sends commands/data to the channel interface control unit 14 via the MPU bus 18, or the data buffer control unit 13 is sent to the MPU
The command data in the data buffer 12 is activated via the bus 18 and sent to the channel interface control unit 14, and then sent from the driver/receiver 15 to the cpU/CHL via the internal bus 19a. Also, common bus 6
Hecomant/To send data, MPU 16 is MPU
When the bus controller 1) is commanded to acquire bus control via the bus 18 and the bus controller 1) acquires control of the common bus 6,
Command/data to data buffer control section 13
is read from the data buffer 12 and sent to the common bus 6 from the driver/receiver 10 under the instruction of the MPU 16.

Combining the above makes it possible to send data from the CPU/CHL to a common bus and vice versa.

Next, the configuration of the device adapters (DA) 2a and 2b will be explained.

FIG. 4 is a block diagram of an embodiment of the device adapter (lower side transfer section) configured in FIG. 2. In the figure, 20.25 is a driver/receiver, the driver/receiver 20 is for exchanging commands/data with the common bus 6, and the driver/receiver 25 is for exchanging commands/data with the adapter of DASD 9. 21
22 is a bus control unit that acquires control of the common bus 6 and controls responses to the common bus 6. 22 is a data buffer that temporarily receives commands/data from the driver/receiver 20. 23 is a data buffer control unit that performs data transfer including buffering and controls the data buffer 22; 24 is an adapter interface control unit;
For response control of the adapter interface for exchanging command data with the SD9 adapter, 2
6 is a microprocessor (hereinafter referred to as MPU);
27 is a control storage that controls the device according to the selection operation of channel adapters la and lb and executes staging operation, write cache operation, etc. by a program. ), parameters, etc. are stored, and 28 is an MPU bus, in which the MPU 26 communicates with a control storage 27, an adapter interface control section 24, a data buffer control section 23, and a bus control section 21, and command/
It is used to exchange data, 29 a, 29
b and 29c are internal buses, which connect the driver/receiver 25 and the adapter interface control section 24, the adapter interface control section 24 and the data buffer control section 23, and the driver receiver 2o, the data buffer control section 23, and the bus control section 21, respectively. It is for the purpose of

To explain the basic operation of the configuration shown in FIG. 4, commands/data from the DASD 9 (its adapter) are given to the adapter interface control unit 24 from the internal bus 29a via the driver/receiver 25, and are notified to the MPU 26 via the MPU bus 28. At the same time, the data is stored in the data buffer 22 from the data buffer control section 23 via the internal bus 29b. Also, from the common bus 6 command/
Data is transferred via the driver/receiver 20 to the internal bus 29c.
The data is given to the bus control unit 21 and the data buffer control unit 23 from the bus control unit 21 via the MPU bus 28, and is notified to the MPU 26 and stored in the data buffer 22. The MPU 26 reads commands/data stored in the data buffer 22 and commands/data applied from the common bus 6 from the data buffer control unit 23 via the MPU bus 28, analyzes them, and executes necessary processing.

On the other hand, in order to send commands/data to the DASD 9 (adapter), the MPU 26 sends commands/data to the adapter interface control section 24 via the MPU bus 28, or the MPU 26 sends commands/data to the adapter interface control section 24 via the MPU bus 28,
3 via the MPU bus 28 and the data buffer 22
The command data in the DASD 9 is sent to the adapter interface control section 24, and sent from the driver/receiver 25 to the DASD 9 (an adapter thereof) via the internal bus 29a. Also, in order to send commands/data to the common bus 6, the MPU 26 sends commands/data to the bus control unit 21 via the MPU bus 28.
The bus control unit 21 orders the common lotus 6 to acquire control over the lotus.
When control is acquired, the data buffer control unit 23 reads commands/data from the data buffer 22 under instructions from the MPU 26 and sends them to the common bus 6 from the driver/receiver 20 .

Next, the configuration of the cache processor 3 will be explained.

FIG. 5 is a block diagram of an embodiment of the cache processor 3 in the configuration shown in FIG.

30 is a driver/receiver for exchanging commands/data with the common lotus 6;
1 is a bus control unit that acquires control over the common bus 6;
A cache control table 32 is used for response control with the common bus 6, and is composed of a memory that stores information for cache memory control, and includes device names and track names of data stored in the cache memory 4. an extent table 32c for storing device names and dock names that are prohibited from being stored in the cache memory 4 (this is referred to as no cache), and an LRU table 32b for allocating space in the track buffer 42. those with
33 is a cache control accelerator section;
Hardware for speeding up the search of the hash table 32a and extent table 32c of the cache control table 32, 34 is a microprocessor (hereinafter referred to as MPU);
and search and update processing of the extent table 32C,
Controls port allocation and allocation (space allocation of cache memory 4) for cache memory 4,
35 is a control storage that stores control programs (micro instructions), parameters, etc. for the operation of the MPU 34; 36 is a control storage for the MPU 34;
37a and 37b are internal buses through which the MPU 26 exchanges commands/data with the bus control section 31, cache control accelerator section 33, cache control table 32, and control storage 35; This is for connecting the cache control table 32, driver/receiver 30, and bus control section 31.

To explain the basic operation of the configuration in FIG. 5, commands/data from the common bus 6 (judgment request from channel adapter CA, port request, cache allocation request, termination notification from device adapter DA) are sent to the bus control unit 31. The signal is supplied to the MPU 34 via the internal bus 37b, and is further supplied to the MPU 34 via the MPU bus 36. The MPU 34 analyzes the given command/data and creates a hash table 32.
a and the extent table 32C (instructing the accelerator unit 33 to quickly search the versh table 32a and extent table 32c), updating the versh table 32a, the port of the cache memory 4,
Register allocation processing and allocation processing using the LRU table 32b are performed, and the results are given to the bus control unit 31 via the MPU bus 36, and sent from the driver/receiver 30 to the common bus 6 via the internal bus 37b.

(B) Explanation of the overall operation of the input/output control device.

Next, the overall operation of the embodiment configuration shown in FIGS. 2 to 5 will be explained with reference to the overall operation diagram shown in FIG. 6.

First, assume that the command chain issued from the CPU is as follows.

eek Set File Mask Set Sector 1? ead Data /Write KD■C
PCI to channel adapter CA via channel CHL
5eek”, SetFM” to “Set 5ectO”
r'' is issued and stored in the data storage sofa 12 in the channel adapter CA.

■When the channel adapter CA receives up to the "Set 5ector" command, the MPU 16 determines whether or not the access request track included in the command received to the cache processor (CP) 3 via the common lotus 6 exists on the cache memory 4. issue a request for judgment.

In the cache processor 3, when the MPU 34 decodes the determination request, the cache control accelerator unit 33
The cache table 32a and extent table 32C of the cache control table 32 are searched at high speed, and the access request trunk is located in the cache memory 4.
whether it exists in the trunk buffer 42 of the
(rMiss, Miss) or the above-mentioned [Noki middle class: x, J
(no cache), and notifies the MPU 34.
The MPU 34 notifies the channel adapter CA of this via the common bus 6.

(2) In the channel adapter CA, the MPU 16 examines the notified determination result, and if it is a "hit", proceed to step (2), if it is a "miss", proceed to step (2), and if "no cache", proceed to step (2).

■In case of "mistake", the MPU of channel adapter CA
16 reports the channel end (CE) status from the driver/receiver 15 to the channel CHL via the channel interface control unit 14.

0 Next, the channel adapter CA selects an empty device adapter DA and a request device, which will be described later in FIG.
A and device selection.

Furthermore, if the free device adapter DA and the requested device are successfully selected, a staging operation, which will be described later in FIG. 8, is performed and the process ends. The staging operation is to transfer one track worth of data including the requested record from the requesting device to the cache memory 4, and to transfer the requested record to the requesting channel adapter CA.

■On the other hand, in the case of "hint", device adapter DA
Since it is not necessary to select a device and a device, the MPU 16 of the channel adapter CA reports the channel end 1° (CE) status and device end (DE) status to the channel CHL from the driver/receiver 15 via the channel interface control unit 14. do.

(2) Next, the channel adapter CA performs a hint selection operation to check whether the requesting device is in reserve (described later in FIG. 9). Reserve means other CPU
prohibits access to that device.

Furthermore, if the requesting device is not in reserve and the hit selection is successful, a write cache operation (described later in FIG. 10) or a read cache operation (described later in FIG. 1) is performed, and the process ends. The write cache operation rewrites the contents of the requested record in the cache memory 4, selects the device that stores the record, and rewrites the contents of that record, and the read cache operation rewrites the contents of the requested record in the cache memory 4. This is to read the contents of a record.

■In the case of "no cache", channel adapter C
The MPU 16 of A sends a channel end (CE) signal to the channel CHL from the driver/receiver 15 via the channel interface control unit 14 as in the case of "miss".
Report status.

0 Next, the channel adapter CA performs DA and device selection, which will be described later in FIG. 7, similarly to step (2).

Furthermore, if the free device adapter DA and the requested device are successfully selected, a normal read or write operation, which will be described later with reference to FIG. 12, is performed and the process ends.

Next, the DA/device selection operation, staging operation, hit selection operation, write or read cache operation, and normal read/write operation will be explained.

(C) Description of DA and device selection operation.

FIG. 7 is an explanatory diagram of the DA and device selection operation.

(C-1) The channel adapter CA does not sequentially output the module table 53a of the table storage 5 via the common lotus 6 according to instructions from the MPU 16. The module table 53a stores flags indicating whether each device adapter 2a, 2b is in use. module table 53
The contents of a are transmitted to the driver/receiver 50 via the common bus 6.
The data is read out by the table storage control section 51 according to an instruction given by the channel adapter CA, and is given to the channel adapter CA from the common bus 6 via the driver/receiver 50.

(C-2) In channel adapter CA, its MPU16
checks the contents of the module table 53a to see if there is a free device adapter DA.

If there is no free device adapter DA, the device waits for release from the busy state until the device adapter DA becomes free.

(C-3) If there is a free device adapter DA, the channel adapter CA reads the device table 53b of the table storage 5 via the common bus 6 according to the instruction from the MPU 16. The device table 53b includes DAS
A flag indicating whether each device 90 to 9n (see FIG. 14) of D9 is in use, a flag indicating whether it is in reserve, and a flag indicating whether hit selection is in progress are stored. The contents of the device table 53b are transmitted to the driver/driver via the common bus 6.
The data is read by the table storage control section 51 according to an instruction given by the channel adapter CA from the receiver 50, and is given to the channel adapter CA from the common bus 6 via the driver/receiver 50.

(C-4) In channel adapter CA, its MPU16
examines the contents of the device table 53b, and the CPU
Check whether the device requested by the HL is reserved and selected (used) by another channel adapter.

If the requested device is being reserved or selected, the access request is placed in a debusy wait state until the reservation is released or the selection is released.

(C-5) If the requested device is not reserved and selected, channel adapter CA
U16 connects the module table 53a and device table 53b of the control storage 5 via the common bus 6.
Update and register the usage flag. That is, the usage flag of the selected device adapter DA in the module table 53a is set, and the usage flag of the requested device is set in the device table 53b.

(C-6) Next, the channel adapter CA connects the common bus 6
The device adapter DA instructs the selected device adapter DA to inquire whether the requested devices 90 to 9n are in operation. If each device 90 to 9n is not used for a certain period of time, the magnetic disk and magnetic head will stick together and will not operate properly. Therefore, a patrol sequence etc. in which a seek operation is performed under the control of the devices 90 to 9n themselves may be performed. Yes, it is checked whether this patrol sequence is in progress, and if the device is in operation, it waits for the busy state to be released until the device operation is canceled.

(C-7) If the device is not in operation or disappears,
Channel adapter CA is the selected device adapter DA
and obtains a path to the requesting device, the actual selection is successful,
Finish DA and device selection.

(D) Description of staging operations.

FIG. 8 is an explanatory diagram of the staging operation.

(D-1) As mentioned above, when the channel adapter CA successfully selects the device adapter DA and the requesting device,
In the channel adapter CA, the MPU 16 issues a cache allocation request to the cache processor (CP) 3 via the common bus 6 to allocate space in the cache memory 4, that is, the track buffer 42.

(D-2) In cache processor (CP) 3, MP
The U34 decodes this, performs allocation processing, and stores the LRU table 32a of the cache control table 32.
The contents of the track buffer 42 are checked using the LRU algorithm, and allocation information indicating the space is sent to the table storage 5 via the common bus 6.
give to

In the table storage 5, the table storage control unit 51 receives this via the driver/receiver 50, and the progress status table 53c of the shared triple 53
Store it in .

(D-3) Next, the channel adapter CA
16 provides operation information ICW indicating the contents of the staging operation to the table storage 5 via the common bus 6. Operation information ■CW consists of staging command, command issuing path (channel adapter), seek address, sector information, etc. In table storage 5, driver/
The table storage control unit 51 receives this via the receiver 50 and stores it in the command area 53d of the share triple 53.

(D-4) Next, the channel adapter CA
16 selects the device adapter DA via the common bus 6
Then, an operation start instruction including the address of the operation information rcw of the table storage 5 is issued.

(D-5) As a result, the device adapter DA reads the operation information ICW of the corresponding address in the shared table 53 of the table storage 5 via the common bus 6, and
5eek, Set 5e to the above request device of SD9
ctor (sector value "0") is issued.

The channel adapter CA is released when the instruction in step (D-4) is issued, and other operations can be performed, and the device adapter DA is also released when the instruction is issued to the device.

(D-6) The device starts its operation and raises an interrupt to the device adapter DA as it approaches the designated sector "0". As a result, the device adapter DA reads the operation information ICW in the shared table 53 of the table storage 5 via the common bus 6. This device adapter DA does not need to be the same as the device adapter DA that instructed the previous device.

Further, the device adapter DA reads the allocation information of the progress table 53C in the shared table 53 of the table storage 5, learns the allocated space of the track buffer 42, and starts staging from the home address (HA) sent from the device. That is, the device adapter DA sequentially gives the home address HA (RO-C, RO-I)- given by the device to the cache memory 4 via the common bus 6, and stores the track buffer 42.
Write in the allocated space. At the same time, the device adapter DA writes the staging progress to the progress table 53C in the shared triple 53 of the table storage 5 via the common bus 6.

While staging is performed in this way, when the device adapter DA approaches the command specified sector value,
First, the interrupt reason (approaching the designated sector) is sent to the module table 53a in the shared table 53 of the table storage 5 via the common bus 6, and then sent to the vacant channel adapter CA via the common bus 6. Raise interrupt for channel recombination.

(D-7) The interrupted channel adapter CA reads the interrupt reason from the module table 53a in the shared table 53 of the table storage 5 via the common bus 6, and when it learns that it has approached the designated sector, the channel adapter CA
Recombination request Req In and device end (D
E) Notify status.

(D-8) The channel CHL issues the next command, 5search 10 Eq command, and when the channel adapter CA receives this, the progress table 53c in the shared table 53 of the table storage 5 is sent via the common bus 6. The progress status is read and updated, the staging is synchronized, and the command transfer mode is written to the progress status table 53c via the common bus 6.

(D-9) The device adapter DA reads the contents of the progress table 53c via the common bus 6, and
Perform mode synchronous transfer.

That is, data from the device is transferred to the cache memory 4 via the common bus 6, and the channel adapter CA
Also forward it to

(D-10) On the other hand, channel adapter CA receives data CCHHR (cylinder address, head address, record number) from channel CHL, and receives data from device adapter DA (here, count section R2-C of record 2). Compare with. If there is a mismatch as a result of this comparison, it is not the requested record, so channel adapter CA returns the channel end (CE) and device end (DE) status to channel CHL, and then 5search again.
Receives 10Eq command.

(D-1)> When the device adapter DA reads the contents of the progress table 53c again via the common bus 6, the command transfer mode remains unchanged, so it continues the synchronous transfer in FORK mode, and the device following R2-C Record 2 from
The data portion R2-D of is transferred to the cache memory 4 and channel adapter CA via the common bus 6. record 2
is not a request record, so in channel adapter CA,
R2-D is read and discarded. and device adapter D
A transfers the next counting unit R3-C from the device to the cache memory 4 and channel adapter C via the common lotus 6.
Transfer to A. In channel adapter CA, step (
Similar to D-10), compare the channel CHL to CCHHR and the next count section, and if it is determined that they match, it is determined that it is a request record, and the status modifier STM, channel end (CE), and device end (DE) status is sent to the channel CHL. and receives the next command from channel CHL.

(D-12) The next command is a write command (Writ
e DAT^), the command transfer mode (Wrtte) is set in the progress table 53c of the table storage 5 via the channel adapter communication bus 6.

The device adapter DA reads the contents of the progress table 53C, and when it learns that it is a write operation, changes to the write mode. When write data R3-D of record 3 from channel CHL is transferred from channel adapter CA via common bus 6, device adapter DA writes write data R3-D to the device. At the same time, write data R3-D is also written to the track buffer 42.

-7. If the next command is a read command (Read Data) as shown in parentheses in the figure, the channel adapter CA similarly sends the progress status table 53 via the common bus 6.
When the command transfer mode (Read) is set in c and the device adapter DA reads it via the common bus 6,
The data part R3-D of record 3 from the device is transferred to the cache memory 4 and channel adapter CA via the common bus 6 as indicated by the dotted line arrow in the figure, and then transferred to the cache memory 4 and channel adapter CA.
The data is further transferred to the channel CHL.

Then, the channel adapter CA resets the command transfer mode of the progress table 53C of the table storage 5 via the common bus 6 when the command chain ends (ends with Write DATA or Read Data). This frees the channel adapter CA and enables other processing.

(D-13) On the other hand, device adapter DA uses common bus 6.
Progress table 53c of table storage 5 via
Reads the contents of , checks the command transfer mode, and learns that the command transfer mode has been reset. Furthermore, if there are more records in the remaining read track of the device, the device adapter DA continues data transfer by staging to the cache memory 4, and when the staging of the last record on the track is completed, the device adapter DA is cache processor 3
is notified of the completion of staging via the common bus 6. As a result, the cache processor 3 uses the hash table 3
2a, the staged track is registered in the track buffer 42.

When the staging operation is completed in this way, the track buffer 42 of the cache memory 4 contains the CPU/CPU
Data for one track including the record requested by the HL is stored, and from then on, access to the record of the track is made to the cache memory 4. On the other hand, the CPU
/CHL can obtain a request record during staging if it is a read command, and can rewrite the request record in the device (and in the cache memory 4) if it is a write command.

(E) Explanation of hint selection operation FIG. 9 is an explanatory diagram of the hit selection operation.

(E-1) The channel adapter CA reads the device table 53b of the table storage 5 via the common lotus 6 according to instructions from the MPU 16.

The device table 53b contains, as described above, a flag indicating whether each device 90 to 9n of the DASD 9 (see FIG. 14) is in use, a flag indicating whether it is in reserve, and a flag indicating whether it is in selection. is stored. The contents of the device table 53b are read by the table storage control unit 51 from the driver/receiver 50 via the common bus 6 in accordance with instructions given from the channel adapter CA, and are provided from the common bus 6 via the driver/receiver 50 to the channel adapter CA. It will be done.

(E-2) In channel adapter CA, its MPUI
6 opens the contents of the device table 53b, and the CPU/C
It is checked whether the device requested by the HL is being reserved or being selected. Since the hit selection operation does not actually select the device, it is sufficient to check whether access to the data of the device is prohibited, whether the device is in reserve, and whether the device is being selected. If it is, it will wait for the busy to be released until the reserve or hit selection is cancelled. Also, check the usage status from other CAs to see if there is access to the same cylinder. If there is, you will have to wait.

(E-3) If the requested device is not reserved or hit selected, the MPU16
updates and registers the device table 53b of the table storage 5 via the common bus 6. That is, "hit selection" is written in the hint selection column of the requesting device in the device table 53b, and the cylinder address is registered.

As a result, the hit selection is successful and the hit operation ends.

(F) Explanation of cache operation.

In the case of a read cache operation, it is sufficient to simply read the contents of the cache memory 4, but in the case of a write operation, it is necessary to rewrite the contents of the device itself in addition to rewriting the contents of the cache memory 4.

First, the write cache operation will be explained using the 10th operation explanatory diagram.

(F-1) As mentioned above (hit selection is successful, CPU/
When the channel adapter CA receives 5 search 10 Bq from the CHL, its MPU 16 issues a vote request for the cache memory 4 to the cache processor 3 via the common bus 6.

As a result, the MPU 34 of the cache processor 3 decodes this and transfers some of the ports of the port section 41a of the shared strange control section 41 of the cache memory 4 and the registers of the register group 41b to the channel adapter C.
A is allocated for use, and sent to the cache memory 4 via the common bus 6, and a vote is allocated to the port section 41a of the shared storage control section 41 and register set-up of the register group 41b is performed.

As a result, the channel adapter CA acquires the vote and register of the cache memory 4, and multiple transfer via the common bus 6 becomes possible.

That is, the cache memory 4 can be accessed in a time-sharing manner even during the staging operation.

(F-2) Next, the channel adapter CA
16 issues a data transfer request to the cache memory 4 via the common bus 6. The data transfer request is sent to the track buffer 4.
Contains the start address and number of bytes of the request record in 2.

In the cache memory 4, the shared storage control unit 41 sets a data transfer request to the assigned register of the register group 41b, and transfers the data transfer request to the trunk buffer 42.
access. As a result, the track buffer 42 first outputs the requested code count section, for example, R3.
-C is read out and set in the assigned port of the port section 41a, and then transferred from the driver/receiver 40 to the channel adapter CA via the common bus 6.

(F-3) In channel adapter CA, channel CHL
The CCHHR sent from CCHHR and the transferred count part R3-C are compared, and if it is determined that they match, it is determined that it is a request record, and the status modifier STM is sent.

Channel end (CE) and device end (DE)
It returns the status to channel CHL and receives the next command from channel CHL.

(F-4) If the next command from channel CHL is a write command (Write D), channel adapter CA returns try status (Retry 5tat).
After returning the data (us) to channel CHL, DA and device selection operations are performed. That is, in the case of writing, it is necessary to rewrite the record in the device, so DA and device selection are performed.This operation is the same as the DA and device selection operation explained in section (C), so the explanation will be omitted. .

(F-5>Next, the channel adapter CA
16 provides operation information ICW indicating the contents of the write-through operation to the table storage 5 via the common bus 6. The operation information ICW consists of a write-through command, command issuing path (channel adapter), seek address, sector information, etc. In the table storage 5, the driver/
The table storage control unit 51 receives this via the receiver 50 and stores it in the command area 53d of the share triple 53.

(F-6) Next, the channel adapter CA
16 selects the device adapter DA via the common bus 6
Then, an operation start instruction including the address of the operation information ICW of the table storage 5 is issued.

(F-7) As a result, the device adapter DA reads the operation information ICW of the corresponding address in the shared table 53 of the table storage 5 via the common bus 6, and
5eek, Set 5e to the above request device of SD9
ctor (sector value is R3).

The channel adapter CA is released when the instruction in step (F-6) is issued, and other operations can be performed, and the device adapter DA is also released when the instruction is issued to the device.

(F-8) The device starts its operation and raises an interrupt to the device adapter DA when the sector value of the instructed sector R3 approaches. As a result, the device adapter DA transmits the operation information rcw in the shared table 53 of the table storage 5 via the common bus 6.
One after another. This device adapter DA does not need to be the same as the device adapter DA that instructed the previous device.

Then, the device adapter DA sets the interrupt reason (nearing the specified sector) in the module table 53a in the shared triple 53 of the table storage 5 via the common bus 6, and then sets the interrupt reason (nearing the specified sector) to the module table 53a in the shared triple 53 of the table storage 5. Raise an interrupt to adapter CA for channel recombination.

(F-9) The interrupted channel adapter CA reads the interrupt reason from the module table 53a in the shared triple 53 of the table storage 5 via the common bus 6, and when it learns that it has approached the designated sector, the channel adapter CA
Recombination request Req In and device end (D
E) Notify status.

(F-10) Channel CHL thereby issues the next command, writeD.

When the next command is a write command (Write D), the channel adapter CA sets the command transfer mode (Write) in the progress table 53C of the table storage 5 via the common bus 6, and then sends a synchronization command to the device adapter DA. via the common bus 6.

As a result, the device adapter DA performs an internal search by comparing the data count section from the device with the designated record R3. On the other hand, the channel adapter CA issues a port request in the same way as in step (F-1), and the cache processor 3 allocates a cache memory vote, performs register sesotoamplification, and acquires a port and a register.

(F-1)") When a match is obtained between the specified record R3 and the count section R3-C from the device in the internal search of the device adapter DA, the device adapter DA sends a synchronization command to the channel adapter CA via the common bus 6. This causes channel adapter CA to issue channel CH
Transfers write data R3-D from L to cache memory +J4 and device adapter DA via common bus 6,
The contents of the track buffer 42 of the cache memory 4 are rewritten, and the contents of the device are also rewritten from the device adapter DA.

When the command chain ends (Write D ends), the channel adapter CA sends a chain end notification to the device adapter DA via the common bus 6, and further resets the command transfer mode of the progress table 53C of the table storage 5. This frees the channel adapter CA and enables other processing. Further, in response to the chain end notification, the device adapter DA notifies the cache processor 3 of the write-through end via the common bus 6, updates the LRU table 32a, and ends the write cache operation.

Next, the read cache operation will be explained using the first) operation explanatory diagram.

(F-20) Similarly to step (F-1), the human selection is successful as described above, and 5earc is sent from the CPU/CHL.
When channel adapter CA receives h 10 EQ, its MPU 16 issues a vote request for cache memory 4 to cache processor 3 via common bus 6 .

As a result, the MPU 34 decodes this and the cache processor 3 transfers some ports of the port section 41a of the share strength control section 41 of the cache memory 4 and registers of the register group 41b to the channel adapter C.
A is allocated for use, and sent to the cache memory 4 via the common bus 6, and is allocated to the boat section 41a of the share strength control section 41 and register group 4.A. Performs register setup for Ib.

As a result, the channel adapter CA acquires the vote and register of the cache memory 4, and multiple transfer via the common bus 6 becomes possible.

That is, the cache memory 4 can be accessed in a time-sharing manner even during the staging operation.

(F-21) Next, channel adapter CA
U16 issues a data transfer request to cache memory 4 via common bus 6. The data transfer request includes the start address of the count section of the requested record in track buffer 42 and the number of hides.

In the cache memory 4, the share strength control unit 41 sets the data transfer request to the assigned register of the register group 41b, and transfers the data transfer request to the assigned register in the trunk buffer 4.
Access 2. As a result, the track buffer 42
From here, first, the count part of the request record, for example, R3.
-C is read out and set in the assigned port of the port section 41a, and then transferred from the driver/receiver 40 to the channel adapter CA via the common bus 6.

(F-22) In channel adapter CA, channel CH
The CCHHR from L and the transferred count part R3-C are compared, and if it is determined that they match, it is determined that it is a request record, and the status modifier STM and channel end (GE)
and device end (DE) status on channel CH
It returns to L and receives the next command from channel CHL.

(F-23> When the next command from channel CHL is a read command (Read D), the channel adapter CA issues a data transfer request from its MPU 16 to the cache memory 4 via the common bus 6.The data transfer request is sent to the track buffer. 42 includes the start address and number of bytes of the data portion of the request record.

In the cache memory 4, the share strength control unit 41 sends the data transfer request to the assigned register of the register group 41b, and transfers the data transfer request to the assigned register of the register group 41b.
access. As a result, the data section of the request record, for example, R3-D, is read from the track buffer 42, set in the allocated port of the port section 41a, and then transferred from the driver/receiver 40 to the channel adapter CA via the common path 6. be done.

(F-24) After further transferring this data part R3-D to channel CHL, channel adapter CA detects the end of the command chain and sends the channel end (CE) and device end (DE) status to channel CH.
After releasing the connection with channel CHL, the selection flag in the hit column of the device in the device selection table 53b of the table storage 5 is canceled, and the read cache operation is ended.

(G) Description of normal read/write operations.

FIG. 12 is an explanatory diagram of a normal read/write operation.

(G-1) As mentioned above, when the channel adapter CA successfully selects the device adapter DA and the requesting device,
The channel adapter CA has its MPU 16 connected to the common bus 6.
Operation information IBrcw indicating the contents of the normal operation is provided to the table storage 5 via the table storage 5. The operation information ICW is composed of a normal operation command, a command issuing path (channel adapter), a seek address, sector information, etc. In the table storage and ledge 5, the table storage control unit 51 receives it via the driver/receiver 50 and outputs the share command. - Store in the command area 53d of the pull 53.

Next, the channel adapter CA issues an operation start instruction including the address of the operation information CW of the table storage 5 to the device adapter DA selected by the MPU 16 via the common bus 6.

(G-2) As a result, the device adapter DA reads the operation information ICW of the corresponding address of the shared triple 53 of the table storage 5 via the common bus 6, and
5eek, Set 5e to the above request device of SD9
ctor (instruction sector value).

The channel adapter CA is released when the instruction in step (G-1) is issued, and other operations can be performed, and the device adapter DA is also released when the instruction is issued to the device.

(G-3) The device starts its operation and raises an interrupt to the device adapter DA as it approaches the designated sector. As a result, the device adapter DA reads out the operating information 1gicw in the shared triple 53 of the table storage 5 via the common bus 6. This device adapter DA does not need to be the same as the device adapter DA that instructed the previous device.

The device adapter DA analyzes the ICW, sends the interrupt reason (approaching the specified sector) to the module table 53a in the shared table 53 of the table storage 5 via the common bus 6, and then sends the interrupt reason (approaching the designated sector) to the module table 53a in the shared table 53 of the table storage 5 via the common bus 6. An interrupt is raised for channel adapter CA to recombine the channel.

(G-4) The interrupted channel adapter CA reads the interrupt reason from the module table 53a in the shared triple 53 of the table storage 5 via the common bus 6, and when it learns that it has approached the designated sector, the channel adapter CA
Recombination request Req In and device end (D
E) Notify status.

Channel CHL will now issue the next command, 5e.
After issuing the arch 10 Eq command and receiving it, the channel adapter CA writes the command transfer mode to the progress table 53c via the common bus 6.

The device adapter DA uses this progress table 53c.
The contents are read out via the common bus 6 and synchronous transfer is performed.

That is, data from the device is transferred to the channel adapter CA via the common bus 6.

(G-5) On the other hand, channel adapter CA 1 receives data CCHHR (cylinder address, head address, record number) from channel CHL, and receives data from device adapter DA (here, count section R2-C of record 2). ). If there is a mismatch as a result of this comparison, it is not the requested record, so channel adapter CA sends the channel end (GE) and device end (DE).
) returns the status to channel CHL and 5earc again
Receive hID Eq command.

(G-6) When the device adapter DA reads the contents of the progress table 53G again via the common bus 6, the command transfer mode remains unchanged, so the data section R2-D of record 2 from the device following R2-C is Clocking, not forwarding.

Device adapter DA then transfers the next count section R3-C from the device to cache memory 4 and channel adapter CA via common bus 6. Channel adapter CA uses channel CH as in step (G-5).
Compare CCHHR and the next count part from L, and if it is determined that they match, it is determined to be a request record, status modifier STM, channel end (CE) and device end (DE) status are returned to channel CHL, and the next one is sent from channel CHL. Receive commands.

(G-7) The next command is a write command (Wrjte
KD), the channel adapter CA is connected to the common bus 6.
Progress table 53C of table storage 5 via
Set the command transfer mode (Write) to

The device adapter DA reads the contents of the progress table 53c, and when it learns that it is a write operation, changes to the write mode. When write data R3-D of record 3 from channel CHL is transferred from channel adapter CA via common bus 6, device adapter DA writes write data R3-D to the device.

On the other hand, if the next command is a read command (Read Data) as shown in parentheses in the figure, the channel adapter CA similarly reads the progress status table 53 via the common bus 6.
When the command transfer mode (Read) is set to c and the device adapter DA reads it via the common bus 6,
The data part R3-D of record 3 from the device is transferred to the cache memory 4 and channel adapter CA via the common bus 6 as indicated by the dotted line arrow in the figure, and then transferred to the cache memory 4 and channel adapter CA.
The data is further transferred to the channel CHL.

Then, channel adapter CA ends the command chain (ends with Write KD or Read Data).
The command transfer mode of the progress table 53c of the table storage 5 is reset via the common bus 6. This frees the channel adapter CA and enables other processing.

The device adapter DA also checks the command transfer mode of the progress table 53c of the table storage 5 via the common bus 6, detects that it has been reset, and ends the process.

(■) Explanation of the configuration of the second embodiment of the input/output control device.

FIG. 13 is a block diagram of a second embodiment of the present invention.

In the figure, the same components as those shown in FIG. 2 are indicated by the same symbols, and lc and ld are channel adapters, respectively.
c and 2d are device adapters having the same configuration as device adapters 2a and 2b, and 9a is the first DA
SD, 9b is the second DASD, and each DAS
It has the same configuration as D9.

Compared to the first embodiment shown in FIG. 2, one DASD is added,
Accordingly, a device adapter 2C12d is provided, and a channel adapter IC1)d is also added. Therefore, the upper bus has four paths for channel adapters 1a to 1d, and the lower bus has four buses. Since the common bus 6 is used in this way, it is easy to add channel adapters and device adapters, and data can be transferred between any channel adapter and device adapter. Also, the channel adapter is either DASD9a,
You can also access 9b, which is extremely convenient. Note that the detailed configuration and operation of the second embodiment are the same as those shown in FIG. 2, so a description thereof will be omitted.

Any number of channel adapters or device adapters can be added, and the number is determined according to the system configuration.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, data can be transferred independently between the upper path and the lower path. Staging and write puncturing can be performed, and conversely, hint operations can be performed using the upper path when the lower path is used, so it is possible to improve the operating efficiency of the system.

In particular, since most of the accesses are on the upper side using the cache memory, by being able to access the cache memory even while the lower path is in use, the CPU access time can be greatly improved and the access time can be accelerated. It is possible to provide an input/output system that can keep up with the high-speed operation of the CPU.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of the first embodiment of the invention, Fig. 3 is an internal block diagram of the channel adapter in the configuration shown in Fig. 2, and Fig. 4 is the configuration shown in Fig. 2. Figure 5 is an internal block diagram of the cache processor in the configuration shown in Figure 2, Figure 6 is an explanatory diagram of the overall operation in the configuration shown in Figure 2, and Figure 7 is the DA/device selection in Figure 6. Figure 8 is a diagram explaining the staging operation in Figure 6. Figure 9 is a diagram explaining the human selection operation in Figure 6.
1) is an explanatory diagram of the read/write operation in FIG. 6; FIG. 12 is an explanatory diagram of the normal read/write operation in FIG. 6; The figure is a configuration diagram of the second embodiment of the present invention, the 14th [ff
1 is a configuration diagram of a conventional input/output system. In the figure, CT-human output control device, la, lb, IC% t
d, c, A-...Channel adapter (upper side transfer section)
, 2a, 2b, 2c, 2d, DA-device adapter (
lower side transfer section), 3.4.-ca.7 memory section, 5
-Table storage (selection exclusive control unit), 9-D
ASD (input/output device).

Claims (4)

[Claims] (1) An input/output control device that transfers data of the requested input/output device to the higher level side in response to an access request from the higher level side, the input/output device in response to an access request from the higher level side. an upper-side transfer unit connected to the upper-layer side that transfers the data of the input-output device to the upper-layer side; a cache memory unit connected to the plurality of input-output devices; A lower-side transfer unit that transfers data of the input/output device to the cache memory unit; and access requests from a plurality of the upper-side transfer units that are placed under the management of the upper-side transfer unit and share the plurality of input/output devices. a selection exclusive control unit that performs selection exclusive control of the input/output device, and the higher-level transfer unit refers to the cache memory unit in response to an access request from the higher-level side, and the requested data exists. The input/output control is characterized in that the data in the cache memory unit or the data obtained by selecting the input/output device via the lower transfer unit are transferred depending on whether or not the data exists. Device. (2) The upper transfer unit is composed of a plurality of upper transfer units, and the lower transfer unit is composed of a plurality of lower transfer units each connected to the plurality of input/output devices. An input/output control device according to claim (1). (3) The upper transfer unit, the lower transfer unit, the cache memory unit, and the selection exclusive control unit are connected by a common bus.
) Input/output control device described in section 2. (4) When the upper transfer unit selects the input/output device via the lower transfer unit as a result of referencing the cache memory unit, the data from the input/output device is transferred to the lower transfer unit. The input/output control device according to claim 1, wherein the input/output control device transfers and stores the data in the cache memory section.