JPS61184784A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve yield and to perform fast operation by providing a diode circuit which generates a voltage drop nearly equal to the voltage drop of a load circuit including the clamping diode of a memory cell and generating the voltage drop across a resistance with a low resistance value by an emitter follower circuit. CONSTITUTION:A diode DR 1 and a load resistance RR 1 have the same designed value so as to generate the same voltage drop with clamping diode DCs 1 and 2 and load resistance RCs 1 and 2 of the memory cell MC 1, a diode DR 2 for level shifting is connected in series, and a load resistance RB 1 for biasing is connected between the DR 2 and a power source VCC. Then, a voltage which is shifted in level by the diode DR 2 is supplied to an emitter follower type transistor QR 1 which is connected to a load resistance RRE at its emitter and to a load resistance RRC at its collector. Therefore, the voltage drop across the load resistance RRE is equalized to the voltage drop across the diode circuit DDC consisting of the diode DR 1 and load resistance RR 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory, and particularly to a high-speed semiconductor memory using a bipolar transistor having a read/write control circuit that controls reading and writing by switching the memory cell read current. Regarding memory.

[Conventional technology]

FIG. 3 is a circuit diagram showing the main parts of a first example of a conventional semiconductor memory. In the figure, MCI to MCn are memory cells formed by bipolar transistors, and a plurality of n cells are arranged to form a memory cell array. Each of the memory cells MCI to MCn is a two-emitter transistor QCI whose base and collector are cross-connected.
, QC2, one emitter is commonly connected and connected to a constant current source IHi (i=1.2+...n) for holding current, and the other emitters are transistors Ql, Q2 that constitute a detection circuit, respectively. The collector is connected to the word line WLi through a load circuit consisting of clamp diodes DCI, DC2 and resistors 1 (, CI, C2) connected in parallel thereto.

The word line WLi of each memory cell is connected to a transistor Q.
WTit- is connected to the power supply vCC via. SA is a sense amplifier and each input is a resistor) 1,81
, about 52t- are connected to the collectors of the transistors Ql and Q2, which are connected to the power supply vCC via 52t, and read out the memory cells.

RWC is a read/write control circuit, which includes the collector of a transistor QR whose one end is connected to the power supply vCC and the other end is connected to the comparison voltage terminal VRt-base, a resistor RWOO, and a resistor 1 (,
A resistor kLl (,
i have The other end of the resistor kLwooo is connected to the collector of the transistor QWOO whose base is connected to the O'' write input signal terminal WO, and the other end of the resistor RWIO is connected to the base of the ul'' write input signal terminal Wli to the collector of the transistor QWIO. and the three transistors QR, QW
In order to configure a current switch, OO and QWIO have their respective emitters connected in common and are connected to a constant current source IWR through which a constant current IWRt flows. Transistors QWOO and QWIO
The collectors of each of the transistors QWQ and QWI are connected to the bases of transistors QWQ and QWI forming an emitter follower configuration, and the emitters of the transistors QWQ and QWI are connected to the bases of transistors Q1 and Q2, which are the respective output terminals.

Next, the operation of this conventional example will be explained.

Table K1 shows the read/write circuit kLWC of this semiconductor memory.
The operation according to the input signal is shown as a truth table of positive logic. Here, the state in which the first signal inputs of terminals WO and Wl are '1' and 1# does not exist in terms of operation. When the input signals to terminals Wl and WO are both “O”, transistor QR is turned on, and transistors QWOO and QW
Both IO are turned off, and the base signals to the transistors QWO and QWI both have a high potential indicated by VCC-RRxIW. And its emitter signal level is
The first level is lowered by the base-emitter on voltage VBEON of the transistors QWO-QWI, and this is taken as the read output voltage VREAD.

Constant current source I for read current connected to memory cell array
SI and IS2 are memory cells selected by the read output voltage VREAD of the read/write control circuit KWC and the clock applied to the selection terminal WTi, for example, the memory cell MCI.
The holding current IHI and the read current ISI vary depending on the difference between the base potentials of the memory transistors QC1 and QC2.
Or perform current switching with IS2, thereby resistor R81
A difference is generated in the potential drop between R82 and R82, which is detected and amplified by the sense amplifier 8A, and the data of the memory cell is read out as an output.

At this time, in order to turn on and off the transistors QCx and QCzt, the read output voltage VRE is
AD needs to be located between the base potential of transistor QC1 and the base potential of transistor QC2, and as a potential drop of resistor 1(, I() due to constant current source IWf(+) in this potential 'fc read/write control circuit RWC, It has occurred.

For high-speed operation, the diodes L)C1 and DC2 are Schottky diodes whose on-voltage (approximately 0.5V) is lower than the base-emitter on-voltage (approximately 0.8V) of the transistors QCI and QC2, which is difficult to manufacture. Normally, the variation in the on-voltage is large, and in this conventional circuit, Ml(, EAD is always constant, so the on-voltage of the clamp diodes DCI, DC20 is It is necessary to narrow the tolerance range of gold, which has the disadvantage of causing a decrease in yield.

Next, when transistors QC1 and QC2 are on and off, and signals of "1" and °t's are applied to terminals W1 and WO, respectively, transistor QR turns from on to off, and transistor QWOO turns on. Mama, transistor QW
IO changes from off to on = This results in base signal level 1jVcc-IWRx to transistor QWI
The potential becomes j lower as shown by (RR+RW10), and the emitter signal level becomes a second level lowered by VBEON.

This second level is a potential lower by IWRxRWlo than the level VREAD at the time of optical reading, and the transistor QC2, which was currently in the off state and constitutes the memory cell,
is set to a potential υ lower than the base potential of , and as a result, transistor QC2 is turned on. Furthermore, at this time, the read current I
Since the transistor QC2 supplies Sz, its collector potential decreases, and the transistor QCI of the memory cell whose base is connected to the collector changes state t- from on to off, and the "1" write is executed. FIG. 4 is a circuit diagram showing a main part of a second example of a conventional semiconductor memory, which improves the drawbacks of the first example shown in FIG.

In the read state, the read/write control circuit RWC:
Diode D having the same on-voltage as memory cell MCI
WOt - resistor RWOI and 1 (, connected in parallel with the series connection of WO2, resistor 1 (, from the connection point of WOl and RWO2,
Similarly, a diode DWI (i) having the same on-voltage as the memory cell MCI is connected in parallel to the series connection of resistors RW1i and RW12, and the read output voltage VREAD is output from the connection point of the resistance ratios W11 and 1 (, R12). It has occurred.

[Problem that the invention seeks to solve]

In this case, clamp diode DC1 and diode DW
In order to make the potential drops of O and DWI the same voltage, the current values IWO and IW1 of the constant current sources IWO and IWI and the current value of the constant current source I81 are set to l5It-IWO=IW1=ISI, and the resistor RWOI, RWO2゜RWll, R
WI2. The resistance values of RCI are RWol and 几WO2, respectively.
, RWII, 几W12. When RC1, RWO1+
RW02 = RWI 1 + W12-R, C1 (It is necessary to set the memory cell load resistance a, and the normal resistance i
(For CI, the lower limit of its resistance value is determined from the original necessity of retaining memory contents, and the upper limit of its resistance value is determined from the maximum value of the overall power consumption.

Usually, for the purpose of high-speed operation, bipolar memory uses IC
With a capacity of 1024 bits per unit, kLCI is 10Ω, ■
With a capacity of C and 4096 bits, Ω is selected to be R and C1=20 to 30. In this conventional example, RWOI= )LWO
2. Even if W11=RW12, 5Ω and 10 respectively
~15 is Ω, which means that the input capacitance of transistors Q1 and Q2 and the wiring capacitance for signal connection are each 39F for on and off of the write changeover switch during the transition between read and write operations. Each time constant is 7.7ns
(=3pFX5 to Ω/2) and 15 to 22.5 ns
(= Ω/2 for 3pFX10-15), and high-speed operation is impossible.

In other words, in semiconductor memories with conventional read/write control circuits, in order to suppress variations in Schottky diodes used as clamp diodes used in memory cell load circuits, it is necessary to narrow the allowable on-voltage range. There is a drawback that the yield is completely reduced. Furthermore, conventional circuits that have improved this drawback have the drawback that they are essentially unable to operate at high speeds above a certain level.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, expand the tolerance range of the on-voltage of the clamp diode used in the load circuit of the memory cell, and improve the manufacturing yield. High,
Another object of the present invention is to provide a semiconductor memory having a read/write control circuit capable of high-speed operation.

[Means for solving problems]

The semiconductor memory of the present invention is a semiconductor memory having a memory cell array in which a plurality of memory cells are arranged, and a read/write control circuit that controls reading and writing by switching the read current of a selected memory cell in the memory cell array. , the read loading control circuit includes a first diode that causes a voltage drop substantially equal to that of a load circuit including a clamp diode of the selected memory cell by flowing the same current as the read current; a second diode having a cathode connected to the other end of the diode circuit and an anode connected to the first node; one end connected to the i-first node and the other end connected to the second node; a first resistor, each connected to a power source, and a first transistor, each having a base connected to the first node, an emitter connected to the first power source via a second resistor, and a collector connected to the second node, respectively. and a second transistor having a base connected to a comparison input terminal, an emitter connected to the second node, and a collector connected to the third node, and one end connected to the first power supply and the other end connected to the second node. A first constant current source connected, a third resistor whose one end is connected to the third node and the other end to the second power supply, and a base thereof are respectively a signal input terminal when writing "1" and a signal input terminal when writing "0". When writing, the emitter is common to the signal input terminal, and the collectors are the fourth and fifth nodes, respectively, to the second node.
third and fourth transistors connected to the node, and fourth and fifth resistors having one end commonly connected to the third node and the other end connected to the fourth and fifth nodes, respectively. and a fifth whose base is connected to the node w, whose emitter is connected to the first power supply via a second constant current source, and whose collector is connected to the second power supply at the first output terminal, respectively. a sixth transistor having a base connected to the fifth node, an emitter connected to the first power source via a third constant current source, and a second output terminal and a collector connected to the second power source. It is composed of transistors.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing essential parts of a first embodiment of the present invention.

This embodiment is a semiconductor memory having a memory cell array in which a plurality of memory cells are arranged, and a continuous write control circuit RWC@ that controls reading and writing by switching the read current of a selected memory cell MCI in this memory cell array. In the read/write control circuit RWC, the same current as the read currents ISI and IS2 is passed through the clamp diode DCI of the selected memory cell.
DC2, resistance RCI.

) A diode circuit DDC which produces the same voltage drop as a load circuit consisting of parallel connections of LC2 and a diode circuit DDC whose one end is connected to the ground potential, whose cathode is connected to the other end of the diode circuit DDC and whose anode is connected to the node N1. a resistor RBI whose one end is connected to the node N1 and the other end to the power supply vCC, and whose base is connected to the node N1 and whose emitter is connected to the ground potential through the resistor 1 (,kLE 'i) and whose collector is connected to the node N2, respectively. A transistor QRI whose base is connected to the comparison input terminal Vi (and a transistor Ql whose emitter is connected to the node N2 and whose collector is connected to the node N3) and a constant current source whose one end is connected to the ground potential and the other end is connected to the node N2. IW 几 and one end is node N
3, a resistor R)t whose other end is connected to the power supply vCC, and a signal input terminal W1 and at O when the base is written to "1" respectively.
Transistors QWIO and QWOO whose emitters are commonly connected to a node N2 and collectors are connected to nodes N4 and N5, respectively, are connected to a signal input terminal WO during writing, and transistors QWIO and QWOO are connected to a node N4 and N5, respectively, with one end commonly connected to a node N3 and the other end connected to a node N4 and N5, respectively. A transistor QWI whose base is connected to the node AN4, whose emitter is connected to the ground potential via the constant current source IW1t-, and whose collector is connected to the power supply vCC at the output terminal 0ut2, whose base is connected to the node N5 The transistor QWO has an emitter connected to the ground potential via a constant current source IWO=i, and a transistor QWO whose output terminal 0utl and collector are connected to the power supply vCC.

The diode circuit DDC includes a diode DR1 and a resistor RRI connected in parallel with the diode DR1.

That is, the read/write control circuit WC of this embodiment is as follows:
In contrast to the conventional example shown in FIG. 3, the diode circuit DDC generates the same voltage drop as the voltage drop caused by the load circuit including the clamp diode of the memory cell, and the voltage drop is applied to the transistor Q) Ll and the resistor RRE. The emitter follower circuit converts impedance to obtain a large current constant current source.

Next, the operation of this embodiment will be explained.

The diode DRI and its load resistance RRI are arranged in the same manner so as to produce the same voltage drop as the clamp diodes DCI, DC2 and the load resistances RCt and Cz of the memory cell MC1.
This is a design value, and the level shift diode D2 is connected in series, and the bias load resistor RB1 is connected to the power supply vC.
It is connected between C and C. The voltage level-shifted by the diode DR2 is then applied to the load resistance RRE t
- connected to its emitter, load resistance R) (Ct - emitter follower transistor QR connected to its collector)
By setting the on-voltage of the level shift diode DR2 equal to the on-voltage between the base and emitter of the transistor Q), the voltage drop across the load resistor WE is diode DR
1 and the voltage drop of the diode circuit DDC consisting of the load resistance ktR1.

Therefore, in order to make the read output voltage VREADt- of the read/write control circuit RWC intermediate between the base potentials of the transistors QCI and QC2 of the memory cell MCI, the resistance values of the resistors RR and RRE are set as RR, , RBE. It is sufficient to set it as HJ47BE-0,5.

In this case, for example, resistance RC1 = 几C2 = Ω - 10
Even so, it is possible to select the load resistance RR in the range of about 2000, and the time constant of each emitter terminal of the output transistors QWO and QWI of the read/write control circuit WRC is 0.
．． 6ns (=200Ω×3pF), which can be sufficiently faster than the conventional example shown in FIG. Historically, the allowable range of the on-voltage of the clamp diode Di(,1,1)El,2 is also
Since the output voltage VREAD of the read/write control circuit WC is regulated by the resistance ratio R)L/R)LE, there is no need to limit it particularly narrowly.

@2 Figure is a circuit diagram showing the main part of the second embodiment of the present invention. This embodiment has the following points compared to the first embodiment shown in FIG.
Load resistance RR in diode circuit DDC, l t-
The current flowing through the diode DRIK is 0.5 V710K due to the removal of the resistive load resistance 8 and 1.
(If the on-state current of the diode D is about 500 microns, the on-state voltage will only decrease by about 3 mV in the case of an ideal diode), which can be ignored in practical terms. Therefore, according to this embodiment, the effect that the circuit becomes simpler can be obtained.

In the above explanation, for convenience of explanation, the first power supply is set to ground potential, and the second power supply is set to gold collector power supply ■CC, but in actual use, the first power supply is set to 1-VER, and the second power supply is set to ground potential. Although the potential is often used, it goes without saying that the present invention is similarly applicable.

〔Effect of the invention〕

As described above in detail, the semiconductor memory of the present invention is provided with a diode circuit that generates a voltage drop approximately equal to the voltage drop of a load circuit including a clamp diode of a memory cell as a read/write control circuit, and transfers the voltage drop to an emitter follower. Since the circuit is configured to generate a resistance across a resistance having a low resistance value, it has the effect of widening the tolerance range of the on-voltage of the clamp diode and shortening the transition time between reading and writing. There is. Therefore, according to the present invention, a semiconductor memory having a read/write control circuit capable of high-speed operation with high yield can be obtained.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 respectively show the first embodiment of the present invention. A circuit diagram showing the main parts of the second embodiment, and FIGS. 3 and 4 are circuit diagrams showing the main parts of the conventional example. 1) C1, DC2, D) Ll... Schottky diode, Di-42... Diode, 1)
i) C...Diode circuit, IHI, IH2,
IHn, ISI, IS2. IWR, IWO. IWI... Constant current source, MCI, MC2, MC
n...Memory cell, Ql, Q2. QCl, QC
2,QI(,0,Ql(,1,QWO,QWI,QW
OO, QWIO, QWTI. QWT2. QWTn-...NPN type transistor,
RBl, RCI, RC2,f(, Jl(, WOo
, 1-LWIO, R-E...Resistance, RWC...
...Read/write control circuit, 8A...Sense amplifier, vCC...[Source, WTI, WT2
゜WTn...Selection terminal. Agent: Susumu Uchihara, Patent Attorney, Pa.)゛. -1)

Claims (3)

[Claims] (1) In a semiconductor memory having a memory cell array in which a plurality of memory cells are arranged, and a read/write control circuit that controls reading and writing by switching the read current of a selected memory cell in the memory cell array, The control circuit includes a first diode that causes substantially the same voltage drop as a load circuit including a clamp diode of the selected memory cell by flowing the same current as the read current, and one end of the control circuit is connected to a first power source. a second diode having a cathode connected to the other end of the diode circuit and an anode connected to the first node; one end connected to the first node and the other end connected to a second power source; a first resistor whose base is connected to the first resistor;
a first transistor whose emitter is connected to the first power supply via a second resistor and whose collector is connected to the second node; the base is connected to the comparison input terminal and the emitter is connected to the second node; are connected to the third node, a first constant current source whose one end is connected to the first power supply and the other end is connected to the second node, and one end of which is connected to the third node. a third resistor whose other end is connected to the second power supply at the node, and whose base is a signal input terminal when writing "1" and whose emitter is commonly connected to the signal input terminal when writing "0", and which is connected to the second node. third and fourth transistors whose collectors are connected to the fourth and fifth nodes, respectively, one ends of which are commonly connected to the third node, and the other ends of which are connected to the fourth and fifth nodes, respectively; fourth and fifth resistors, the base of which is connected to the fourth node, the emitter of which is connected to the first power source via a second constant current source, and the collector of which is connected to the first output terminal of the fourth node; fifth transistors each connected to a power supply; a base connected to the fifth node; an emitter connected to the first power supply via a third constant current source; and a collector connected to the second output terminal. A semiconductor memory comprising: sixth transistors each connected to a power source. (2) The semiconductor memory according to claim (1), wherein the diode circuit comprises the first diode alone or a sixth resistor connected in parallel with the first diode. (3) The semiconductor memory according to claim (1), wherein the ratio of the resistance values of the third resistor and the second resistor is 0.5.