JPS6118368B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for modulating a signal by multiplying a signal in one frequency band with a substantially sinusoidal or square wave signal in a second frequency band. In the past, modulators were constructed by combining various nonlinear devices, such as vacuum tubes, diodes, transistors, and switches, with transformers or amplifiers. For example, U.S. Patent No. 3,937,882
The modulator shown in (Bingham, February 10, 1976) is a typical example. Individual adjustment of circuit parameters has generally been required when design requirements require that these values be kept very low for all spurious outputs of the modulator. It is often desired to realize the transfer function of an electronic circuit using only components that can be implemented in an LSI circuit. An example of a configuration using such parts is a switch,
It consists of a capacitor and an operational amplifier. The technology for using these parts is
It is called a capacitor, and the IEEE of Hostcka et al.
It is described in the Journal of Solid State Circuits (December 1977, p. 600). The transfer function of a switched capacitor circuit is shown to be sensitive to the parasitic capacitance between each electrode of the capacitor and a common ground (usually the substrate). The parasitic capacitance between the electrode on the substrate side and the substrate (ground) is larger. However, the influence of this larger parasitic capacitance can usually be eliminated by grounding the substrate-side electrode of the capacitor to the substrate. However, even in this case, the sensitivity to the smaller parasitic capacitance between the upper electrode of the capacitor and the substrate remains dependent. Two examples of switch capacitor configurations that are completely insensitive to either of the above parasitic capacitances are given by Martin and Sedra in Electronics Letters.
(June 21, 1979, P365). It carries a pair of inverting and non-inverting integrators as well as circuitry for the various filter sections. Therefore, the main objective of the present invention is to provide a fully integrated modulation device that does not require separate components. Another object is to implement such a modulation device using switches, capacitors and operational amplifiers. Yet another object is to provide a modulation device that provides a modulation signal to an integrator to operate in an inverting mode and a non-inverting mode alternately under control of a carrier signal. Yet another object is to provide a modulator that is insensitive to capacitor parasitic capacitance. According to the invention, an integrator is used which switches between an inverting mode and a non-inverting mode under the control of a carrier signal. The incoming signal, i.e. the modulating signal, is switched
It is input to this integrator through a capacitor circuit. All the circuit components used in the integrator and switched capacitor circuits can be implemented on LSI. The present invention features an operational amplifier (integrator) with a feedback capacitor and one or more input capacitors that act as a switch between the incoming signal and the integrator, introducing the input signal to the integrator either unchanged or out of phase. The modulation device consists of a capacitor and a capacitor. The output signal of the integrator is equivalent to a carrier signal modulated with the incoming signal. Hereinafter, several embodiments of the present invention will be shown, and the above-mentioned objects and other objects, features, advantages, etc. will be made clear through the following detailed description with reference to the drawings. FIG. 1 shows a block diagram of a modulation device comprising a logic circuit 8, a switched capacitor circuit 10 and an integrator 12. Input 14 of logic circuit 8
is given a clock signal which is the basis for sampling the modulated signal. The modulated signal is applied to input 16 of switched capacitor circuit 10. A carrier signal is applied to the input 18 of the logic circuit 8, and the state of this signal determines whether the sampled modulated signal is applied to the integrator 12 in its unchanged form or in its inverted form. Integrator 1
2 generates an output signal equivalent to the carrier signal modulated by the modulating signal. Logic circuit 8 provides the cut signal to switched capacitor circuit 10 so that the modulated signal is applied to integrator 12 in the manner described above. According to an embodiment of the present invention, the modulation device shown in FIG. 1 is composed only of circuit elements that can be easily mounted on an LSI. The switch is usually a MOSFET IC, and the integrator is an ordinary operational amplifier with a feedback capacitor, and all of these components (elements) can be integrated on a single board. Advantageously, the invention can be implemented without using any separate parts. FIG. 2a shows an example of the basic configuration of the switched capacitor circuit shown in FIG. During one half-wave period (half cycle) of the carrier signal, switches 20 and 22 close in phase to charge capacitor 24. Switches 20 and 22 are then opened and switches 26 and 28 are closed to discharge capacitor 24 to integrator 12. In this mode of operation, the sampled modulation signal is sent to the integrator in inverted form. Therefore, when the integrator 12 is constructed from an inverting amplifier with a feedback capacitor, the entire modulation device operates in a non-inverting mode. During the other half-wave period of the carrier signal, switches 20 and 28 close in phase to charge capacitor 24 and apply the sampled modulated signal to integrator 12 as is. After that, switch 2
0 and 28 are open, and switch 22 is opened instead.
and 26 close, discharging capacitor 24 to ground. Therefore, if the integrator has the above configuration,
The operation of the modulator as a whole is in the inversion mode.
Modulation is performed by mode switching under the control of the carrier signal. Logic circuit 8 is switch capacitor circuit 10
Generates a switching signal to switch the switch. A preferred logical representation of the switching signal Sn (where n represents the number of each switch in FIG. 2a) is as follows. S ₂₀ = S ₂₂ = S ₂₆ = CLOCK CXR S ₂₈ = CLOCK where CLOCK and CXR indicate the logic levels of the clock signal and carrier signal, respectively. There are no restrictions on the phase relationship between the clock signal and the carrier signal. However, if the frequency of the clock signal is less than eight times the frequency of the carrier signal, significant distortion occurs that results in this behavior. In a preferred embodiment of the invention, the frequency of the block signal is 2 to the power of x, and the value of x is at least 4. FIG. 2b shows an example of a preferred relationship between the carrier signal, the clock signal, and the switching signals described above. When the modulator is operating in a non-inverting mode, capacitor 24 is charged during the first half cycle of the clock signal and discharged into integrator 12 during the next half cycle. Therefore, the modulation signal applied to integrator 12 is delayed by one-half period of the clock signal. In contrast, in the inversion mode, the modulated signal is applied to the integrator without time delay. This imbalance generates spurious components in the output signal. This imbalance is eliminated by adding another switch to the basic switched capacitor circuit, as shown in Figure 3a. During the first half period of the carrier signal, switch 30
is left open and the remainder of the switched capacitor circuit is operated similar to the non-inverting operation of the circuit of FIG. 2a. However, during the second half-period of the carrier signal, switches 20 and 22 remain open and switch 26 remains open.
remains closed. Switch 30 is then closed during the first half cycle of the clock signal, charging capacitor 24 through switch 20. During the second half period of the clock signal, switch 30 is opened;
Switch 28 is closed to discharge capacitor 24 toward integrator 14. Thus, even in inversion mode (operating mode in the second half period of the carrier signal),
The above-mentioned time delay will occur, and the above-mentioned imbalance will disappear. The relationship between the clock signal and the carrier signal described in FIG. 2a also applies in this case, but the individual switching signals vary. Logic circuit 83 is switch capacitor circuit 1
Generates a switching signal that controls the operation of the ⁰³ switch. The preferred switching formula for the switching signal Sn (where n indicates the respective switch number in FIG. 3a) is as follows. _S20 = _S22・_S26 =CLOCKCXR _S28 =CLOCK _S30 =・Here, CLOCK and CXR are as described above. FIG. 3b shows an example of the preferred relationship between the carrier signal, clock signal and switching signal in FIG. 3a. FIG. 4a is a complementary version of the modulator of FIG. 3, so a detailed description of the mode of operation will be omitted. Switch 32 is a complementary switch to switch 30 of FIG. 3a. In order to fully understand the operation of the device shown in Fig. 4a, the carrier signal is shown in Fig. 4b.
4 shows an example of a desired relationship between clock signals and switching signals. When the circuit of FIG. 3a (or FIG. 4a) is integrated, the electrodes of the capacitor 24 (switches 22, 28, 30 in FIG. 3a, 2 in FIG. 4a)
0, 26, 32) and the substrate, the integrator 12
, but the parasitic capacitance does not affect the gain of integrator 12 in non-inverting mode. This imbalance produces a small spurious component in the output of the integrator 12. To deal with the effects of parasitic capacitance, use the circuit shown in Figure 2a, which has no sensitivity to parasitic capacitance, and adopt a delay method in which the modulation signal is delayed by a half period of the clock signal or switching signal in the inversion mode before being introduced into the integrator. It can be removed by FIG. 5a shows the switched capacitor circuit ¹⁰² of FIG. 2a in which a delay circuit 38 for providing the above-mentioned delay is added. In this example, the modulation signal is input 40
given to. Switch 42 operates in phase with switch 22. During the first half period of the carrier signal, switch 42 is also in phase with switch 20, so no delay is imparted to the modulated signal.
However, during the second half period of the carrier signal, switch 42 operates out of phase with switch 20, and switch 42, capacitor 46, and unity gain amplifier 44
The modulated signal is delayed by a half period of the clock signal by the sample-and-hold circuit created by the above. This eliminates the imbalance described with respect to FIG. 2a. The integrator shown in FIG. 5a consists of an amplifier 48 and an integrating capacitor 50. A circuit 51 consisting of a switch 52, a switch 54 and a capacitor 56 is connected in parallel with the integrator 12. This switch-capacitor switch combination circuit 51 has the function of preventing DC saturation of the amplifier by dissipating a portion of the charge in the capacitor 50 during each cycle of the clock signal. The frequency relationship between the switching signal and the carrier signal explained in FIG. 2a also applies to FIG. 5a.
However, logic circuit 85 generates a switching signal with appropriate modifications. Switching signal Sn (here n is 5th a)
The preferred logical formula for (indicates the number of each switch in the figure) is as follows. S ₂₀ = S ₂₂ = S ₄₂ = S ₅₄ = S ₂₆ = CLOCKCXR S ₂₈ = S ₅₂ = CLOCK Here, CLOCK and CXR are as defined above. FIG. 5b shows an example of a preferred relationship between the carrier signal, clock signal and switching signal of FIG. 5a. It is desirable to implement the switching functions described above so that they do not overlap with each other. The operation of the switch that should be closed is repeated until the switch that is already closed is opened. A suitable method for obtaining a non-overlapping relationship is to generate the switching signals described above and to send each switching signal to a corresponding AND gate.
Then, a clock pulse having twice the frequency of the aforementioned clock signal is applied to the second input of each AND gate. Then, the output signal of the AND gate is given to the corresponding switch as a switching signal. In this way, each switch is not closed for 1/4 period of the clock signal, so a switching relationship that does not overlap can be obtained. In the above-described embodiment, a square wave was used as the carrier signal, but if approximation to a sine wave carrier is required, the gain of the integrator 12 is increased or decreased in steps by the shaping means so that the modulation is a step-by-step of the sine wave. Let it be done by approximation. That is, since the gain of the integrator 12 is directly proportional to the capacitance of the capacitor 24, the gain is controlled by sequentially switching and introducing several capacitors in parallel with this capacitor. The number of capacitors used in the shaping means determines the degree of approximation to a sine wave. FIG. 6a shows an example of connecting a capacitor and a switch in parallel with the capacitor 24. This parallel circuit can be added to any of the switched capacitor circuits described above. switch 5
When 6, 58, and 60 are open, the gain of integrator 12 is determined solely by capacitor 24 of switched capacitor circuit ¹⁰⁶ . First, turn on the switch 56 and introduce the capacitor 62, and then turn on the switch 5.
Capacitors 64 and 66 are added to the circuit by sequentially closing capacitors 8 and 60. Next, open the switches in reverse order to disconnect the capacitors from the circuit one after the other. The capacity ratio of capacitors 24, 62, 64, and 66 is 1.000:
By setting it to 1.848:1.414:0.765, the 3rd, 5th, 7th, 9th, 11th, and 13th harmonic components of the carrier signal and their sidebands can be lowered. Switches 56, 58, 6 of FIG. 6a are shown in FIG. 6b.
A timing chart of switching signals S ₅₆ , S ₅₈ , and S ₆₀ for 0 is shown. A truth table showing the preferred logical relationship between these switching signals generated by the logic circuit ⁸⁶ is shown. In this table, F ₁ indicates the logic level of the carrier signal, and F ₂ , F ₄ , and F ₈ indicate the logic levels of signals having twice, four times, and eight times the frequency of the carrier signal, respectively. 【table】

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the modulator, Fig. 2a is a circuit diagram showing an example of the basic configuration of the switched capacitor circuit shown in Fig. 1, Fig. 2b is a timing chart of the control logic of the switch shown in Fig. 2a, and Fig. 3a is is the second
Figure 3a is a circuit diagram showing another configuration example of the switch capacitor circuit in Figure 3a, Figure 3b is a timing chart of the control logic of the switch in Figure 3a, Figure 4a is
The figure is a circuit diagram showing another configuration example of the switch capacitor circuit in Figure 1, and Figure 4b is a circuit diagram showing another configuration example of the switch capacitor circuit in Figure 1.
Timing chart of switch control logic in figure.
5a is a circuit diagram showing still another configuration example of the switched capacitor circuit in FIG. 1, FIG. 5b is a timing chart of the control logic of the switch in FIG. 5a, and FIG. 6a is a circuit diagram of the switched capacitor circuit in FIG. 1. A circuit diagram showing yet another example of the circuit configuration, FIG. 6b shows the timing and timing of the control logic of the switch in FIG. 6a.
It's a chat. 8, 8 ² , 8 ³ , 8 ⁴ , 8 ⁵ , 8 ⁶ : logic circuit, 12 : integrator, 10, 10 ² , 10 ³ , 10
⁴ , 10 ⁵ , 10 ⁶ : Switch capacitor circuit, 24: Main capacitor, 20, 22, 26, 2
8, 30, 32: Switch, 62, 64, 66:
Auxiliary capacitors, 56, 58, 60: Auxiliary switches.

Claims (1)

[Claims] 1. A switched capacitor modulation device that modulates a carrier signal with a modulation signal to form a modulated signal, comprising a first input to which a modulation signal is applied, and a first input to which a plurality of switching signals are applied. main capacitive means having two inputs, an output for providing a sampled modulated signal, first and second electrodes, and a plurality of main capacitive means for connecting said first and second electrodes to said input and output in response to a switching signal. switching means comprising a binary switch; logic means for generating said switching signal in response to a carrier signal and a clock signal having a frequency at least four times that of said carrier signal; and said switching signal being modulated in response to said sampled modulation signal. A switch capacitor modulation device comprising: integrating means for providing a signal; 2. In the modulation device according to claim 1,
The plurality of binary switches include at least first, second, third and fourth switches, and the first
An electrode is connected to the first input via a first switch and to a common ground via a second switch, the second electrode is connected to the output via a third switch, and the second electrode is connected to the output via a fourth switch. connected to a common ground. 3. In the modulation device according to claim 2,
The logic means is configured to generate, during a first half cycle of the carrier signal, a switching signal which closes the first and fourth switches and opens the second and third switches during one half cycle of the clock signal. The main capacitive means is charged with the modulation signal, and the first and fourth switches are opened during the remaining half cycle of the clock signal, and the second and third switches are opened.
The main capacitive means is discharged by generating a switching signal that closes the switch. 4 In the modulation device according to claim 3,
Said logic means controls said switching signal by generating, during a second half-cycle of the carrier signal, a switching signal which closes said first and third switches and opens said second and fourth switches during one half-cycle of the clock signal. generating a switching signal which causes the main capacitive means to be charged with the modulation signal and which opens the first and third switches and closes the second and fourth switches during the remaining half cycle of the clock signal; The main capacitive means is discharged. 5. In the modulation device according to claim 4,
Delay means consisting of an operational amplifier 5 switch having an input and an output, and storage capacitive means are provided, the input of the operational amplifier being connected to said first input via a fifth switch, and the output of the operational amplifier being connected to said first switch. The storage capacitive means is connected between the input of the operational amplifier and the common ground, and the fifth switch is controlled by the same switching signal as the fourth switch. 6 In the modulation device according to claim 3,
Said switching means include a fifth switch for connecting said first input to said second electrode in response to a switching signal S other than those mentioned above, and said logic means connect said fifth switch in said first half-cycle of the carrier signal.
generating said switching signal S which opens said switch; further said logic means generates said switching signal S which causes said second switch to close and said first and fourth switches to open during said second half-cycle of the carrier signal; During the first half period of the clock signal, the fifth switch is closed and the third switch is opened to charge the capacitive means with the modulating signal, but during the second half period of the clock signal, the fifth switch is opened and the third switch is closed. and generating a switching signal for discharging the capacitive means. 7 In the modulation device according to claim 3,
The switching means may be configured to receive switching signals other than those mentioned above.
S' includes a fifth switch connecting said output to said first electrode in response to said switching signal S', said logic means opening said fifth switch during said first half-cycle of a carrier signal. to occur,
Further, the logic means closes the fourth switch and opens the second and third switches during a second half cycle of the carrier signal, closes the first switch and opens the second switch during the first half cycle of the clock signal. generating a switching signal that opens a fifth switch to charge the capacitive means with the modulating signal, but opens a first switch and closes a fifth switch to discharge the capacitive means during a second half cycle of the clock signal; . 8. The modulation device according to claim 5, 6 or 7, wherein the switching means further includes shaping means consisting of a plurality of auxiliary capacitive means and a plurality of auxiliary switches responsive to the auxiliary switching signal, each of which The auxiliary capacitive means is connected to both ends of the main capacitive means via corresponding auxiliary switches, and the logic means generates the auxiliary switching signal for operating the auxiliary switch at a frequency that is an integral multiple of the carrier signal.