JPS587903A - Switched capacitor modulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for modulating a signal by multiplying a signal in one frequency band by a substantially sinusoidal or square wave signal in a second frequency band.

In the past, modulators were composed of various nonlinear devices, such as vacuum tubes,
It was constructed by combining diodes, transistors, switches, etc. with transformers or amplifiers. For example, U.S. Patent No. 3,937,882 (Binglam
The modulator shown in 1976/month/0 days given) can be said to be a typical example. Due to design requirements and all spurious outputs of the modulator, it has generally been necessary to keep these values very low and to individually adjust circuit parameters if necessary.

It is often desired to realize the transfer function of an electronic circuit using only components that can be mounted on an LSI circuit.

One example configuration of such components is a switch, a capacitor, and an operational amplifier.

The technology using these components is called switched capacitor technology, and is based on the IEEE standard of Ho5ticl et al.
Journal of 5solid 5tate
C1rcits (December 1977 P, 600
) etc.

The transfer function of a switched capacitor circuit is shown to be sensitive to parasitic capacitance between each electrode of the capacitor and a common ground (usually the substrate). The parasitic capacitance between the electrode on the substrate side and the substrate (ground) is larger. However, the influence of this larger parasitic capacitance can usually be eliminated by grounding the substrate side electrode of the capacitor to the substrate.

However, even in this case, the sensitivity to the smaller parasitic capacitance between the upper electrode of the capacitor and the substrate remains dependent.

Two examples of switched capacitor configurations that are completely insensitive to either of the above parasitic capacitances are given by Martin.
and 5edra, Electronics Let
ters (June 21, 1979, P365). It carries a pair of inverting and non-inverting integrators as well as circuitry for the various filter sections.

Therefore, the main objective of the present invention is to provide a fully integrated modulation device that does not require separate components.

Another object is to implement such a modulation device using switches, capacitors and operational amplifiers.

Yet another object is to provide a modulation device for providing a modulation signal to an integrator so as to alternately rainbow in inverting and non-inverting modes under the control of a carrier signal.

Yet another object is to provide a modulation device that is insensitive to the parasitic capacitance of capacitors.

According to the invention, an integrator is used which switches between an inverting mode and a non-inverting mode under the control of a gear signal. The incoming signal, ie the modulation signal, is input to this integrator through a Suinocito capacitor circuit. All of the circuit components used in the integrator and switched capacitor circuits can be mounted on an LSI.

The invention features an operational amplifier (integrator) with a feedback capacitor and one or more input capacitors that switch between the incoming signal and the integrator, introducing the input signal as it is or out of phase into the integrator. The modulation device consists of a capacitor and a capacitor. The output signal of the integrator is equivalent to a carrier signal modulated with the incoming signal.

Hereinafter, several embodiments of the present invention will be shown, and the above-mentioned objects and other objects, features, advantages, etc. will be made clear through the following detailed description with reference to the drawings.

Figure 1 shows a logic circuit 8 and a Swisso-chito capacitor circuit 1.
1 is a block diagram of a modulation device consisting of an integrator 12 and an integrator 12; An input 14 of the logic circuit 8 is supplied with a clock signal which is the basis for sampling the modulation signal. The modulation signal is applied to input 16 of switched capacitor circuit 10. A carrier signal is applied to the input 18 of the logic circuit 80, and the state of this signal determines whether the sampled modulation signal is applied to the integrator 12 in its unchanged form or in its inverted form. 12 generates an output signal equivalent to the carrier signal modulated by the modulating signal. Logic circuit 8 applies the cut signal to Suinocito capacitor circuit 10 so that the modulating signal is applied to integrator 12 in the manner described above. According to an embodiment of the present invention, the first
The modulation device shown in the figure is composed only of circuit elements that can be easily mounted on an LSI. The switch is usually an MO8FET IC, and the integrator is an ordinary operational amplifier equipped with a feedback capacitor, and all of these components (elements) can be integrated on one substrate. Advantageously, the invention can be implemented without using any separate parts.

FIG. 2a shows an example of the basic configuration of the Suinotito capacitor circuit of FIG. 1. During one half-wave period (half cycle) of the carrier signal, switches 20 and 22 close in phase to charge capacitor 24. Switches 20 and 22 are then opened and switches 26 and 28 are closed to discharge capacitor 24 to integrator 12. In this mode of operation, the sampled modulated signal is sent to the integrator in inverted form. Therefore, if the integrator 12 is configured with an inverting stepper having a feedback capacitor H, the entire modulation device will operate in a non-inverting mode.

During the other half-wave period of the carrier signal, switch 2
0 and 28 are closed in phase, charging the capacitor 24, and applying the sampled modulation signal to the integrator 12 as it is. Switches 20 and 28 are then opened, and switches 22 and 26 are then closed, discharging capacitor 24 to ground. Therefore, when the integrator has the above-described configuration, the operation of the modulation device as a whole is in the inversion mode.

Modulation is performed by mode switching based on ηi control of the carrier signal.

The logic circuit 8 is a switch of the Suinocito capacitor circuit 10,
Generates a switching signal to switch the notch. A preferred logical representation of the switching signal Sn (where n does not represent the number of each switch in FIG. 2a) is as follows.

S. 2 CL, OCK ■ C' There are no restrictions on the phase relationship between them. However, if the frequency of the clock signal is 8 times higher than the frequency of the carrier signal,
If it is less than 2 times, there will be significant distortions that will cause this behavior.

In the preferred embodiment of the invention, the frequency of the block signal is 2
and the value of X is at least 4.

FIG. 2b shows an example of a preferred relationship between the carrier signal, the clock signal and the switching signal mentioned above.

When the above modulator is operating in non-inverting mode,
Capacitor 24 is charged during the first half cycle of the clock signal and discharged into integrator 12 during the next half cycle. Therefore, the modulation signal applied to integrator 12 is delayed by half a period of the clock signal. In contrast, in the inversion mode, the modulated signal is applied to the integrator without time delay. This imbalance generates spurious components in the output signal.

This imbalance can be eliminated by adding another switch to the basic example switched gear puncture circuit, as shown in Figure 8.

Key 1. During the first half-cycle of the IJ gear, switch 3° remains open and the remainder of the Suinotito capacitor circuit operates in a manner similar to the non-inverting operation of the circuit of FIG. 2a.

However, during the second half period of the carrier signal, switch 20
and 22 remain open, and switch 26 remains closed. Then, during the first half cycle of the clock signal, switch 30 is closed and capacitor 2 is connected through switch 20.
Charge 4. The second half period of the clock signal opens switch 30 and closes switch 28 to discharge capacitor 24 to integrator 14. In this way, even in the inversion mode (operation mode in the second half period of the carrier signal), the above-mentioned time delay occurs, and the above-mentioned imbalance is eliminated.

The relationship between the clock signal and the carrier signal described in FIG. 2a also applies in this case, but the individual switching signals vary.

Logic circuit 83 generates switching signals that control the operation of the switches in switched capacitor circuit 103. A preferred switching logic equation for the switching signal Sn (where n indicates the respective switch number in FIG. 3a) is as follows.

52o=S2. =CLOCK-CXR8,6-CLO
CK■CXR 828-CLOCK S3o-CLOCK-CXR Here, CLOCK and CXR are as described above.

FIG. 3b shows an example of a preferred relationship between the carrier signal, clock signal and switching signal in FIG. 3a.

FIG. 4A is a complementary version of the modulator shown in FIG.

The switch 32 is in the complementary opening state with the switch 30 in FIG. 3a. ! An example of the desired relationship between the carrier signal, the clock signal and the switching signal is shown in FIGS. , When the circuit shown in Fig. 3a (or Fig. 4a) is integrated, the electrode of the capacitor 24 (in Fig. 3a, the switch 2
2.28.30, in Figure 4a, the gain of the integrator 12 increases in the inversion mode due to the parasitic capacitance between the electrode connected to 20.26.32 and the substrate. does not affect the gain of integrator 12 in non-inverting mode.

Due to this imbalance, a small spurious component is generated in the output of the +N divider 12.

The influence of parasitic capacitance is sensitive to parasitic capacitance, so the circuit of Figure 2a is used, and in the inversion mode the modulation signal is delayed by a half cycle M of the clock signal and the switching signal before being introduced into the integrator. This can be eliminated by adopting a delay method.

Fig. 5a shows the Suinochito Gapanta circuit 10 of Fig. 2a.
A delay circuit 38 for providing the above-mentioned delay is added to 2. In this example, the modulated signal is applied to human power 40. The switch 42 operates in the same phase as the switch 22. During the first half cycle of the key IJ gear, switch 42 is also in phase with switch 20, so no delay is imparted to the modulated signal.

However, during the second half period of the carrier signal, switch 42
operates in opposite phase to switch 20, and a sample hold circuit formed by switch 42, capacitor 46, and unity gain amplifier 44 delays the modulated signal by a half period of the clock signal. This eliminates the imbalance described with respect to FIG. 2a.

The integrator shown in FIG. 5a consists of an amplifier 48 and an integrating key pacitor 50. A circuit 51 consisting of a switch 52, a switch 54, and a capacitor 56 is connected in parallel with the integrator 12. This switch-container switch combination circuit 51 connects the capacitor 5 at each period of the clock signal.
It has the function of preventing DC saturation of the amplifier by dissipating a part of the zero charge.Explained in Figure 2a 1~ The frequency relationship between the switching signal and the carrier signal is the same as in Figure 5a. Applies to.

However, logic circuit 85 generates a switching signal with appropriate modifications.3 The preferred logic equation for switching signal Sn (where 11 indicates the number of the valley switch in FIG. 5a) is as follows.

S2o" CI, 0CK (θCXR 822""'42 = 854 2 CLOCKS26 =
CLOCK (1) CXR828= 852=CLOC
K Here CLOCK and CXR are as defined above.

FIG. 5b shows an example of a preferred relationship between the carrier signal, clock signal and switching signal of FIG. 5a.

It is desirable that the switching functions described above do not overlap with each other. A switch that should be closed is made to operate again until a switch that is already closed opens. A suitable method for obtaining a non-overlapping relationship is to generate two consecutive switching signals and send each switching signal to a corresponding AND gate.

Then, a clock pulse having twice the frequency of the aforementioned clock signal is applied to the second input of each AND gate. Then A
The output signal of the ND gate is applied to the corresponding switch as a switching signal. In this way, each switch is closed only for % period of the clock signal, so that a switching relationship that does not overlap can be obtained.

In the above-described embodiment, a square wave was used as the carrier signal, but if approximation to a sine wave carrier is required, the gain of the integrator 12 is increased or decreased in steps by the shaping means so that the modulation is in the order of the sine wave. I hope it will be done soon. That is, since the gain of the integrator 12 is directly proportional to the capacitance of the integrator 24, the gain is controlled by sequentially switching and introducing several capacitors in parallel with this capacitor. The number of capacitors used in the shaping means determines the degree of approximation to a sine wave.

FIG. 6a shows an example in which a capacitor and a switch are connected in parallel with the capacitor 24. This parallel circuit can be added to any of the pinched capacitor circuits described above. When the switches 56, 58, 60 are open, the gain of the integrator 12 is equal to that of the Suinocito capacitor circuit 10.
6 capacitors 24 only. First switch 5
6 and introduce the capacitor 62, and below, switch 5
Capacitors 64 and 66 are added to the circuit by sequentially closing capacitors 8 and 60. Next, in reverse order, place the switch next to it and disconnect the capacitors from the circuit one by one. capacitor 24.62.64
．． 66 and the capacity ratio is 1.000: 1.848; 1.
414:0.765, the 3rd, 5th, .
7.9.11 and 13 harmonic components and their sidebands can be lowered.

FIG. 6b shows a timing chart of switching signals S56, S58, S6o for switches 56, 58, and 60 of FIG. 6a. The preferred logical relationship between these switching signals produced by logic circuit 86 is shown in the truth table of Table 1. In this table, F□ is the logic level of the carrier signal, F3, F4, F
8 indicates the logic levels of signals having frequencies twice, four times, and eight times that of the carrier signal, respectively.

Table ■ 0000000 0001100 0010110 0011.111 0100111 0101110 0110100 0111000 1000000 1001100 1010110 1011111 1100111 1101110 1110100 1111000

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modulation device, FIG. 2a is a circuit diagram showing an example of the basic configuration of the switched capacitor circuit of FIG. 1,
Figure 2b is a timing chart of the control logic of the switch in Figure 2a, Figure 3a is a circuit diagram showing another configuration example of the Swissotete capacitor circuit in Figure 2a, and Figure 3b is a control logic for the switch in Figure 3a. logic timing chart,
FIG. 4a is a circuit diagram showing another example of the configuration of the Suinotito capacitor circuit shown in FIG. 1, FIG. 4b is a timing chart of the control logic of the switch shown in FIG. 4a, and FIG. FIG. 5b is a timing chart of the control logic of the switch in FIG. 5a; FIG. 6a is a circuit diagram showing yet another example of the configuration of the switched capacitor circuit in FIG. 1; circuit diagram,
FIG. 6b is a timing diagram of the control logic for the switch of FIG. 6a. 8.82.83.84.85.86: Logic circuit 12: Integrator 10.10”, to 10 105.106: Switched capacitor circuit 24: Main capacitor 20.22.26.28.30. 32 varnish inches 62.
64.66: Auxiliary capacitor 56.58.60: Auxiliary switch Patent applicant Raycal Parts Inc. (1 other person) Fig 3b 9L Patent Application No. 7021'-7b 2, Title of Invention 7'+ r -j-1-N-1\ ',,'9
E 115-p, Relation to the amended person's case Address of patent applicant
, -- Te, To 4, 1:1t within the proxy box (no, yuri, - entry 61)) 14--

Claims (1)

[Claims] (1) A switched capacitor modulation device that modulates a carrier signal with a modulation signal to form a modulated signal.
a first human power to which one modulation word is applied, a second human power to which a plurality of switching signals are applied, an output for applying a sample modulation signal, and a main power having first and second electrodes. switching means comprising capacitive means and a plurality of binary switches for connecting said first and second electrodes to said input and output in response to a switching signal; Logic means for generating the switching signal in response to a clock signal having a signal, and integrating means for detecting the modulated signal in response to the distorted modulation signal. (2. 1.9 in the modulation device of claim 1,
The plurality of binary switches include at least first, second, and third binary switches.
and a fourth switch, the first electrode is connected to the first human power via the first switch and connected to a common ground via the second switch, and the second electrode is connected to the third switch. (3) In the modulation device according to claim 2, the logic means In one half cycle, the main capacitive means is operated by generating a switching signal that closes the first and fourth switches and opens the second and third switches during one half cycle of the clock signal. 1.81, and a switching function that opens the first and fourth switches and closes the second and third switches during the remaining half period of the clock signal. (4) In the modulation device according to claim 3, the logic means discharges the main capacitive means in a half cycle of the carrier signal stream 2.
During one half cycle of the clock signal, the main capacitive means is charged with the modulating signal by generating a switching signal that closes the first and third switches and opens the second and fourth switches. In addition, during the remaining half period of the clock signal, the main capacitive means is discharged by generating a switching signal that opens the first and third switches and closes the second and fourth switches. . (5) In the modulation device according to claim 4, a fifth switch of an operational amplifier having an input and an output, and a delay means consisting of storage capacitive means are provided, and the input of the operational amplifier is connected to the fifth switch through the fifth switch. Attended by one person,
The output of the operational amplifier is connected to the first switch, and the storage capacitive means is connected between the input of the operational amplifier and the common ground. (Insertion 1.) The fifth switch is controlled by the same switching signal as the fourth switch. (6) In the modulation device d according to claim 3, the switching means includes a fifth switch 7 for connecting the electric power to the second electrode in response to a switching signal S other than the one described above.
said logic means generate said switching signal S which opens said fifth switch during said first half-cycle of the carrier signal; , the second switch is closed, the first and fourth switches are open, and during the first half cycle of the clock signal, the fifth switch is closed and the third switch is closed.
The switch is opened to charge the capacitive means with the modulating signal, but during the second half period of the clock signal, the fifth
generating a switching signal to open the switch and close the third switch to discharge the capacitance tip means; (7) In the modulation device according to claim 3, the switching means includes a fifth switch that connects the output to the first electrode in response to a switching signal S' other than the one described above, and the logic means generating said switching signal S' which opens said 52nd switch during said first half-cycle of the carrier signal; further said logic means causes said switching signal S' to close said fourth switch during said second half-cycle of the carrier signal; Then, the second and third switches are left open, and during the first half period of the clock signal, the first switch is closed and the fifth switch is opened to charge the carrier stabilizing means with the modulation signal, but when the second half of the clock signal generating a switching signal for opening the first switch and closing the fifth switch for discharging the capacitive means during a half cycle of the first switch; (8) In the modulation device according to claim 5, 6 or 7, the switching means includes shaping means consisting essentially of a plurality of auxiliary capacitive means and a plurality of auxiliary switches responsive to an auxiliary switching signal. each auxiliary capacitive switching means is connected across the main capacitive means via a corresponding auxiliary switch, and the logic means generates the auxiliary switching signal for operating the auxiliary switch at a frequency that is an integer multiple of the carrier signal. to do.