JPS6118363A - Pwm control circuit of inverter device - Google Patents

Abstract

PURPOSE:To obtain a PWM signal generator of an inverter which is facilitate in the synchronization of an inverter frequency with a carrier frequency by composing a PWM control circuit of all digital elements, thereby simplifying the entire circuit configuration. CONSTITUTION:An inverter frequency command (f command) applied in a binary value is converted by a frequency converter 7 into a clock A of frequency proportional to the value, and input to a ring counter 8 and a frequency divider 9. The prescribed value is set in advance in the counter 8, and the counting operation of the clock A is repeated with the value as one period. Phase information A obtained from the counter 8 is applied to memory cells 10, 11, a calculation is further performed in the first calculator 12, various control data are output. The divider 9 divides the clock A on the basis of the output data to output a clock B. The carrier frequency and the inverter frequency are switched by switching the dividing frequency ratio of the divider 9 and the set value of the counter 13.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to PWM (pulse width modulation) approximated to a sine wave.
The present invention relates to a PWM control circuit of an inverter device that obtains a signal output.

[Conventional technology]

A conventional device of this type is shown in FIG. However, FIG. 1 only shows one set of PWM signal generation parts. In the figure, 1 is a sine wave oscillator that outputs a reference sine wave according to a frequency command and a voltage command, 2 is a triangular wave oscillator, and 3 is a comparator.

Next, the operation will be explained with reference to FIG. That is, the sine wave oscillator 1 outputs a reference sine wave according to the input frequency command and voltage command. On the other hand, the triangular wave oscillator 2 generates a triangular wave (hereinafter referred to as
The two sets of oscillator outputs are compared by a comparator 3. Then, the output of the comparator 3 is turned OFF during an interval where the carrier is larger than the reference sine wave, and turned ON during the opposite interval, whereby a PWM control signal output approximated to a sine wave is obtained from the comparator 3.

This relationship between the champions is shown in the waveform diagram of FIG. In the figure,
4 is a reference sine wave output from the sine wave oscillator 1, 5 is a carrier output from the triangular wave oscillator 2, and 6 is a sine wave approximation PWM control signal output from the comparator 3.

The PWM control circuit of a conventional inverter device is configured as described above, so if the circuit is configured with analog elements, an adjustment element for the sine wave or triangular wave oscillation signal voltage is essential, and adjustment is not only troublesome, but also digital. When constructed from elements, it had the disadvantage of requiring a large number of parts and making the circuit complex.

In addition, in the conventional circuit configuration, it is necessary to synchronize the carrier frequency fe and the inverter frequency f, and to synchronize the carrier frequency fe and the inverter frequency f.
There is a drawback that many additional circuits are required to switch the value of f ) in accordance with f.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and basically the configuration of the PWM control circuit is made up of all digital elements, including three counters, some memory elements, and an arithmetic circuit. By using , the overall circuit configuration can be simplified, and the carrier frequency fc and inverter frequency f can be synchronized, and n corresponding to f (= f c/f
) It is an object of the present invention to provide a PWM signal generator for an inverter that allows for easy switching of values.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. First, in FIG. 3, 7 is a frequency converter (for example, a rate multiplier) that converts the frequency of the input clock signal in proportion to the binary inverter output frequency command (hereinafter referred to as f command) and outputs it as clock A. , 8 is front d
A ring counter (for example, a 16-bit self-ring counter) that counts the frequency of its own lock A and uses one period of the counting operation as one period of the inverter output. frequency f
In response to the ratio n (=f c/f ), arithmetic circuit 1, which will be described later,
A frequency divider (e.g., 8-bit color/digital) that divides the frequency by the count value set by 2 and outputs it as clock B, 10
and 11 are storage elements for output data that configure one carrier period to be output next based on the count value of the ring counter 8, for example, the third and fourth periods among the six periods. A ROM 12 outputs data proportional to the second period (hereinafter referred to as THain data) and data proportional to the second and fifth periods (hereinafter referred to as Tssin data); 12 is a first arithmetic circuit; TM a from the memory element 10.11 every one carrier period in
A command (hereinafter referred to as fmax command) indicating the maximum frequency that the inverter device can output sets the setting value of the counter 13, which will be described later, corresponding to the duration of one carrier period in which in data and TB gin data are input and output to the customer. ) and inverter output voltage command (hereinafter abbreviated as ■ command)
Furthermore, calculations are executed in response to a command indicating n (= f c/f ) (hereinafter abbreviated as n command ξ), etc., and stored in the internal memory described later, and one carrier period calculated previously is constructed. Setting values corresponding to the durations of the six periods are sequentially set each time a synchronization signal A is input from a counter 13, which will be described later.Furthermore, at the end of one carrier period, a synchronization signal B is input to the second calculation circuit 14. Output.

13 counts the clock B output from the frequency divider 9, and when the clock B output from the frequency divider 9 has been counted, the synchronizing signal A is sent to the first arithmetic circuit 12 and the second arithmetic circuit 1.
4 (e.g., 8-bit counter)
, 14 is a second arithmetic circuit that takes in the count value of the ring counter 8 in accordance with the synchronization signal B from the first arithmetic circuit 12, and calculates and outputs one carrier period to be output next. That is, 6 periods of CIPWM signal (33 phases of U, V, W)
The memory element 15 calculates the address of the memory element 15 in which the potential data of is stored and stores it in an internal memory to be described later, and also stores the potential data of the PWM signal of each phase of each period calculated one cycle before. the address of counter 1
The signals are output sequentially by the synchronization signal B from 3. 15 is based on the address signal from the second arithmetic circuit 14. It is a storage element such as a ROM that outputs the potential of the PWM signal of each phase.

Next, the operation of the present invention will be explained below. First, FIG. 4 shows an example of the basic principle of the pulse width modulation method used in the present invention. In the figure, the PWM control signal for one phase has a reference waveform of 16 and triangular wave carrier 17
This method is used to compare. That is, in the section where the triangular wave carrier 17 is larger than the reference waveform 16, the "L level" is output, and in the opposite section, the "1H" level is output. Furthermore, in order to obtain PWM control signals for three phases, three sets of the same waveform with phases shifted by 120 degrees are prepared as reference waveforms, and these are compared with one triangular wave carrier.

In the case of this modulation method, only one phase of the PWM control signal is fixed at the "H" level #level for each 60° interval, and the remaining two phase signals are turned ON. ,
Voltage control is performed by turning it off.

Figure 5 shows a PWM signal almost equivalent to that shown in Figure 4 above.
1 shows a principle diagram for performing control using the circuit of the present invention. A reference pattern 18 in FIG. 5 indicates a boundary line at which one of the PWM signals of each phase switches, based on the three-phase reference waveform in FIG. 4.

The three-digit numbers marked in each area surrounded by these boundary lines indicate the levels of the U-phase, ■-phase, and W-phase PWM control signals from the left, and 1 indicates the "H" level and 0 is “L#”
It means to output the level.

Here, when the triangular wave carrier 19 is run over the reference pattern 18 of FIG. 5, a PWM control signal is obtained as in the case of FIG. 4. In one embodiment of the present invention, in order to simplify the processing, a carrier is used that reciprocates linearly up and down in one period section of the triangular wave carrier 19 at the center phase of the triangular wave, as shown in the carrier 20 of FIG. to substitute. In this case, the phase of the carrier 20 is 360/n (de
g) (The up and down reciprocating time of the carrier 20 is the time equivalent to 360/n (deg) =
1/f c).

From the above, the level of the PWM control signal of each phase is determined by the number of the area where the carrier 20 is currently located,
Further, the duration of each potential is determined by the time it takes the carriers 20 to pass through that region. Furthermore, in order to perform voltage control, it is sufficient to change the amplitude of the carrier 20 in inverse proportion to the output voltage, as in the case of normal sine wave comparison.

Next, the operation of the circuit shown in FIG. 3, which embodies the above-described method for forming a PWM control signal, will be described.

FIG. 6 is a diagram for explaining the detailed operation of each part of the circuit of FIG. 3.

In FIG. 3, an inverter frequency command (f command) given in binary is converted by a frequency converter 7 into a clock A having a frequency proportional to the value, and is input to a ring counter 8 and a counter 9. Then, the maximum output frequency f max of the inverter device and the clock A from the frequency converter 7 are stored in the ring counter 8 in advance.
A value of the ratio fmax/f1max of the highest frequency f1max is set, and as shown in FIG. 6, the counting operation of the clock A described above is repeated with this set value as one cycle. One cycle of this counting operation corresponds to one cycle of the output of the inverter device. In addition, the inverter maximum output frequency frn
When changing ax, a count value inversely proportional to the fmax command may be set in the ring counter 8.

The memory elements 10 and 11 each store data proportional to the duration of the horizontally lined area and the diagonally shaded area of the reference pattern 2'1 in FIG. 6 for a 60° section. These data are, for example, T in FIG.
This corresponds to M sin data 25 and Tssin data 26. By extracting the appropriate lower bit of the count value of the ring counter 8 mentioned above, phase information A (24 in FIG.
create. Furthermore, the memory element 10.11 outputs TMsin data and TB sin data corresponding to this phase information A to the first arithmetic circuit 12. The first arithmetic circuit 12 first operates a counter 13 (described later) in response to the fmax command and the n command.
The count value n2 data of the half carrier interval is calculated. Next, the TM sin data and T3 sin data read every carrier cycle from the memory element 10.11 are multiplied by the V command (data corresponding to the V command is stored in the memory element 10.11, and 1M data and Ts data proportional to the command are calculated by adding corrections corresponding to the f max command and fc command. Furthermore, To data is calculated by subtracting both the 1M data and Ts data from the previously calculated n2 data.

These calculated 7M data% TS data and TO data indicate that, among the areas of the reference pattern 21 in Fig. 6, the sun rays pass through the area indicated by horizontal lines, the area indicated by diagonal lines, and other areas, respectively. The count value of the counter 13, which will be described later, corresponds to the time for Once these data are calculated, they are stored in the calculation memory 30 as shown in FIG. 6 as, for example, six pieces of data, and are sequentially set in the counter 13 in the next carrier interval.

While the first arithmetic circuit 12 is executing the above-described data arithmetic operation, the first arithmetic circuit 12 simultaneously receives previously calculated setting data corresponding to each period constituting one carrier section from a synchronizing signal A from a counter 13 (to be described later). Each time the above-mentioned TO+TS+TM is inputted, the above-mentioned TO+TS+TM
Sequential counter 13 in the order of HTM r TS r TO
Set to . Furthermore, when all six pieces of data in one carrier section have been output, the synchronization signal B is output to the second arithmetic circuit 14, and the above-mentioned calculation memory 3
0 and the contents of the output memory 31, and repeat the above operation.

Further, the first arithmetic circuit 12 changes the set values of the frequency divider 9 and the counter 13 in response to the fC command and the fma:c command.

The frequency divider 9 has a value set by the first arithmetic circuit 12 so as to have a value proportional to the count time of the counter 13 (given by 1/nf, the time of one carrier period determined by the n command and f command). , divides the frequency of the aforementioned clock A and outputs it as clock B. Therefore, the ratio n (possible c/f) between the carrier frequency fe and the inverter frequency f is switched by adjusting the frequency division ratio of the frequency divider 9 and the set value of the counter 13. Also, since the frequency of clock A is proportional to the f command, the reference pattern of the inverter and the carrier are in a synchronous state (n = constant) while the set values t of the frequency divider 9 and the color/rear 13 are not adjusted. It has become.

The counter 13 stores data (the above-mentioned Tll)+TS calculated in the previous one carrier period by the first arithmetic circuit 12.
, TM data), the synchronization signal A is activated when the clock B from division period 9 is counted by the set value.
is output to the first arithmetic circuit 12 and the second arithmetic circuit 14. Based on this counter 13 operation, 'reference pattern 2' in FIG.
The duration of the potential of each phase shown in each region of 1 is defined. “The second arithmetic circuit 14 is provided with phase information B (23 in FIG. 6) whose value changes every 30° interval by taking out an appropriate high-order bit of the count value from the ring counter 8 mentioned above. is input, and corresponding to this phase information B, for example, six periods constituting one carrier period in the phase in which the current carrier exists ('ro l 'rs l 'rM+'rM+TS
PWM control signal (t
The address of the memory element 15 in which the potential data (corresponding to the numbers marked in each area of the reference pattern 18 in FIG. 5) of the three phases (y, v, w) is stored is calculated. in this case,
For example, the address of the storage element 15 is determined using a data table corresponding to the phase information B as shown in FIG. 6, 27. A specific example of the data table is shown in FIG. 7th
In the figure, three sets of 3 given corresponding to phase information B
The digit data is the same as the numbers marked in each area of the reference pattern 18 in FIG. 5, but here it shows the address of the storage element 15 corresponding to each data.

The addresses of these potential data are temporarily stored as, for example, six pieces of data in the calculation memory 32 as shown in FIG.
is output to.

The second arithmetic circuit 14 executes the address arithmetic operation as described above, and at the same time inputs address data corresponding to the potential data of each phase to be output in each period constituting one carrier period calculated last time from the counter 13 described above. Every time the synchronization signal A is input, vo is output from the output memory 33 shown in FIG.
l VS + VM + "M r VS rV (," is sequentially outputted in the order of .Furthermore, when the tuning signal B is input to the first arithmetic circuit 12, the above-mentioned calculation memory 32
and output memory 33, and repeat the above operation.

In addition, when it is necessary to switch between forward rotation and reverse rotation of the inverter device, the second arithmetic circuit 14 uses the forward and reverse commands that specify the forward rotation and reverse rotation of the inverter as shown in FIGS. 6 and 7.
The memory element 15 selects between forward rotation and reverse rotation by switching between the forward rotation data table 27 and the reverse rotation data table 28 as shown in the figure. The potential of the PWM control signal of each phase at that point is output.

As described above, in the PWM control signal generation circuit of the present invention, as shown in FIG. By defining the output time of each potential data by the counting time of the counter 13, a PWM control signal substantially equivalent to that of FIG. 4 is output. In addition, two sets of memories (one for calculation and one for output) are prepared as memories for storing potential data and setting data for the counter 13, and while data is being output from one memory, the next one is being stored in the other memory. The data to be output during the carrier period is calculated and stored, and each time one carrier period is completed, these two
By switching between two memories, data can be output continuously.

Also, a clock A with a frequency proportional to the inverter frequency
One set of phase reference ring counters for counting (e.g., 16 bits = fc/f switching and two sets of counters for setting potential data output time in each period (e.g.,
It is characterized by the use of 8-bit).

In addition, in the above embodiment, PW constituting one carrier period
An example has been shown in which there are six potential data of the M signal and six set values of the counter 13, but in this case, the third data set and the fourth data set are exactly the same, so
By making these into one data set, it is also possible to configure one carrier period with five periods. Further, in the above embodiment, the carrier performs vertical reciprocating motion (corresponding to a triangular wave carrier), but it is assumed that the carrier only moves from top to bottom or from bottom to top (corresponding to a sawtooth p-wave carrier). ) cases can also be configured. In this case, since one carrier period consists of three periods, the number of times the potential data is output and the set value is set to the counter 13 is also three times during one carrier period.

In the above embodiment, as a pulse width modulation method, only one phase of the PWM control signal is fixed at the "H" level @L" level every 60° period, and the remaining two phase signals are turned ON.
, OFF shows the case where stain pressure control is performed, but the reference butter 77., which is stored in the memory element 10.11 in FIG. By changing the data of the second
It is also possible to form a PWM control signal using other modulation methods, such as a sine wave approximation PWM control signal as shown in the figure.

In addition, in the above embodiment, an example was shown in which two sets of counters (e.g., 8-bit counters) were used for switching n = f e/f and for setting potential data output time in each period. counters into a set of counters (e.g.
It can also be a 16-bit counter).

Further, in the above embodiment, the configuration is shown as a circuit, but it is also possible to replace the parts other than the frequency converter T in FIG. 3 with a microcomputer. In this case, the microcomputer is, for example, NEC1B781
Built-in 1 as ring counter 8 in Fig. 3.
A 6-bit counter is used as the counters 9 and 13, and a built-in 8-bit counter is used as the counters 9 and 13. Also, memory elements 10, 11, 15
The data table in the second arithmetic circuit 14 is stored in the built-in ROM. Built-in RAM is used as the calculation memory and output memory for storing potential data and setting data of the counter 13 in the second arithmetic circuit 12.14,
An input/output I10 port is used as an output terminal for PWM control signals (voltage data) of each phase, an input terminal for data such as control clock signals, (2) commands, fc commands, tmax commands, forward/reverse commands, etc.

The processing contents of the microcomputer are as follows:
An interrupt that occurs when the count value of a built-in 8-bit counter corresponding to counter 13 in the figure matches a set value is used. In the circuit shown in FIG. 3, setting data to the color/receiver 13 and address data to the memory element 15 are performed every time the synchronization signal A is input to the first arithmetic circuit 12 and the second arithmetic circuit 14. Instead of outputting, the microcomputer's counter interrupt processing program sets setting data to the counter and outputs the potential data of each phase to the I10 port. Further, other processing and calculations are performed by the main program. Furthermore, reading of data such as the ■ command, fc command, fmax command, forward/reverse command, etc. is performed by external interrupt processing.

〔Effect of the invention〕

As described above, according to the present invention, the PWM of the inverter
Since the control circuit is entirely composed of digital elements, there is no need for adjustment elements that would be required when the control circuit is composed of analog elements. In addition, by using a ring counter (for phase reference) that counts a control clock with a frequency proportional to the inverter frequency and two sets of counters, the value of the ratio n (= f c / f ) between the inverter frequency f and the carrier frequency fe can be determined. can be kept constant, and by adjusting the set values of the two counters in accordance with the n command, it is also possible to easily switch n during acceleration and deceleration. Furthermore, by switching the setting value of the ring counter according to the command, the highest frequency that the inverter can output can be changed, and the data table of the arithmetic circuit can be prepared for forward rotation and reverse rotation, and these can be switched according to the command. It is also possible to easily switch between forward and reverse rotation of the inverter device.

Furthermore, by replacing the circuit of the present invention with a microcomputer, the circuit can be made smaller and less expensive.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of a sine wave approximation PWM control circuit using a triangular wave comparison method for a conventional inverter device, and Fig.
FIG. 3 is a circuit configuration diagram showing an embodiment of the PWM control signal generation circuit according to the present invention. FIG. 4 is a waveform diagram showing the operation of the circuit shown in FIG. Waveform diagrams to show the principle, FIG. 5 is a diagram of the principle of three sets of p w M control signal formation according to the present invention, and FIG.
FIG. 7 is an explanatory diagram of the operation of an embodiment of the present invention shown in FIG.
The figure is a data table diagram corresponding to the phase information in the second arithmetic circuit of the embodiment shown in FIG. 3. 1... Sine wave oscillator, 2... Triangular wave oscillator, 3...
・Comparator, 4... Reference sine wave, 5... Triangular wave carrier, 6... Sine wave approximation PWM signal, 1... Frequency converter, 8... Ring counter, 9... Frequency divider , 10... memory element, 11... memory element, 12...
・First arithmetic circuit, 13...Counter, 14...Second
Arithmetic circuit, 15... Storage element, 16... Reference waveform,
17... Triangular wave carrier, 18... Reference pattern,
19... Triangular wave carrier, 20... Carrier, 21
... Reference pattern, 22 ... Counting operation of ring counter 8, 23 ... Phase information 2.24 ... Phase information 1
．． 25...TMlsin data (contents of memory element 10), 26...T5 sin data (contents of memory element 11), 27...data table for normal rotation, 2B...
Reversal data table, 29...first arithmetic circuit 12
30...Memory for storing setting data of counter 13 (for calculation), 31...Memory for storing setting data of counter 13 (for output), 32...Storing address data of memory element 15 memory (for calculation), 33.
. . . Address data storage memory (for output) of storage element 15, 34 . . . Output method of PW and M control signals. In the drawings, the same reference numerals indicate the same or equivalent parts. Figure 1 Figure 2

Claims (3)

[Claims] (1) A frequency converter that converts an inverter output frequency command of a PWM control type inverter device that converts AC or DC power into AC power of variable frequency and variable voltage into a first clock having a frequency proportional to the frequency command value; , a ring counter that counts the first clock and makes one cycle of the counting operation one cycle of the inverter output; and a ring counter that counts the first clock and makes the first clock correspond to a ratio of a carrier frequency and an inverter output frequency by a first arithmetic circuit described below. a frequency divider that divides the frequency by a value determined by the second clock and outputs it as a second clock; and a subdivision period that constitutes one carrier period that inputs the count value of the ring counter in one carrier period and outputs it in the next period. The corresponding setting value is a first command indicating the output voltage of the inverter, and
It is determined in response to a second command indicating the ratio between the carrier and the inverter output frequency, and stored in the internal memory, and the already determined preset data is sequentially applied to the counter in accordance with the first synchronization signal of the counter described later. a first arithmetic circuit that outputs a second synchronizing signal to a second arithmetic circuit described later at the end of one carrier period;
a counter that outputs a first synchronization signal corresponding to a value set by the arithmetic circuit to the first arithmetic circuit and a second arithmetic circuit described later; and a second synchronization signal from the first arithmetic circuit that outputs the counted value of the ring counter. The PWM signal value corresponding to each phase of each subdivision period of one carrier period to be inputted and output next is calculated and stored in the internal memory, and the PWM signal value of each subdivision period calculated last time is input to the counter. A PWM control circuit for an inverter device, comprising a second arithmetic circuit that sequentially outputs signals in synchronization with a first synchronization signal. (2) It has a plurality of storage elements that store PWM signal values for forward rotation and reverse rotation, and outputs switching between forward rotation and reverse rotation by switching the contents of the storage elements according to external signals for forward rotation and reverse rotation. 2. A PWM control circuit for an inverter device according to claim 1, further comprising a second arithmetic circuit configured to obtain data. (3) The inverter device outputs by switching the setting value of the ring counter and adding correction to the calculation data of the first calculation circuit according to the maximum frequency command indicating the maximum frequency that the inverter device can output. 2. The PWM control circuit for an inverter device according to claim 1, wherein the highest possible frequency is switched.