JPS61181130A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS61181130A
JPS61181130A JP60022291A JP2229185A JPS61181130A JP S61181130 A JPS61181130 A JP S61181130A JP 60022291 A JP60022291 A JP 60022291A JP 2229185 A JP2229185 A JP 2229185A JP S61181130 A JPS61181130 A JP S61181130A
Authority
JP
Japan
Prior art keywords
pattern
reticle
resist film
film
transmitting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60022291A
Other languages
Japanese (ja)
Inventor
Tsukane Hirokawa
広川 束
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60022291A priority Critical patent/JPS61181130A/en
Publication of JPS61181130A publication Critical patent/JPS61181130A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To enable the preparation of a minute pattern of high precision without repeating the conditions of lateration of dimensions when a reticle is designed, by a method wherein a half-transmitting portion pattern provided in a reticle is matched in position with a protuberant portion staged higher. CONSTITUTION:A reticle 6 is formed of a shielding portion (c) with a thick chrome film provided on a glass substrate 61, a half-transmitting portion (a) with a thin chrome film provided on the substrate, and a transparent transmitting portion (b). When exposure is conducted by means of this reticle 6 and with the same exposure amount, an exposure amount according with the thickness of a resist film 4 in the half-transmitting portion (a) and the transmitting portion (b) respectively cna be given, and consequently a resist film pattern having excellent precision as desired is formed. Concretely, an exposure energy applied to the resist film 4 is controlled in accordance with the film thickness, and the film thickness of the half-transmitting portion (a) is prepared in consideration of the film thickness of the half-transmitting portion (a) and that of the resist film 4.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明は、フォトプロセスを用いて半導体基板(ウェハ
ー)面にレジスト膜パターンを形成するための、フォト
マスクおよびそのパターン形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photomask and a pattern forming method thereof for forming a resist film pattern on a semiconductor substrate (wafer) surface using a photo process.

半導体集積回路(IC)はLS1.VLSIと高度に集
積化され、微細化されてきた。それは、高集積化・高密
度化される程、高性能化される利点があるからである。
The semiconductor integrated circuit (IC) is LS1. It has been highly integrated and miniaturized with VLSI. This is because the higher the integration and density, the higher the performance.

そのため、フォトプロセスでは、1μm程度、あるいは
、それ以下のサブミクロンの微細パターン(Fine 
Pattern)を形成されるようになってきた。
Therefore, in the photo process, submicron fine patterns of about 1 μm or less are created.
Pattern) has come to be formed.

一方、高集積化・高密度化と共に、半導体基板面は段差
が激しくなり、特に素子間の配線を多層に積層する場合
、パターン精度が低下し易く、断線が心配される状況で
ある。
On the other hand, with the increase in integration and density, the surface of a semiconductor substrate becomes more uneven, and especially when wiring between elements is stacked in multiple layers, pattern accuracy tends to decrease and there is a fear of wire breakage.

従って、フォトプロセスによってレジスト膜パターンを
形成する際、段差のある部分においても高精度な微細パ
ターンが形成されるよう、十分に配慮されなければなら
ない。
Therefore, when forming a resist film pattern by photoprocessing, sufficient consideration must be given so that a highly accurate fine pattern is formed even in portions with steps.

〔従来の技術] ところで、転写用のフォトマスクには、半導体基板に密
着させて露光する密着露光用マスクと、半導体基板と間
隔を保って縮小露光するレチクルとがあり、従来、フォ
トプロセスでは、密着露光のマスクが主体に用いられて
いたが、光学機械の進歩による精度の向上から、縮小露
光用のレチクルが汎用されるようになってきた。それに
は、レチクルが傷つきにくり、長寿命であることも、汎
用化される原因となっている。以下、レチクルを例とし
て、本発明を説明することにする。
[Prior Art] By the way, there are two types of photomasks for transfer: a contact exposure mask that exposes the semiconductor substrate in close contact with the semiconductor substrate, and a reticle that performs reduced exposure while maintaining a distance from the semiconductor substrate. Conventionally, in the photo process, Masks for close-contact exposure were mainly used, but with improvements in precision due to advances in optical machinery, reticles for reduction exposure have come into widespread use. The fact that the reticle is scratch resistant and has a long lifespan is another reason for its widespread use. The present invention will be explained below using a reticle as an example.

第4図は従来のフォトプロセスにおける、段差のある半
導体面を露光する露光工程の断面図を示している。本例
は半導体基板(被処理基板)1面に、膜厚1μm程度の
多結晶シリコン膜からなる第1層の配線2が設けられ、
その上に膜厚1μmの燐珪酸ガラス膜からなる絶縁膜3
を被覆し、次いで、絶ff1111i3に直径1.8μ
mφのスルーホールを開ける目的で、レジスト膜4を塗
布し、このレジスト膜をレチクル5によって露光してい
る状態図である。尚、レチクルは実際には5〜10倍に
拡大したパターン寸法であるが、図には判り易くするた
め、縮小して形成パターンと同じ寸法で示している。
FIG. 4 shows a cross-sectional view of an exposure process in which a semiconductor surface with a step difference is exposed in a conventional photo process. In this example, a first layer of wiring 2 made of a polycrystalline silicon film with a film thickness of about 1 μm is provided on one surface of a semiconductor substrate (substrate to be processed).
On top of that is an insulating film 3 made of a phosphosilicate glass film with a film thickness of 1 μm.
and then coat the absolute ff1111i3 with a diameter of 1.8μ
This is a state diagram in which a resist film 4 is applied and this resist film is exposed with a reticle 5 for the purpose of opening a through hole of mφ. Note that the reticle actually has a pattern size enlarged 5 to 10 times, but in order to make it easier to understand, the reticle is shown reduced in size to have the same size as the formed pattern.

図において、51はレチクル5のガラス基板、52はク
ロム膜パターンである。従って、レジスト膜4はポジ型
レジストを用いており、露光工程後、露光部分のレジス
ト膜が現像によって溶解除去されて、窓部A、Bを設け
たレジスト膜パターンが形成され、そのレジスト膜パタ
ーンを保護膜として、絶縁膜3をエツチングして窓あけ
される。
In the figure, 51 is a glass substrate of the reticle 5, and 52 is a chrome film pattern. Therefore, the resist film 4 uses a positive resist, and after the exposure process, the exposed portion of the resist film is dissolved and removed by development to form a resist film pattern with windows A and B. Using this as a protective film, the insulating film 3 is etched to form a window.

[発明が解決しようとする問題点コ ところで、レジストを塗布すると、レジストは流動性の
ある液体であるから、図示のように、レジストI!it
4の表面が平坦になって、第1層の配線2が設けられた
絶縁膜3の上には、レジスト膜が薄く (例えば、膜厚
0.8μm)形成され、他の絶縁11* 3の上には厚
いレジスト膜(例えば、膜厚1.8μm)が形成される
[Problems to be Solved by the Invention] By the way, when a resist is applied, since the resist is a fluid liquid, as shown in the figure, the resist I! it
A thin resist film (for example, 0.8 μm thick) is formed on the insulating film 3 on which the first layer wiring 2 is provided, and the surface of the other insulating film 11*3 is flat. A thick resist film (eg, 1.8 μm thick) is formed thereon.

従って、同一の露光量で全面を照射すると、窓部Aが最
適の露光量の場合は、窓部Bは露光不足になり、窓部B
が最適の露光量の場合は、窓部Aが路光過多となって、
所望通りの窓パターンを両方に形成できないと云う問題
がある。
Therefore, if the entire surface is irradiated with the same amount of exposure, if window A has the optimal exposure, window B will be underexposed, and window B will be underexposed.
If is the optimum exposure amount, window A will have too much path light,
There is a problem that a desired window pattern cannot be formed on both sides.

この問題は、半導体装置の高集積化・微細化に従って、
次第に大きくクローズアップしてきており、これはIC
の品質、信頼性に大きな影響を与えるものである。
This problem has become more difficult as semiconductor devices become more highly integrated and miniaturized.
It is gradually getting a bigger close-up, and this is an IC.
This has a major impact on the quality and reliability of the product.

そのため、現在ではレチクルに設計面より操作して、窓
部の寸法を変化させている。即ち、窓部Aを所望寸法よ
り小さくしておき、そうして、窓部Bに最適の露光量を
与える。そうすれば、窓部Aには露光過度の露光量が照
射され、その露光エネルギーのオーバーのために、窓部
Aの周囲にも露光エネルギーが潜り込んで露光され、そ
れを現像すると窓部Aが拡大して、ちょうど最適の窓部
Aの寸法をもったレジスト膜パターンが形成される。
Therefore, at present, the dimensions of the window are changed by manipulating the reticle design. That is, the window A is made smaller than the desired size, and the window B is given the optimum exposure amount. Then, the window area A is irradiated with an excessive amount of exposure light, and due to the excessive exposure energy, the exposure energy sneaks into the surrounding area of the window area A and is exposed, and when it is developed, the window area A is exposed. After enlarging, a resist film pattern having exactly the optimum dimensions of the window portion A is formed.

これは、レチクル作成時に窓部Aの寸法を調整するので
あるが、このレチクルの作成時に寸法上で操作すること
は、レチクルの設計を複雑化することになる。レチクル
はIC上に描画するパターンの縮小量を見込んで大きな
パターンに設計し、更に、パターンの大小によって、露
光量を加減するための寸法操作を行なう。これらは一定
した法則を通用できるから、すべて、コンピュータの計
算制御でなされる。しかし、これに附加する、上記した
段差による寸法操作は、コンピュータの計算制御が複雑
化し、ウェハープロセスの全工程から人為的にチェック
を追加しなければ誤りが起こり易いゆ 本発明は、このような問題点を解消させるフォトマスク
とそれを用いるパターン形成方法を提案するものである
This involves adjusting the dimensions of the window A when creating the reticle, but manipulating the dimensions when creating the reticle complicates the design of the reticle. The reticle is designed to have a large pattern in consideration of the amount of reduction of the pattern to be drawn on the IC, and further, dimensional operations are performed to adjust the exposure amount depending on the size of the pattern. All of these processes are controlled by computer calculations, as fixed rules apply. However, additional dimensional manipulation due to the above-mentioned steps complicates computer calculation control, and errors are likely to occur unless manual checks are added to all steps of the wafer process. This paper proposes a photomask that solves these problems and a pattern forming method using the photomask.

[問題点を解決するための手段] その問題は、遮蔽部と透過部と半透過部とからなるパタ
ーンが設けられているフォトマスクを用い、且つ、段差
のある被処理基板上にレジスト液を塗布してレジスト膜
を形成し、次いで、曲部分には半透過部パターンが位置
合わせされ、且つ、凹部分には透過部パターン、または
、遮蔽部パターンが位置合わせされるフォトマスクによ
って露光して、レジスト膜パターンを形成する工程が含
まれるパターン形成方法によって解決される。
[Means for solving the problem] The problem was solved by using a photomask provided with a pattern consisting of a shielding part, a transparent part, and a semi-transparent part, and applying a resist solution onto a substrate to be processed with steps. A resist film is formed by coating, and then exposed using a photomask in which a semi-transparent pattern is aligned in the curved portion and a transparent pattern or a shielding pattern is aligned in the concave portion. This problem is solved by a pattern forming method that includes a step of forming a resist film pattern.

[作用] 即ち、本発明はレチクルに露光光線や電子線の露光量が
少なくなるような半透過部(半遮蔽部とも云える)を設
け、その半透過部パターンを段差の高い凸部分に位置合
わせして、露光・現像してレジスト膜パターンを形成す
る。
[Function] That is, the present invention provides a reticle with a semi-transparent part (also called a semi-shielding part) that reduces the amount of exposure to exposure light or electron beam, and positions the pattern of the semi-transmissive part on a convex part with a high step. Together, they are exposed and developed to form a resist film pattern.

そうすれば、レチクルの設計時に、寸法の変更条件を繰
り返えさなくても、均一な規則通りの設計でレチクルを
作成して、高精度な微細パターンを作成することができ
る。
In this way, when designing the reticle, the reticle can be created with a uniform and regular design, and a highly accurate fine pattern can be created without having to repeat the dimensional change conditions.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図は本発明にがかる一実施例のレチクル6の断面図
を示しており、凸状になって、レジスト膜が薄く被覆さ
れている窓部Aを露光するパター73部分は、薄くクロ
ム膜を被覆したパターンになっている。遮蔽部Cのクロ
ム膜の膜厚を1000人とすると、この部分は100人
 (数10人〜数100人)程度の膜厚を被覆する。
FIG. 1 shows a cross-sectional view of a reticle 6 according to an embodiment of the present invention, and a putter 73 portion that is convex and exposes a window A that is thinly coated with a resist film has a thin chrome film. It has a pattern that covers it. Assuming that the thickness of the chromium film of the shielding part C is 1000 people, this part will cover about 100 people (several tens to hundreds of people).

従って、本例では、ガラス基板61の上に厚いクロム膜
が設けられた遮蔽部Cと、薄いクロム膜が設けられた半
透過部aと、透明な透過部すとからレチクルが形成され
ている。
Therefore, in this example, a reticle is formed from a shielding part C in which a thick chromium film is provided on the glass substrate 61, a semi-transmissive part a in which a thin chromium film is provided, and a transparent transmitting part A. .

第2図はこのようなレチクルを用い、段差のある半導体
面を露光する露光工程の断面図を示し、本図は第4図に
対応する図で、同一部材には同一記号が付しである。こ
のレチクル6を用いて、レジスト膜4を同一の露光量で
露光すると、半透過部a、透過部すそれぞれのレジスト
膜の膜厚に合致した露光量を与えることができて、所望
通りの精度の良いレジスト膜パターンが形成される。即
ち、本発明は、レジスト膜4に加える露光エネルギーを
レジスト膜の膜厚に応じてコントロールする方法で、半
透過部の膜厚とレジスト膜の膜厚とを勘案して、半透過
部の膜厚を作成する。
Figure 2 shows a cross-sectional view of the exposure process in which a semiconductor surface with steps is exposed using such a reticle.This figure corresponds to Figure 4, and the same parts are given the same symbols. . When the resist film 4 is exposed with the same amount of light using this reticle 6, it is possible to give an exposure amount that matches the thickness of the resist film in the semi-transmissive part a and the transmissive part, thereby achieving the desired accuracy. A good resist film pattern is formed. That is, the present invention is a method of controlling the exposure energy applied to the resist film 4 according to the thickness of the resist film, and takes into account the film thickness of the semi-transparent part and the film thickness of the resist film. Create thickness.

そうして、このように形成したレジスト膜パターンを保
護膜にして、絶縁膜3をエツチングしてスルーホールを
形成すると、高精度な微細スルーホールが形成される。
Then, by using the resist film pattern thus formed as a protective film and etching the insulating film 3 to form through holes, highly accurate fine through holes are formed.

且つ、このようなレチクルは容易に作成することができ
る。第3図+8)〜(C)にその形成工程順断面図を示
しており、まず、同図(a)に示すように、ガラス基板
61上に膜厚1000人程度0厚いクロム膜62をスパ
ッタ法で被着し、その上にレジスト膜パターン65を形
成し、このレジスト膜パターン65を保護膜にして露出
したクロム膜をエツチングする。
Moreover, such a reticle can be easily produced. Figures 3+8) to 3(C) show cross-sectional views in the order of the formation process. First, as shown in Figure 3(a), a thick chromium film 62 of about 1000 layers is sputtered on a glass substrate 61. A resist film pattern 65 is formed thereon, and the exposed chromium film is etched using this resist film pattern 65 as a protective film.

エツチングはドライプロセスにより、例えば、四塩化炭
素ガスを反応ガスに用いる。
Etching is a dry process using, for example, carbon tetrachloride gas as a reaction gas.

次いで、レジスト膜パターン65を除去した後、同図価
)に示すように、再びスパッタ法で膜厚100人位の薄
いクロム膜62を被着し、その上に第2のレジスト膜パ
ターン66を形成する。このレジスト膜パターン66を
保護膜にして、再び被着したクロム膜62の膜厚100
人だけ除くようにコントロールエッチする。しかる後、
レジスト膜パターン66を除去すれる、同図(C)に示
すように完成される。この時、第2のレジスト膜パター
ン66を形成するためのマスクは、新たに作成する必要
はなく、前工程の段差の付くマスク (第1の配線をパ
ターンニングするマスク)を利用するだけで良い。
Next, after removing the resist film pattern 65, a thin chromium film 62 with a thickness of about 100 mm is deposited again by sputtering, and a second resist film pattern 66 is applied thereon. Form. Using this resist film pattern 66 as a protective film, the film thickness of the chromium film 62 deposited again is 100.
Control sex to exclude only people. After that,
The resist film pattern 66 is removed, and the process is completed as shown in FIG. At this time, there is no need to create a new mask for forming the second resist film pattern 66, and it is sufficient to simply use the mask with steps from the previous process (the mask for patterning the first wiring). .

このようにすれば、微細パターンも高精度に形成され、
それに用いるレチクルの作成も容易になる。
In this way, fine patterns can be formed with high precision,
It also becomes easier to create a reticle for use.

上記例は、ポジ型レジスト膜によって説明しているが、
ネガ型レジスト膜の場合は遮蔽部と透過部とが逆転する
だけで、同様にして高精度な微細パターンが形成される
。また、レチクルの作成も容易である。
The above example is explained using a positive resist film, but
In the case of a negative resist film, a highly accurate fine pattern can be formed in the same way by simply reversing the shielding part and the transmitting part. Furthermore, it is easy to create a reticle.

尚、レチクルの代わりに、本発明を密着露光用のマスク
に適用できることは云うまでもない。
It goes without saying that the present invention can be applied to a mask for contact exposure instead of a reticle.

[発明の効果] 以上の説明から明らかなように、本発明によれば段差の
あるIC面に高精度にパターンニングできて、ICの信
頼性1品質の向上に役立つものである。
[Effects of the Invention] As is clear from the above description, according to the present invention, patterning can be performed with high accuracy on an IC surface having a step, which is useful for improving the reliability and quality of an IC.

且つ、そのような転写マスクの作成も難しくない。Furthermore, it is not difficult to create such a transfer mask.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明にがかる一実施例のフォトマスクの断面
図、 第2図はそれを用いた露光工程を示す断面図、第3図(
a)〜(C)はそのフォトマスクの作成工程順断面図、 第4図は従来の露光工程を示す断面図である。 図において、 ■は半導体基板、   2は第1の配線、3は絶縁膜、
      4はレジスト膜、5.6はレチクル、  
51.61はガラス基板、52、62は厚いクロム膜、
63は薄いクロム膜、65、66はレチクル作成用レジ
スト膜パターン、aはレチクルの半透過部、 bは透過部、      Cは遮蔽部、A、 Bはレジ
スト膜4の窓部 を示している。 代理人 弁理士 松 岡 宏 四 部 第2図 第3図
FIG. 1 is a cross-sectional view of a photomask according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an exposure process using the photomask, and FIG.
A) to (C) are cross-sectional views in the order of steps for producing the photomask, and FIG. 4 is a cross-sectional view showing a conventional exposure process. In the figure, ■ is a semiconductor substrate, 2 is a first wiring, 3 is an insulating film,
4 is a resist film, 5.6 is a reticle,
51 and 61 are glass substrates, 52 and 62 are thick chromium films,
63 is a thin chrome film, 65 and 66 are resist film patterns for forming a reticle, a is a semi-transparent part of the reticle, b is a transparent part, C is a shielding part, and A and B are window parts of the resist film 4. Agent Patent Attorney Hiroshi Matsuoka Part 4 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims]  段差のある被処理基板上にレジスト液を塗布してレジ
スト膜を形成し、次いで、凸部分には半透過部パターン
、または遮蔽パターンが位置合わせされ、且つ、凹部分
には透過部パターン、または、遮蔽部パターンが位置合
わせされるフォトマスクによつて露光して、レジスト膜
パターンを形成する工程が含まれてなることを特徴とす
るパターン形成方法。
A resist solution is applied to a substrate to be processed with steps to form a resist film, and then a semi-transparent pattern or a shielding pattern is aligned in the convex portion, and a transparent pattern or a shielding pattern is aligned in the concave portion. 1. A pattern forming method comprising the steps of: forming a resist film pattern by exposing the shielding portion pattern to light using a photomask aligned with each other.
JP60022291A 1985-02-06 1985-02-06 Formation of pattern Pending JPS61181130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60022291A JPS61181130A (en) 1985-02-06 1985-02-06 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60022291A JPS61181130A (en) 1985-02-06 1985-02-06 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS61181130A true JPS61181130A (en) 1986-08-13

Family

ID=12078643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60022291A Pending JPS61181130A (en) 1985-02-06 1985-02-06 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS61181130A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335276B1 (en) 1998-11-26 2002-01-01 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US6649934B2 (en) 1998-12-12 2003-11-18 Samsung Electronics Co., Ltd. Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same
US7602456B2 (en) 2006-05-19 2009-10-13 Mikuni Electoron Co. Ltd Method of manufacturing LCD apparatus by using halftone exposure method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335276B1 (en) 1998-11-26 2002-01-01 Samsung Electronics Co., Ltd. Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
US6649934B2 (en) 1998-12-12 2003-11-18 Samsung Electronics Co., Ltd. Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same
US7602456B2 (en) 2006-05-19 2009-10-13 Mikuni Electoron Co. Ltd Method of manufacturing LCD apparatus by using halftone exposure method

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