JPS61180355A - User's interface processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This disclosure relates to the area of computer networks and to specialized processors that operate maintenance subsystems for networks.

Mutual Related Patent Applications This application was filed by David Andrew A.
October 1984 by the invented sound ndreasen
The application was filed on April 25, 2013, and was filed under the title ``Maintenance Subsystem for Computer Networks'' (Maintenance Subsystem for Computer Networks).
nc(3S system For Com
664.670, entitled ``Puter N etwork''.

11911. In the design and development of computer system networks, what limits must be drawn in order to provide an optimal system and in terms of economic factors, size and space factors, and diversity of control of the system. In order to decide which, multiple considerations and trade-offs must be balanced.

The computer network system described herein connects the units in a manner that maintains a very high degree of reliability for use with various peripheral types of equipment as well as data communications and telephone lines to remote terminals. is designed to provide rapid transfer of data between and rapid processing of data by a central processing unit.

The system is configured such that each of the various elements and units, when initiated, provides its own self-test routines and reports results and information to a maintenance processor called user interface processor 100. This processor communicates with various remote terminals and a "data link processor °'
It operates in conjunction with various types of peripheral devices through a uniquely designed I10 subsystem that handles units called . These types of data link processing units are described in U.S. Patent No. 4.415.98.
No. 6: No. 4,392,207: No. 4.313.162
No. 4.390.964 and No. 4.386.41
They are described in their earlier form in No. 5.

The maintenance subsystem included here is a maintenance subsystem for the various parts of the system so that self-test data is collected and sent to a remote diagnostic unit, which is a central diagnostic unit for numerous computer networks in many different locations. interconnected to elements. The remote terminal performs basic diagnostic routines on any computer network that has a problem and pinpoints the specific cause and location of the trouble.
F sends a message that clearly indicates that the local operator can correct the fault by changing the card, replacing the module, or adjusting any other specified fault or malfunction. can.

OS once! A user interface processor according to this disclosure includes:
A specialized processor known as a maintenance processor, which is a computer that includes a central processing unit that is connected to a number of remote peripheral devices via a data link processor and to other remote terminals via telephone lines. System network support.

A user interface processor or "maintenance processor" is an operator display that provides visual and diagnostic information to various elements of the network, such as a data link processor to a central host processing unit and to remote peripheral devices. It provides an interface to the power control card that enables connections to the terminal and to external cabinets and to remote support centers for comprehensive diagnostic and fault-location services.

The user interface processor connects to the central host processing unit via a processor interface card and to various peripherals and terminals via a data link interface/superordinate slave port controller.

The 7M 0-column communication controller and communication power/output unit operate in conjunction with a set of timers and priority interrupt controllers to communicate with the main host processor for normal operating purposes and for maintenance and diagnostic services. ing.

To localize specific problems within any given computer network system, each of a series of local computer networks is checked locally in a self-test procedure and then referred to a remote support center for further comprehensive diagnosis. Connected. A network of many differently arranged computer systems
Connected to one remote support center that can service all of them on a time-sharing basis.

Overview Maintenance subsystem: The maintenance subsystem of the computer network is shown in Figures 1A and 1B.
1C and 1D.

As seen in these figures, the user interface processor is connected to all of the various elements of the computer system network, i.e., the user interface processor is connected to the processor interface card and to the main host processor on the one hand; , on the other hand, it is connected to the power supply control card, the maintenance card, the operator's display terminal and the various data link processors.

Therefore, user interface processor 100
These combinations of connected elements provide the basic operation and maintenance functions for a computer network. For example, user interface processor 10'0 may initialize and power up the entire computer network system. User interface processor 1
00 initiates a self-test procedure whereby each of the interconnected data link processors performs their own self-test, executes a check routine and sends the results back to the user interface processor. Additionally, the user interface processor connects to the power-down control card to provide maintenance and diagnostic information and data to a remote unit that then further performs diagnostics to determine the location of any fault areas in the system. can bring.

In general, the user interface processor will initiate its own "self-test" routines to verify that it is in proper operating condition and display the results on the operator's display terminal.

Processor interface card: FIG. 1A in the maintenance subsystem.

The processor interface card 40 of FIG.
It is used to provide the basic system clock and also provides the 8 MHz data link interface power/output clock. This processor interface card 40 provides an interface to the processor backplane and also provides a unit called a system event analyzer 40e. In addition, the PIC uses a 4000 part history trace 40h to maintain the history of any selected input signal.
6- Provides a pid word. Roughly, this PIC
provides 16 bytes of memory that holds error correction pits for control store in the user interface processor.

Power Control Card (PCC): The power control card 50 of FIG. 1A controls the power on/off sequence and will detect any failure to any of the power modules directly connected to the PCC. .

The PCC also monitors the cabinet for any atmospheric losses and over temperature to provide a sensing signal for this effect.

The power supply card communicates with the user interface processor via an 8-bit parallel bus.

The power control card also communicates with any remote devices using the R8-232G remote link interface. It can communicate with other power control cards on an external base using the two-wire R8-422 direct connect data communications protocol.

In addition to providing 256 bytes of non-volatile storage memory, the power supply IfII III card 50 also maintains battery backup with time-of-day functionality. It also provides an automatic restart option after an AC power line failure.

Description of the Preferred Embodiment: Figure 1A shows a user interface processor 100 as part of a network configuration. Output bus 100b of microprocessor 110 is connected to processor interface card 40 and to memory bus 30m which connects main processor 30 of FIG. 1B to memory control unit 32 and main memory 34.

In FIG. 1A, RAM 150 provides output to power control card 50 and erasable PROM 1 50 is connected to operator display terminal 100.

The power supply control card 50 (FIG. 1A) provides power up-down sequences; monitors for power supply failures; initiates automatic restart (in case of power failure); provides warnings that temperatures are exceeded; Provides automatic power on/off operation; provides "remote" power control of external cabinets; maintains an internal time clock; and functions to provide a communication path (data link) for remote support and diagnostic services.

The processor interface card 40 (FIG. 1A) includes a memory 34 (FIG. 18), a memory control unit 32,
The PIC 40 functions to provide control and data acquisition for diagnostic testing of the upper slave port 500 and the main processor 30; is provided. PIC/10 provides a hist file in Figure 1A for real-time tracking of microcode addresses (breakpoints); it provides 16 general-purpose links for intermittent fault tracking. This allows performance monitoring so that traps can be set to count the number of failure occurrences. PIC40 is
Main system processor 30 receives U[Pl for maintenance information regarding power-off, time, reload, etc.
A communication path (ALIL) to be able to communicate with oo
F register, cscp operator).

In FIG. 1B, memory bus 30II1 connects main processor 30 to memory control unit (MCU) 32 and to UIPloo.

Further, an upper dependent port 500 (HDP) is attached to the memory bus 30m, and this l-IDP 500 provides a DLr (data link interface) bus 5d to the I10 subsystem 500S and peripheral'! A message level interface (MLI) bus 51 is supplied to the 1/○ expansion module 500e connected to the A location.

FIG. 1C shows the main processor 3
2 shows in more detail the connection of UIPloo to a processor interface card (PCI) 40 that interconnects 0 and HDP 500.

FIG. 1D shows how the UIP 400 connects to the processor interface card 40 and main processor 30 on one side, and to the I10 data link processor 100.
d, maintenance card 100m, and 0DT
100t and a remote link 50m.

The user interface processor 1oO in FIG.
It is designated by the initials "UIP".

The user interface processor consists of one logic board that can interface to a data link interface (DLI) backplane and to four independent serial data communication interfaces.

Under certain software instructions, user interface processor 100 operates as a data link processor (
DLP) and will support burst rates of up to 8 Mbytes per second when operating as such. The user interface processor 100 may also be used as a high dependent port (HDP) supporting a burst rate of 50 K, bytes per second. Thus, the same card of hardware can be manufactured to take on different required features and functionality.

Kneading interface processor 100 operates on a maintenance principle, whereby cards in a computer system such as that of FIG. 1A may be separated and replaced. A combination of ``self-tests'' and ``peripheral tests-driver tests'' is used to isolate any faults to replaceable modules.

This is done by indicating to the operator (via the operator's display terminal, ODT, 100t) the identity of the failing board after the self-test is complete.

Therefore, user interface processor 100
is essentially a microcomputer system placed on a single printed circuit board. This system is
It contains several important components: (a) a 16-bit central processing unit 11 in Figure 1;
0; (b) 192 bytes (7) PROM170a
.

b (Figure 1): (c) RAM 15 reaching 1/2 MB of Figure 1
0a,b; (d) Programmable input-output ports <20
2a, 202b): (e) Serial data communication port (200a, 20
06); (f) I-destination interrupt: ]ntro-7 (PRITC80
0); (a) Programmable timer (PIT700)
(h) OL I-HDP controller 180 (D
(i) DLl Upper Dependent Port (HDP) 500 of FIG. 1B. The user interface processor 100 includes a modular block unit (M
odular B 1ock U net f
orr nput-output system
m) via the controller 180 and the UIO (General Purpose Input Output) Can communicate with the host computer via the backbrain.

The user interface processor can simulate a DLI upper subordinate port, thus allowing it to communicate with the data link processor on a common basis without a "distribution card."

It is comparable to the distribution cards used earlier. A description of the data link processor and the use of the ``distribution card'' describes the I10 subsystem (T
/OS ubsysteIIIU+5ina Da
U.S. Pat.
Input output subsystem U
SinOCard-Reader Periphera
No. 4 U.S. Pat.
．． No. 390.964.

The user interface processor includes a backplane interface to a bus known as a backplane maintenance bus. These backbrain lines can be used to initiate data link processor self test routines and read the results of a given data link processor's self test when driven onto the backplane.

In this 1Ffl presentation, the two aforementioned user interface processor ports will be referred to as DLP and HDP, respectively.

The user interface processor 100 of FIG.
A microprocessor-controlled system that includes: (i) a microcomputer subsystem (110
): (ii) Data link interface controller (180): (iff) Upper subordinate port controller (180
); These three units connect the user interface processor to the host computer (30, 32, 34 of FIG. 1B) via the DLI controller 180 (FIG. 1).
) and further communicates with the upper subordinate port 500 of FIG. 1B.
The data link processor 100d of FIG. 1D is connected to the I10 backplane via the I10 backplane.

U[Ploo has some communication constraints in this regard.
data link interface) controller (180
), which itself does not provide ML■ (message level interface) and simply backplane 01! It only provides an interface. in this regard,
The superior dependent port 500 provides these functions to itself in firmware, so that the
It cannot be used with distribution cards, routing modules, or base control cards as implemented in the data link processor configuration described in No. 0.964. This particular upper slave port 180 of FIG. 1 must be used on a base that provides an 8 MHz clock such as that provided by the maintenance card 100m of FIG. 1D.

Microprocessor Subsystem The microcomputer subsystem includes both serial and parallel interfaces used to perform data communication operations.

The microprocessor subsystem consists of several elements: (I) a microprocessor 110 (such as the Intel 8086); (If) 512 bytes of dynamic RAM (1
50a, 6): (I[1) 192-byte PROM (EPRO
M) 170; (■) Four serial data communication ports (200a, b,
202a, 6): (V) 6 parallel I/O ports (407, 408, 4
09 two units): (V1) Programmable interval timer (PIT70
0): (■) Programmable interrupt controller (PRrT
c800) These elements are shown in FIG.

Microprocessor 110: Microprocessor 110
is used to drive user interface processor 110 and is located at IN location 8086-2 (i
8 MHz chip designated as APX-86/10). This microprocessor chip is manufactured by Intel Literature D.
I)t, 3065 Bowers Avenue,
5anta C1ara, Ca, 95051)
Published by Microprocessor and Peripheral Handbook (M 1croprocessor).

r and Peripheral Handbook
) -1983 (Ordanan/<210844-
001)'' in the Intel publication published on pages 3-1 to 3-24.

This processor is a high-performance 16-bit CPU implemented in 8MO8 technology and packaged in a 40-bin dual-inline package. This processor has 64
With an I10 address of 1, up to 1 Mbyte of memory can be addressed. Since this 8086 microprocessor is used only in a single-processor situation, it is operated in minimal mode and therefore generates its own path control signals.

Dynamic RAM 150: Microprocessor 11
0 provides access to a 128 byte dynamic RAM array. Array 150 of FIG. 1 is organized as 46K by 18 bits and is byte-addressable by microprocessor 110. Array 150 of FIG. RAM array 150 is controlled by a dynamic RAM controller chip, the preferred element of which is a National DP8409. This chip is manufactured by National Semiconductor Corporation (Natio
nal Sem1conductor Corp.
, 2900 Semiconductor Dri
ve, 5anta C1ara, Ca.

95051), pages 350 to 391 of the publication entitled NSI 6000 Databook, 1983.

This chip provides all the necessary multiplexing, driver and refresh logic for row and column addresses. This chip is operated in the fastest mode, so no standby state is required.

A “refresh request” is requested every 1.6 microseconds by a refresh counter, which also (in the microprocessor 110)
86 retention sequence to occur. Once this sequence is recognized, the RAM controller chip (DP8409) accesses one row of RAM 150, thus refreshing it.

The duration of this access is equal to the duration of a microprocessor memory access cycle, thereby reducing refresh overhead time to a minimum. In this type of configuration, the memory bandwidth is 3.83 Mbytes per second. This memory is also refreshed during "reset" periods of microprocessor 110, thus preventing corruption of the memory contents.

Error detection in RAM array 150 is performed by vertical byte parity via circuit 160 of FIG. Thus, each 16-bit word of RAM 150 has two parity bits, one for each byte.

Whenever a word or byte of dynamic RAM is accessed, parity is checked for each byte, regardless of whether the operation is a word-cycle or a byte-memory cycle. When such an error occurs, the microprocessor 11
0 sets its non-maskable interrupts to ``true'' and error logging is set after ``i'' (such implementation is
0 firmware) can be implemented to record bad addresses.

PROM memory 170: Storage of firmware for user interface processor 100 is 24KX
6 (8KX8) PRs arranged in 16 matrices
Provided by OM's Array. This therefore provides 48 bytes of storage. The PROMs used are of the 8KX8 erasable type and operate in roughly a single cycle (no wait). PRO
M memory 170 is mapped to the top point of the microprocessor memory map. This means that the microprocessor 110 (at address FFFF0 of 6)
This is due to the fact that it resets to this point.

Serial Ports: As seen in FIG. 1, the user interface processor 100 has two chips 200a called serial communication controller chips (Scc).
and 200b are used. In a preferred embodiment, these chips are 1315 Dell Aven
ue, Campbell, Ca.

Ziloo Corporation with address 95008
Manufactured by ZILO cation, part 285
30°“Counter/Firmware Technical Manual (counter/FirmwareTech
nical Manua1) entitled Ziloa
The chip is described in a publication published in March 1982 by the Corporation.

SCC chips 2ooa and 20ob each provide two independent serial full-duplex data communication channels with synchronous/asynchronous data rates reaching 1 Mbit per second. These chips can provide up to 250K bits per second with FM (Frequency-Modulation) encoding, and they can also deliver up to 250K bits per second with NRZI (Inverted Non-Return-to-Zero) encoding. It is possible to provide up to 125K bits per block.

The SCC chip has two receiver sections 2 in FIG.
32.234, each of which has a 3-byte FIFO (first-in-first-out register) that allows buffering of 4 bytes of data (including the receive data register) in receive mode. Min incorporates a single holding register along with the transmitter data register.

FIG. 2 shows typical internal features of the ZiloOZ8530SCG (Serial Communication Controller) 200.

These connect to remote terminals on serial data lines.
Channel A (215a) and Channel B (2156).

The control signals for these channels are channels A, 2
17a and for channel B, 217b“
Individual control and condition! ! ! ” is specified as.

An internal bus 212 connects these channels and control units to baud rate generator A, 210a and to baud rate generator B, 210b.

Internal bus 212 also connects to channel register 211a and channel B register 211b, and also has connections to internal control logic 220 and interrupt control logic 222, which connect to its 41 icpu pass card output circuit 224. .

The serial communications controller 200 is an operative part of the user interface processor 100 for use as an 'interrupt control device'. The controller is capable of driving a programmable interrupt vector in response to a microprocessor interrupt acknowledge signal.

The use of the cascaded outputs of the priority interrupt (PRITC800) controller (FIG. 1) allows the 5CC200 to operate as a slave interrupt controller. This method of usage enables the 5CC200 vector interrupt capability. While the serial communications controller chip has an "interrupt priority option", this feature is not used in the user interface processor since it is allowed for the interrupt control logic 222 of FIG.

By using two of the serial communication controller chips, this results in a total of four serial data communication lines, shown in FIG. 1 as lines 1 and 2 and lines 3 and 4. These four lines are routed through two external 4-brane connectors that allow the use of existing data communication paddle cards to provide an electrical interface for use with interfaces such as R8-232C or TDI. interfaced.

The serial communication controller 200 has several capabilities described below.

(1) SCC asynchronous, 5.6.7 or 8 bits per knee character - 1,1
-1/2. or 2 strokes - odd or even parity - 1, 16, 32 or 64x clock mode - break generation and detection - parity, overrun, and framing error detection (2) SCC bytes - distribution [10 knee internal or external Character synchronization - 1 or 2 sync characters in separate registers - Automatic sync character insertion and deletion - Cyclic Redundancy Check (cRC) generation/detection - 6 or 8 bit sync characters (3) SCC 5DLC/HDLC function car abort sequence generation - Automatic zero insertion and deletion - Automatic flag insertion between messages - Address field recognition - Field remainder processing - CRC generation/detection - SD with EDPJfE/loop entry and output
L loop mode (/1) and others (7) SCCI crab -NRZ, NR
Zl, FM Coding - Digital Phase-Locked Loop for Baud Rate Generator Synchronous Clock Recovery Period for 8 Channels SCC Register Function: All modes of communication used are established by the bit values of register 236.238 in Figure 3. .

When data is received or transmitted, the value of the read register (211a, 6) changes. These read status register values can facilitate software functionality for further register changes.

Referring to the block diagram of serial communication controller 200 in FIG. 2, the set of registers (211a and 211b) for each channel 17 (A and B) includes 14 write registers and 7 successive registers. Ten of the write registers are used for control, two are used for synchronization character generation, and two are used for baud rate generation.The remaining two write registers are: Shared by both channels; one is used as the ``interrupt vector'' and the other is used as the ``main interrupt control.'' Five successive registers represent the ``steady'' function and two registers for the baud rate. generator 2
10a, 210b; one is used for the "interrupt vector", one is used for the receiver buffer, and one is used to read the interrupt pending bit.

SCC Transmitter: The transmitter section 240 of the serial communication controller 200 is shown in FIG.

The transmitter section of the SCC uses an 8-pit “
It has a transmission data register 240, and a synchronization register or address register 238 (WR6
), synchronous key 1t register or 5DLC flag register 2
36 (WR7 in Figure 3) or transmission data register 24
“Transmission shift register” loaded from either 0
244.

In byte orientation mode, register WR6 (
238) and WR7 (236) may be programmed with a sync character.

In “single sync mode”, an 8-pit or 6-bit sync character is used in WR6, while 1
5-bit synchronization character in registers WR6 and WR7
``Bi-synchronous mode'' in

used in

In bit orientation mode, register WR7 (236)
The flags contained in the flags are loaded into the transmission shift register 244 of FIG. 3 at the beginning and end of a message.

If asynchronous data is being processed, then the third
Registers WR6 and WR7 in the figure were not used and the ``transmission shift register'' 244 was shifted out to the transmission multiplexer (252) at the selected clock rate.Formatted with ``start'' and ``stop'' pits. be done.

Synchronous data (excluding SDLC/HDLC) is shifted to a transmission multiplexer 252 at a ×1 clock rate and to a CRC (cyclic redundancy checker) generator 250.
shifted to

It should be understood that 5DLC stands for "Synchronized Dedelink Control" while HDLC is its European version.

5DLC/HDLC data is shifted out via zero insertion logic 248 which is disabled while the flag is sent. The address bit AO is inserted into the address, control, information, and frame clock fields following five adjacent °1'' in the data stream.The result of the CRC generator 250 for the 5DLC data is also: Routed through zero insertion logic 248.

SCC Receiver: Referring to FIG.
．． 234GE: 3) (7) Has an 8-bit FIFO buffer register and one 8-bit shift register. This configuration creates a 3-byte delay time that allows central processing unit 30 of FIG. 1A time to service interrupts at the beginning of blocks of high speed data.

For each reception of data in a FIFO at 232.234, an error FIF 234e is provided to store parity and framing errors and other types of status information.

In FIG. 3, incoming data is routed through one of several paths according to mode and character length. In asynchronous mode, if a character length of 7 or 8 pits is selected, the serial data enters a 3-bit delay in element 280. If a character length of 5 or 6 bits is selected, then the data goes directly into the receive registers 232-234.

In ``sync'' mode, the data path is determined by the stage of the ``receive process'' currently operating. Starting with the ``Free Selection'' phase, a bit pattern is searched for.

The incoming data is then passed through the receive synchronization register 282 and compared to the synchronization character stored in register RW6 (238) or register WR7 (236) depending on the mode being used.

The single sync mode matches the sync character programmed in register WR7 (236) and the characters collected in the receive sync register (282) to establish synchronization.

Synchronization is achieved differently in the ``bi-synchronization'' mode. The data contained in the receive shift register 232.2
34 while the next eight bits of the message are collected in the receive synchronization register 282. If these two characters match the characters programmed in WR6 (238) and register RW7 (236), synchronization is established. Incoming data can then bypass receive synchronization register 282 and go directly into 3-byte delay 280.

The 5DLC mode of operation uses the receive synchronization register 282 to monitor the incoming data stream and, when necessary, check if, for example, five consecutive "1's" are received and the sixth bit is If so, perform zero deletion (278) when deleted from the data stream. 6th pit is °1″
The seventh bit is examined only if it is equal to .

If the seventh pit is zero, a flag sequence has been received and the receiver is synchronized to that particular flag. If the 7th pid is "1°", a "break-off" or EOP (end of ball) is recognized according to the selection of either normal 5DLC mode or 5DLC loop mode.

Therefore, the same path is taken by the incoming data for both 5DLC modes.

The reformatted data enters a 3-pit delay and is transferred to the receive shift register (232, 234).

5DLC reception operation is performed by reception shift register 2.
32 The characters collected in (232) are stored in register W.
We begin in the vacancy selection phase by attempting to match the flag pattern in R7 (236).

When a flag character is recognized, subsequent data is routed through the same path regardless of character length. Although either the CRC-16 or CRC-3 DLC cyclic redundancy check formulas can be used for both single- and bi-synchronous modes: only the CRC-8 DLC formula is also used for the 5DLC operation.

The data path taken for each mode is also different. The bisync protocol is a byte-oriented operation that requires the central processing system (host 30 in FIG. 1B) to determine whether a data character is included in the CRC calculation. An 8-pit delay in all synchronous modes except 5DLC is allowed for this process. In 5DLC mode, all bytes are included in the cyclic redundancy checker calculation.

User interface processor 100 can use serial communication controller 200 in two different ways. These are = (Eng) balled; and (I
I) It is an interrupt. Both of these require register manipulation during initialization and data transfer. However, when used in interrupt mode, the 5CG200
It can be programmed to use its vector interrupt protocol for faster and more efficient data transfer.

HARK: During the polling sequence, the status of successive register 211a or 211b in FIG. 2 is checked in each channel. This register indicates whether a receive or transmit data transfer is required and whether any special conditions exist.

This method of I10 transfer eliminates interrupts.

All interrupt functions must be disabled for the device to operate correctly. No interrupts are activated,
This mode of operation begins a cycle of read register OII to detect incoming characters that jump to the data-handler routine.

c': The serial communication controller 200 is prc in FIG.
, providing interrupt capabilities similar to priority interrupt controller 800. Through the use of this method, increased throughput is achieved. The 5CC200 is ready to transfer data whenever the SCC "interrupt pin" is active.

Continuation and write register (211a) in FIG.

211t1) is programmed so that the interrupt vector points to the interrupt service routine. This interrupt vector may also be modified to indicate various status conditions.

Thus, as many as eight possible interrupt routines may be represented.

Transmit, receive, and external status interrupts are the sources of these interrupts. The source of each interrupt is prioritized in each channel, with receive, transmit, and external status interrupts being prioritized in each channel, with channel B in Figure 2 having higher priority than channel B. However, it is activated under program control.

SCC baud rate generator: each channel A and B
The baud rate generators for channel A are shown in FIG. 2 as 210a for channel A and as 210b for channel B.

Therefore, each channel includes its own programmable baud rate generator.

Each generator consists of two 8-bit time constant registers forming a 16-bit time constant, a 16-bit down counter,
and a flip-flop on the output to ensure a square wave output. This baud generator uses a 4MH clock derived from an 8MHz processor clock to drive the baud rate generator.

The loading of the time constant register is specified by
．． The counter is toggled at a baud rate of x32 or x64.

Digital phase-locked loop DP,...= Referring to FIG. 3, the series communication controller 200
It is shown as having a DPLL unit 271 that can be used to receive clock information from a data stream with I or FM encoding. NRZ
I is “inverted, non-return to zero” while F
M” is the frequency modulation.

The DPLL271 in Figure 3 has a data rate 32 times the normal data rate (
NRZ I ) * Taha 16 times (FM) t' is driven by a certain clock. The DPLL uses this clock along with the data stream to create a receive click from the data. This clock is then
It can be used as a C receive or SCC transmit lock, or both.

Input-Output Ports: To provide access to external interfaces, a pair of counter-timer parallel output ports (cIO) are provided, as shown in FIG. These counter i'v ports are
Described in the Zilog publication entitled “Z 1loo Tech Manua 1゛° and 73
15 Dell Avenue, Campbe
Ziloa Corpo, CA, 95008
This is achieved through the use of the zilog chip (Z8536) manufactured by raNon and introduced in March 1982.

This CrO or counter input-output port (202a, 202b in FIG. 1) is a general-purpose 1/O port, which consists of two independent 8-bit, double-buffered bidirectional input-output ports. and an extra 4-bit f/O port. These types of ports feature programmable polarity and programmable direction (in pit mode); they provide a 1" catcher and a programmable oven drain output.

The CIO device also includes three 16-pid counter timers, each with three output duty cycles and four external access lines. These timers are programmable as "retriggerable" or "nonretriggerable."

The ClO 400 of FIG. 4 is pattern-recognizable and generates an "interrupt" when it recognizes a particular pattern at a port.

As shown in Figure 4, there are three I/O ports provided by the counter input-output device: Port A (407) and Port 8 (408) are 8-pit general purpose ports, while , port C (409) is a 4-pit dedicated port. , two port configurations are available and designated as (1) port with pip1-port and (]II handshake. In the case of three of these ports, they can be programmed as bit ports, However, only ports A and B can operate as handshake ports.

Ports A (407) and B 408: two “
There are general-purpose '°8-pit ports, these are port [3 (408), which corresponds to callan timer 1 (401) in
and 2 (402) are identical except that they can be programmed to provide external access to. Either port can be programmed to be “handshaked” driven as a single or dual buffer 7 port (input, output or bidirectional) or as a “control port” with the direction of each bit individually programmable. can be done.

Both ports A and B (FIG. 5) include pattern recognition logic 412 that generates an interrupt when a particular pattern is detected. Pattern recognition logic 412
can be programmed to make the functionality of this port similar to a "priority interrupt controller". Port A
and B can also be linked to a 16-bit human output port with handshake capability.

Each of these ports has 12 control and status registers to control their capabilities.

The data path for each port consists of three internal registers, these are: (I>Input Data Register 41
1; (II) Output data register 410: (I[[)
and a buffer register 415.

The output data register 410 is accessed by writing to the port data register, while the input data register is accessed by reading the port data register. Two registers, a mode specification register and a "handshake" specification register, are used to define the mode of the port and specify what type of handshake, if any, should be used.

At ports A and B, the reference pattern for the “Pattern Recognition Logic” is specified as 3
identified by the contents of two registers (not shown):
(ENG) Pattern polarity register; (IF) Bakun switching register; and ([[) Pattern mask register. The detailed characteristics of each bit path (eg, whether the direction of data flow or path is inverted or non-inverted) is programmed using the data path polarity register, data direction register, and special I10 control register.

Referring to FIG. 5, the counter timer output CI
A detailed block diagram of each of o ports Δ and B is shown. In FIG. 5, output data register 410 and input data register 411 are shown connected to internal data bus 212. Output data register 410
is connected to a data multiplexer 420, which is connected to pattern recognition logic 41.
2 or to an input data register 411 or to a buffer register 415 having an output that can be passed to an output buffer inverter 418. Output buffer inverter 418 can provide an output to input buffer inverter 422, which input buffer inverter 4
22 to data multiplexer 420 or port B
Their outputs can be given to counter timers 1 and 2 (408 in FIG. 4). Port control logic 413 in FIG. 5 communicates with internal data bus 212 J!
It is possible to provide internal port control or handshake control during 11 minutes.

For each port, the master control and status bits are
are collected into a single register called the "°Command and Status Register". Once a port is programmed, this is the only register that is accessed for the most part. first time! To facilitate fl configuration, port control logic 413 is designed so that registers associated with capabilities that are not needed or requested are ignored and not programmed.

The block diagram of FIG. 5 illustrates the port configuration that may be used and applies to ports A and B (407 and 408 in FIG. 4).

6' Port C (409): In FIG. 6, includes a dedicated "4-bit register" present in port C (409 in FIG. 4). The functionality of this register is dependent on the functionality of ports A (407) and B (408). Port C (409) provides a handshake line when requested by the other two ports. .

The “Request/Wait°” line is also provided by port C (409), which in turn brings port A (407) L
Transfers by B and B (408) are performed by the direct memory access unit or central processing unit CPU3 of FIG. 1B.
0 can be synchronized. Any bits of port C (409) that are not used as handshake lines may be used as input/output lines or as external access lines to counter timer 3 (403 in FIG. 4).

Since the functionality of port C is primarily defined by ports Δ and B (in addition to the internal input data and output data registers accessed as in ports A and B), here we use the three bits − Only path registers are required: a data path polarity register, a data direction register, and a special control register (not shown).

Karan 9f 94f person car output crab unit: In Figure 4, three counters/timers 401 in Cr0400
, 402, 403 are all units of the same type. Each of them has a 16-pit down counter, a 16-bit time constant register (which holds the value a-coded into the down counter), a 16-bit current count register used to read the contents of the down counter, and! It consists of two 8-bit registers for IIIIll and status (ie, mode designation, and counter/timer command and status registers).

Four port pins (counter input, gate 1)
Three different counter/timer output duty cycles are available (manual input, trigger input, and counter/timer output) can be used as dedicated external access lines for each counter/timer (Figure 4). be. These are: (I) pulse duty cycle; (■) one-shot duty cycle; and (I
[[) is the square wave duty cycle. The operation of this counter/timer can be programmed as either retriggerable or non-retriggerable.

As shown in FIG. 7, each counter/timer is connected to an internal data bus 212 and has two time constant registers 710 and 711, which have outputs to current count registers 720 and 721. A 16-bit down counter 715 is connected thereto. Additionally, counter/timer control +0 thick unit 712 has an input line from a port and is connected to internal path 212 .

('[0 (capacitor/timer input output crab unit) -・
7η゛IIflI logic: The microprocessor 110 in FIG.
(FIG. 4) Interrupt signals can be received from interrupt control logic 222. The interrupt control logic of the C,IO 400 provides five registers (not shown): (I) Main Interrupt Control Register; (II) Current Vector Register; (III)
(IV) and (V) 3 associated with interrupt logic
two interrupt vector registers.

Roughly speaking, each port and counter/timer command and status register contains three bits associated with the interrupt logic...these are
Interrupt’” and °“Interrupt Activation” under Z11 Service
It is. Karan 9f 94f person car out crabnit for every one
One interrupt has priority interrupt controller (800- in Figure 1)
The interrupt controller is programmed to recognize the Cl0400 as a slave interrupt controller. Similar to the operation of the 5CC200, this implementation allows the interrupt vectoring capabilities of the Cl0400 to be fully utilized.

Programmable Interval Timer (PIT) As can be seen in Figure 1, the user interface processor includes a P[T700 or programmable interval timer. Each device is an 8MHz programmable interval timer consisting of an I10 accessible set of three 16-pid counters/timers.
It operates functionally similar to the three counters in 00. P[The two outputs of the 7700 timer are both 'OR'
1 and drives the interrupt level to the priority interrupt controller PRI TC800 of FIG.

The individual outputs of these two timers are also C[
0400, which allows microprocessor 110 of FIG. 1 to determine (via read from the cIO port) which timer caused the interrupt. Other timers also have priority interrupt control PRrTC programmable via different interrupt levels.
Drive the 800 directly.

PTT700 (Programmable Interval Timer in Figure 1)
has six different modes of operation, which are described as follows: Output on terminal count; Hardware retriggerable one-shot: Velocity generator; Square wave generator: Software triggerable Strobe; Hardware Triggered strobe.

Program b-capable interrupt controller 800: 1st
In the figure and FIG. 8, it can be seen that the PRITC 800 has been designated as a programmable priority interrupt controller. The interrupt controller device 800 is incorporated to coordinate multiple interrupts provided on the user interface processor.

The programmable priority interrupt controller has eight Ti
1 and generates a priority for each interrupt along with an individual vector for each interrupt.

Various components of user interface processor 100 can provide interrupt signals to microprocessor 110. These various quibs of interrupts are: (a) 5CC1 interrupt: (11) 5CC2 interrupt; (c) ClO1 interrupt: (d) ClO2 interrupt; (e) Interval timer υ1 included. (8254) (both OR
(f) Interval Timer Interrupt (8254): (Ω) Forebrain Receive Interrupt: (h) DLI Controller Interrupt.

These interrupts will be given priorities and the interrupt controller device 800 will output a vector pointing to a service routine in the microprocessor 110 in response to its corresponding interrupt input. Priorities are under programmed control and can be used to assign a level of priority to each input. Programmable priority interrupt controller PRITC 800 is shown in block diagram form in FIG.

The block diagram of FIG. 8 shows the basic elements of PRITC 800, namely the priority interrupt controller of user interface processor 100. Here, data bus buffer 810 is connected to internal bus 212 , which has a bidirectional connection to interrupt mask register 822 . Mask register 822 communicates with in-service register 824, priority decomposer 826, and interrupt request register 828 to provide output to internal bus 212 and control logic 820. il+II tllll O chic 820
provides output to read/mload logic 812 and to cascade buffer comparator 814.

The input unit Cl0400 and the serial communication controller 5CC200 require a separate ``interrupt acknowledgment'' term for each of the units.The microprocessor 110 (8086) Since driving the acknowledgement (INTA), means were provided for implementing a method of decoding a separate "interrupt response" signal.

PRITC800 interrupt:] N'r-o-5c, ClO
400 and 5CC200 interrupts are programmed to examine interrupts as if they were from other interrupt controller devices (referred to as ``cascade mode''). This is a 3-bit field (CASO in Figure 8) in the PRfTC800 interrupt controller.
-CAS2), this field is unique for each interrupt level programmed as a slave interrupt.

These three outputs are decoded and sent to the separate “
1.11-inclusive acknowledgment" is used.

This fully utilizes the interrupt vectoring capabilities of the SCC and CIO chips.

The three cascade outputs mentioned above (CASO, CASl, CAS output from the cascade buffer 814 in FIG.
2) can also be driven into the foreplane (FP) to use another external interrupt f/J m chip, thus increasing the amount of interrupts to 15 types of interrupts.

As seen in Figure C, the user interface processor 100 has a foreplane connector (FP2).
A buffer microprocessor interface connected to the microprocessor interface is provided. This interface is
oo is connected to the application dependency logic through this interface. All necessary memory control signals are provided so that the logic providing expanded memory can be executed. , LJ I
P1oO's external input-output devices are also connected.

These may be in/out units or units memory mapped to the UrP100.

Each interrupt is received by the UIP's programmable priority interrupt controller PRI TC800. Further interrupts are handled by the UIP interrupt controller cascade output (
814 CASo in FIG.

1.2) can be brought about by adding another controller. This can result in an expansion of up to eight interrupt signals. For devices with very slow access times, "input enabled" (derived from microprocessor 110) is
), which allows these slower components to meet the timing constraints of the microprocessor.

The microprocessor 110 receives an output signal @HL present on the CTL path of the foreplane (FP2 in FIG. 1).
However, the input signal @H
○1-0 does not exist. This is foreplane F
This means that application dependent logic connected to P2 cannot perform direct memory accesses to the UIP RAM array 150, for example. Additionally, the buffers that drive some signals on the foreplane are always enabled and they are
It cannot be disabled by the P microprocessor 110 or by application dependent logic mounted on the foreplane (FP2 in FIG. 1).

There is a group of signals brought to foreplane connector FP2 of the user interface processor board. In these signals, direction is indicated by days for bidirectional, ■ for two-person power: and zero for output.

The list of signals on the forebrain connector is as follows: one microprocessor address bus (200 bits) one microprocessor data bus (16 bits) one interrupt controller power scale path (3 bits) one microprocessor data bus (16 bits) Prosena control signal B HE/-Bite high activation O
RD/-Read Strope OW
R/' - writing stroke OM/
10 -Memory/10 00 pieces/R-
Data transmission/reception 0△LE - Address latch activation 0DEN/ - Data activation 01-I L D8 - Hold acknowledgment 0INT - Interrupt (input of ■ to interrupt controller) INTΔ/ - Interrupt acknowledgment 0RDY
- Ready (standby function activated) r In FIG. 9, a 10-step diagram of the DLI/HDP controller is shown. While the term “DLI” stands for “Data Link Interface”, it also refers to “HD
The term ``P'' stands for ``superordinate subordinate port ''.

Data Link Interface (DLI/1-IP) Controller: The DLI/1-IDP controller 180 of FIG. 1 is illustrated in more detail by the block structure shown in FIG.

The DLI controller provides an ``interface'' that includes ``clear'' and ``self-test'' initiation logic, DL transmit/receive register 922, burst counter 916, and burst termination logic. 926 and a horizontal parity word (LP
W) generator 923, vertical parity generation and routing, request and 5Il! Urgent request logic and DL
I/microprocessor communication logic.

A 24-bit state machine with parity (925 and 9oO) receives conditions from and controls these data elements. Microprocessor 110 also.

It receives status from each part of these elements and controls each part of these elements.

FIG. 9 also shows a block diagram of the Dll/HDP interface. The data bus 909 is a control bus [-
A 910, l-I D P register 911, D L
P status transmit/receive register 912, D L,
P request/address logic 913 and data latch 9
14, host pointer 915, and burst counter 9
16 are connected. Control store 910 has outputs that provide signals to condition selector 917 and to parity check circuit 918.

Data latch 914 is connected to DLI transmit/receive register 92
It has a data bus connection to 2. host pointer 9
15 gives an address to a RAM 920 connected to a vertical parity generator checker 923.

Microprocessor address bus 110a is connected to address buffer F919 and device decoder 921.

Clear/-Start self-test: ``Clear'' and ``Self-test'' configuration logic (1121 in Figure 1)
) detects when various types of clear and self-test signals are required.

The clear signals detected by the Clear/Self Test PAL112i in Figure 1 (Programmable Array Logic) are as follows: LCLCLR...Local Clear MSTRCLR...Main Clear 5ELCLR...Select Clear PLIPCLR...Power Up clear PSSCLG
. . . Path Selection Module Occurs Clear These signals are received and latched by the clear self-test PΔL 1121, which further indicates to the microprocessor 110 that a non-maskable interrupt has occurred due to the self-test PAL (112+ >) and thus a clear condition has occurred. Let me know.

The microprocessor 110 processes this PLΔ(11
21) and determine which conditions have occurred and what actions should be taken as a result.

Clear Self Test PAL (112i) also performs one function that controls the microprocessor 110 reset signal. u+pioo is reset and cleared under the following conditions: (I) PUPCLR...Power up clear; (
U) Forebrain Buddle Card - Attached Button Clear; (Il1) Selective Clear Jumper Selectable A Button (SELCLR): (IV) All other clear signals are sent to the 8086 microprocessor (1st A non-maskable interrupt (110) in the figure is generated.

A dynamic RAM parity error signal is incorporated into the clear self-test PΔL (112a). It also generates a non-maskable interrupt and can be read by microprocessor 110 to determine whether a clear signal or a parity error caused the NM■ interrupt.

DLI transmit/receive register: In FIG.
The I transmit/receive registers 912 and 922 have two
Implemented in a G.917A bidirectional register/latch.

This 2917A is 901 Th.

mpson Place, P, O, Box 4
53.3 Advanced Micro Devices, Inc., with an address at Unnyvale, Ca. 94086.
1cro [) evices, r nc.

) is a register/latch manufactured by 291
The 7A unit is based on the ``Polar Microprocessor Logic and Interface Data Book'' published in 1981 by Advanced Micro Devices, Inc.
lvl 1croprocessor L-oqi
cand Interface [) ata
3ook) ”.The “output enablement” on the DLI status bus (Figure 9) is
A signal called CON N [CT” and a signal called “
Generated by '[03ND'''.

This control signal (under cONNEC and l08ND) is
Occurs in request logic 913.

The combination of C0NNECT and “DLP request” generates an “output enable signal” to DLr buffer 1922, thus causing the connected data link processor D
Drive data from the LP onto the DLI data bus (Figures 1C and 9). The microprocessor 110 can also set "DLP Request °" to "false" and send it as "true °".

“Latch activation” which receives data from DLI and provides it to receive register 922 is controlled by signal AF (sync 5TIOL). Clocking of data to the DLI transmit registers is performed by the Dll state machines (925 and 9).
10). Use of the term "PAL" refers to programmable array logic.

DL Burst Force Outer 916: The burst counter 916 of FIG. 9 is implemented as a PAL programmed as an 8-pit-up-counter. it is read and loaded by microprocessor 110;
Count - Activation is the Dll state machine (910,9
25>. An overflow term designated as BUFFUL is also generated by burst counter 916, which generates a "burst output" when the counter overflows.

The burst termination logic 926 includes a signal TERM (termination).
, signal BLJFFuL (burst counter execution),
and signal @5TIOL<strobe I10 level). These signals are D! State machine (92
5,910) by giving conditional input to burst flip-
Used to reset flop 926 and stop burst mode.

Horizontal parity generation/check: Parity check circuit 9
18 provides a horizontal parity generator implemented with two PALs (923), and these two PALs
L is programmed to perform horizontal parity word (LPW) I calculations. The data pipeline latch means is connected to an internal DLI data bus 909 (“D” in FIG.
It consists of two latches 914 and 923 used to meet the timing requirements on the A T A ”).

The microprocessor 110 of FIG. 1 controls the clearing and output of the NEQZER from the LPW generator (923).
Check O status. DLI state machine (91
0,925) controls the integration and readout of the horizontal parity word LPW generator 923. "Enable Vibration Latch" (923) is also controlled by the DLI state machine (910, 925>).

Vertical Parity Generation Check: Vertical parity generation and routing is performed by two 9-pit valid generators with quad 2x1 tri-state multiplexers 922. Bidirectional register/latch (2917
A> is used to transmit and receive parity bits on the DL data bus (FIG. 1).

Vertical parity occurs when accessing dual port RAM 920 from microprocessor system 110 and is written to parity RAM 920. Vertical parity is from the Dll interface 922 to the dual port R
When writing to AM 920, the checked and actual DLI parity is written to parity RAM 920.

Vertical parity is read from the parity RAM when read into the DLI transmit/receive register 922. flip-
The 70 tube is used to store the results of the parity check and provides the vertical parity error status signal (V
PERR) to the microprocessor 110.

VPERR is a status input read by microprocessor 110.

Request Logic for DLP: Request and emergency request logic is processed in request PAL 913. Microprocessor 110 controls the transmission and removal of DLP request signals. This request is made by monitoring the emergency request input from the DLr (Figure 1C) to the DLI backbrain (Figure 1C).
Figure C) causes LJIP requests to be removed when there are urgent requests from other data link processors.

The signal rO8ND (input-output transmission) also indicates the request PA
Generated by L913. The signal rO8ND is U I
P 100 requests service signal C0NNEC
Automatically set when T is "true". This situation occurs when U I Pl 00 returns the descriptor link to the host computer 30 of FIG. 1B. This signal l03ND is also It can be set by microprocessor 110.

The quotations in Figure 1Δ, Figure 1B, Figure 1C, and Figure 1D refer to the user interface processor (UIPloo) for the system initial role.
System network connection and processor interface
Ace card 40. Operator display terminal 10
0t, electric m full ill card 50, power supply module 50p, modem 50m and remote support center 50r, and other units in the system network, all of these units are shown in Fig. 1Δ. has been done.

In FIG. 1B, user interface processor 1 for upper subordinate port HDP 500 and I/○ subsystem 500s and extended r/○ base 500e.
00 relationship is shown, and the main processor 30. memory bus 3
0+e and connections to memory control unit 32 and memory storage card 34 are further shown.

FIG. 1C further shows processor interface card 40, main host processor 30. Memory control unit 3
2 and upper subordinate ports 500 are shown.

FIG. 1D shows the interface relationship of the user interface processor 100 with respect to the processor interface card 40 and the main host processor 30, and also shows a group of data link processors 100d, a maintenance card 100m, a local terminal 100t and a power control card 50 and a remote support link 50
+r is shown.

The user interface processor 100 is responsible for the operation of the system network and, in particular, for the
1 setting'' plays an important role.

The computer network system shown in FIGS. 1A, 1B, 1C, and 1D will "power-on" and initialize in approximately three minutes. No operator intervention is required during the "power-on" sequence when the hardware and software are properly installed in the system. The operational features of this sequence and how to handle exceptional conditions that may occur are discussed below.

Power-on: There is a power button located on the top left hand corner of the computer cabinet, and by pressing this button, you can either 'power-on' or 'power-off' according to the current state of the system.

will start any of the sequences.

The "Power-On" button will connect power to the main processor 30 of the system built into the cabinet and to the disk-system unit. The presence of at least one operational installed disk is required for the power-on sequence to be successfully completed.

After power is successfully established, the UIP maintenance subsystem will control the system network to handle the next stage of the "power up" sequence.

Computer maintenance subsystem self LLL:
The computer maintenance subsystem will first perform a "self-test" to ensure that its own processing elements and memory are operational. Thus, in FIG. 1A, the self-test procedure is as follows: A self-test will occur to check the microprocessor 110, timer 700, memory EPROM 170 and DRAM1 50, and DLI/HDP controller 180. This self-test only requires a few seconds and if the If the test routine passes successfully through all units involved, then the operator's display terminal console 10
Pag greeting ((Irf3) at 0t (Figure 1A)
etinO)” will be displayed.

Starting system initialization: In the computer network described, this initialization would require approximately 3 minutes of time. If a "readout" does not appear on the console display 10o within a few seconds,
It is then indicated that the maintenance subsystem is inoperable and appears to be experiencing the following problems: (a) External power is not being supplied to the console cabinet. It is necessary to restore power and press the "Power-on" button again.

(6) The "self-test" procedure is malfunctioning.

It is necessary to press the 'power-off/'fft power-on' button again at another time. Here, ○DT screen 1
A repeated failure to display a greeting above 00 indicates a problem with the system hardware or firmware.

(c) There are some problems with the connection from the maintenance subsystem to the operator's console 100t.
Verify that the terminal 100 is properly powered and regulated and remove the terminal 100 from the computer cabinet.
[It is necessary to check that the plug of the cable to the terminal is securely inserted into the terminal. Once this check has been made, it is necessary to press the "Power-Off/Power-On" button again.

Loading maintenance subsystem software: Maintenance subsystem is B○OT C0D
It is necessary to load its own software from the file designated as
The data link interface 7 at 5d in Figure B is located on an embedded disk connected to the user interface processor 100 by the eighth line.

If there is no OOT CODE file available, then one must be created for use. Typically, this file is available and requested software loaded within a few seconds, and the clever belter recognizes that the BOOr C0DE file is found by observing a message that briefly appears on the console display. There are many things to do. These messages will appear as follows: BOOT-DLP xx BOOT-UNIT xxx Sector Address xxxxxx [300T-DLP, BOOT-Unit t3 When the number appears for the sector address Therefore, the unit containing the BOOT CODE file is selected.

In addition, the status line at the bottom of the screen (
Yu, “°Loading maintenance software”
will show.

Failure to load BOOT CODE: Any failure to load the maintenance software will be displayed on the operator's display screen. A status line at the bottom of the screen will indicate the cause of the failure and require the operator to take some action.

Therefore, the possible causes of the displayed failure are: (a) BOOT unit not found; (b) BOOT C0 on input crab unit XXX
DE fu? file was not found.

(c) Irukaninit XXX was not ready.

As a result, the operator will be prompted to specify a valid unit number. The operator must then ensure that the appropriate unit is powered up and ready to proceed, and the raid operator can type in the unit number to be used. The Maintenance I10 configuration will be displayed on the console to indicate to the operator the set of units found on the last attempt to locate or access the BOOT CODE file.

If the correct unit does not appear in the table, then there appears to be a problem with the I10 subsystem 500S of FIG. 1B.

If the unit is present on the table, but the BOOT
C0DE fu? If the file is not found on a particular unit, then it appears that the BOOT CODE file will never be created on that particular unit.

The possibility is that the disc in question is corrupted or deteriorated, and the operator should identify the damage, the backup unit if one such disc exists, and If not, the BOOT given to the computer network system described.
The software should be loaded from the C0DE tape.

If a ``backup'' BOOT unit exists, it is identified as the next unit to try. However, if no BOOT unit is found, then the list has already been searched. Therefore, it is not beneficial to try one of the units already shown in the 10 configuration table. Check that the expected B00T unit is operational, and if not, make the BOOT unit operational. If it is necessary to take action to bring the situation up to speed, the infringing operator should re-enter the operation by specifying the unit number.

It is also possible that a BOOT CODE unit is configured, but a parity error is encountered during software loading II.

When such a situation occurs, the operator will be asked to identify other BOOT units. Therefore, backup units should be identified if they exist and are available.

If software loading consistently fails due to errors in maintenance subsystem memory, the system may be serviced to replace the failed element before the "power-on" sequence is successfully completed. There must be.

This procedure for tape loading is only necessary in case of catastrophic loss of the BOOT unit (eg, head failure) or if the computer system never initializes its BOOT unit.

If the BOOT code file is not available, the maintenance subsystem must perform a ``tape load''.
This is done by identifying this unit as the BOOT unit after each C0DE tape is installed (the screen above the operator's console 100 should then wait until the operator identifies it).

The maintenance subsystem will then operate from the tape unit rather than the disk unit.

The tape unit must remain installed throughout the First II setup sequence in order for subsequent files to be read. When the MCP (Main Control Program Operating System) is finally activated, the operator:
The BOOT C0DE file must be created on the installed disk and the "Power-off/Power-On" switch of the system must be initiated again. Next and all subsequent "Power-on" finds and uses the BOOT CODE file on the disk, so the 8007 CODE tape is then removed.

Loading System Microcode: The next step is performed automatically in the power-on sequence. This step is to load the computer system microcode (from the BOOT CODE file or from tape depending on whether the system is tape loaded).

A "status line" at the bottom of the operator's screen will indicate this condition. This loading will take approximately 30 seconds.

If loading fails, the reason will then be indicated on the console of display unit 100t. If this failure is Ilo on the BoOT unit
If the problem is due to
If possible, the system should be restarted by identifying a backup 800T unit.

If loading fails due to an error in processor 30's 1lIIItII store (the memory in which the system's microcode is stored), then the failed element must be serviced.

System reliability testing: After the system microcode is loaded, reliability testing will be performed on the computer network.

This test takes approximately 30 seconds each and requires approximately 30 seconds of processing time.
indicates that the control store in the system is properly loaded and that the processing elements of the system are operational. This system BOOTs the main control program
It is possible.

Initial fullH determination of the operating system: At this point, the maintenance subsystem has one more task left to perform in the power-up sequence. Here, this task is “SYSTEM/UT
The program specified as "I LOADER" must be loaded into the computer system. This program is loaded from the BOOTCODE file and
Moreover, this takes approximately 30 seconds.

Any failure to load the SYSTEM/UI TLOADER program will result in an
It is due to lo issue or some system issue. In the event of a failure, the cause of the problem will be displayed on the operator's console 100°C. after that,
The operator must take appropriate action by either restarting the "power-on" sequence on the backup BOOT unit or servicing the failed element.

Maintenance PrinciplesThe requirements for initial setup and maintenance in computer system networks are similar;
This similarity is exploited to significantly reduce the cost by sharing the access interface hardware. first time! The sharing of hardware for fl 1 configuration and maintenance allows faults to be reported locally or remotely and to initialization with only a small functional pit in the circuit.

Another advantage of this shared hardware is the high degree of visibility into all of the subsystems across the system network. This direct visibility provides superior analysis for faults and fault resolution.

Access and enablement of initial configuration and maintenance functions for the computer network system is provided through the use of user interface processor 100.

The particular computer network system disclosed herein is comprised of the following items: a main central processor including data cards and control cards; a memory control unit (MCLJ); an upper slave port ()-IDP); a data link processor. (DLP).

``Maintenance subsystem'', which is basically the maintenance and initialization subsystem of this disclosed computer network, is composed of the following items: User interface processor 100: Processor interface card (PIC): Power control card (
FCC).

Diagnostic Requests: Several parameters and requests are included for a diagnostic routine to occur in the computer system network described above. These are = (a) all diagnostic tests must be run both locally and remotely (and they must appear in the same format and accept the same commands); (b) how are diagnostic tests performed? System failures must also be isolated at the "card" or "card"level; Must have one finger available for test engineering.

Initial Configuration Requirements: The following elements are required for initial configuration of the disclosed computer network: (a ”) Initial configuration of the system can be performed from either a local location and/or a remote location. (6) Initialization of the system may be possible without operator intervention of any kind, i.e., without an operator at a local location; (c) Structural configuration during the initialization period; Failures (interconnect and line failures)
can be detected before a detection against machine integrity is made.

Test Operations: The diagnostic program included in this system has two primary functions, the first being to serve as a reliability test on any well-specified subsystem; The function of is to analyze any failures detected by the reliability routines to specific card unit locations.

Introducing: All subsystems with a microprocessor must be able to perform self-tests.

For those units that do not have a microprocessor, diagnostic access hardware is provided on each printed circuit board for self-testing. The self test is
This is accomplished by connecting to a user interface processor 100 that provides information and drives tests via a processor interface card 40.

System Tests: These tests are issued as diagnostic tests that provide a means to dynamically test at the system level. This dynamic test incorporates the event analyzer of the Brossena interface card 40 and the hisd file of the processor interface card 40.

Type of failure: The type of failure to be detected in this system is
They are classified by the level of testing required to detect the fault, the level of skill required to correct the fault, and the time at which the fault is detected. Four types of failures are considered for detection in computer system networks.

Failure Type ■: These types of failures are failures such as failure to power up; no response on the console unit (operator's display terminal); or failure to resolve operational problems that occur.

There is no readily available diagnostic program or one or more faults are present. There is a high possibility that a fault exists in the core logic circuit.

This type of failure cannot be confirmed from a remote service tip.

Fault Type ■: These types of faults are detected during system initialization when a logic card and console message identifying the fault is displayed. Type ■ faults are also detected when running the diagnostic program, where the same console messages are displayed.

This type of fault is characterized by structural faults...stuck at 1, stuck or short circuit at O. Correcting this type of problem simply requires replacing the required card on the maintenance display console.

Failure Type ■: Failures of type ■ are multiple equipment failures reported in the maintenance log; failure of the main control program (MCP) to initialize; continuous dumps not cleared by stop-load; and/or or internal diagnosis (E
- mode diagnostics) detected by error messages displayed by running the program.

This type of failure is characterized by a failure of two peripheral devices or a failure of a memory unit; it is a failure that can be confirmed from a remote service center.

Elements for correction in this type of problem include peripheral adjustment and/or logic card replacement.

Fault Type V: Examples of this type of fault are system dumps caused by machine checks; or event traps that capture data regarding specific events.

This type of failure is characterized by: data-dependent failures, intermittent hardware failures or software failures. However, these failures must be such that they can be confirmed from a remote support center. This type of problem requires a high degree of skill to correct. This problem can only be identified in the running system context or by analyzing the dump.

Test Levels: The included diagnostic tests are divided into four levels:
each of which is intended to handle a specific fault type. In general, the execution of a test case depends on the good execution of preceding test cases, unless the tests are used to address or cover completely independent logic. Each test case is configured to eliminate the use of hardware that has not been previously tested.

Basic Board Test and Self-Test Level 1: This type of test is used to obtain a minimum level of structural and functional reliability in the included hardware. Its purpose is to verify the initial configuration path during system power-up to serve as a reliability test during debugging and as a manufacturing test thereafter. These tests use diagnostic code running on either the UIP (Basic Board Test) or the onboard microprocessor state machine (Self Test).

Level 1 tests cover tests that include the main central processor 30, the main control unit 32, the upper slave ports 500, and the processor interface card 40, thereby testing each of these four units. is given a basic board test driven by user interface processor 100.

Level 1 testing also covers certain other units that are defined as "self-tests" driven by on-board microprocessor units. These units, which are provided with self-tests via the microprocessor, are provided with a user interface processor 1.
00. ? lf source control card 50, storage module disk-to-data link processor, printer tape-to-data link processor, and data communications data link processor.

Micro-coded Diagnostics - Level 2: These tests are used to obtain a higher level of reliability in the main frame hardware by testing the interaction between sub-modules in a controlled situation and in memory sub-modules. Used as a unit use. These tests are written in HNE microcode and run on the central processor 30 at normal clock speeds (4 MHz), with a driver running on the user interface processor 100 controlling the execution of the test cases and Monitor the results.

These Level 2 tests cover the following items: (a) Central processor 30: (6) Memory control unit 32 and memory storage board 34; (0) Superior slave board T-500 (Figure 1B) :(d
) A maintenance subsystem including a user interface processor 100, a processor interface card 4o; and a power control card 50.

E-Mode Orphan Diagnostics - Level 3: E-Mode Orphan Diagnostics is a NEWP (New Programming Language) compiled E-mode program that runs on top of normal system microcode. This °°E-mode" includes a bus stack structure and is described as 80M (Computer Association (Associate
ion for Computina Machi
Published by Q. Wagner
Δn E-Machine Workbench by J. R. and J. W. Maine.
Bench)”.

They are used to obtain a higher level of reliability in main frame hardware by configuring for the following tests: (a> Controlled E-
(6) Interactions between microcode and hardware; (c) System and [10] interfaces not covered in lower level testing.

These level 3 tests are divided into two groups: the processor group and the I10 group.

Processor group tests are designed to test E-mode operation in situations where the complexity of the main control program is not included. Standard test cases are provided that perform operations singly, in pairs, and in triplicates. A patch has been brought to this particular program to generate test cases using the NEWB compiler, and to aid in diagnosis, to allow engineers to extract the erroneous code from the main control processor situation. There are options to use a wide range of depack features, as well as the computer network features of ``events and history logic'' to perform in a diagnostic situation.

The I10 group, from E-mode, processor 30 and upper slave ports 500 microcode-hardware, message level interface/data link interface (MLI, zDL+),
and diagnostic equipment configured to test the complete path through the data link processor to the peripheral device itself. This is relatively l! This situation can take advantage of the event and history logic and extensive debugging features of these programs.

Reciprocal Effects Test - Level 4 Level 4 testing is used to find faults that occur only in passive system situations.

After verifying that computer mainframe 30 is properly functioning, the master control program performs interaction tests (PTD and SYSTEM) to further diagnose problems in the master control program situation.
S ) can be driven.

Additionally, event and history logic can also be used to capture failures that occur only during system execution or application software execution.

Diagnostic Analysis and Error Handling: When an error occurs, the diagnostic system will provide an "error message" indicating which board is malfunctioning.

At the basic board or interaction level, the hardware is tested in separately configured blocks, with testing of one block dependent on successful completion of testing of the preceding block.

Thus, a diagnostic test terminates upon the occurrence of an error in the module under test, but a diagnostic test
Continue running tests on the other module if the test is not dependent on the previous test to further diagnose faults in areas such as the M-bus or control bus that can potentially affect more than one module. Will.

In the event of a recoverable error, for example the incorrect comparison of data in Pattern Sensitivity Test 1~, the diagnostic test should record all information related to the error when the error occurs and continue until completion. Probably.

Diagnostic rating: Diagnostics are ranked by running them against a list of faults that can be generated by DDRIVE (a program for generating test cases). The number of faults detected by diagnostic tests can be used to determine the rate of testing required.

Maintenance Interfaces: Six maintenance interfaces will be discussed below: (a) TEST RUNNER-M (', /
-r interfaced to nonce software; (
11) Computer system mainframe diagnostic interface; (c) Computer system I/(81 disconnection ink-
(d) Maintenance terminal and operator display terminal functions: (e) Data link interface (DLI) interface; (d > User interface body length diagnostic capability.

TEST RUNN to maintenance software
To bring a unified approach to the ER interface, an interface to diagnostics, we
An executable program called ``ER'' will control all execution of the offline diagnostics, interface and error logging.
R is a simple menu driven program designed to complete the overall maintenance principles of problem solving for units that give explicit details of failures at board level and may be replaced. There is.

There are two modes of operation for TEST RUNNER. Initially, the ``auto mode'' is included during the initialization sequence of the system and performs a sub-hit of diagnostics.

Any critical failure detected during this mode will take the system out of automatic and into manual first W1 configuration mode.
Diagnosis is then performed to confirm or isolate the problem. What non-critical faults are detected (
For example, modules not required for initial configuration or memory modules other than the data link processor)
will be flagged to the operator, but will cause the initial 11+1 setting to continue.

Second, MANUAL or INTERACTIVE
MODE exists. This mode may be entered during system initialization or will be entered as a result of a critical failure during automatic mode. This mode allows you to specify which diagnostics are to be run and to capture and/or examine the state of the system.
It uses history logic.

Diagnostic tests for main processor 3o, memory control unit 32 and upper slave port 500 are initiated from user interface processor 100. Here, the user interface processor functions to: (a) initiate the computer system network; (6) provide on-site and remote service access to the computer system network. This includes an interface to the main control processor 3o, operation of the shift chain to the computer network system and control of the system cock and event analysis for stopping the computer system network; (c) the computer (d) respond to real-time interrupts such as control store parity and super-stop interrupts from the system; (d) supply software (soft front panels) from the computer system network;

The user interface processor hardware and its functionality is discussed in connection with FIGS. 1-9 of Akitiam.

Computer System Human Power/Output Diagnostic Interface: User Interface Processor 100 is a processor with limited input/output capabilities. U I
Pl 00 can communicate with peripheral devices configured in the system via a data link interface. User interface processor 100 via power control card 40 provides a link to a remote support center, shown as 50r in FIG. 1A.

This allows remote diagnostic capabilities.

The user interface processor 100 also provides a maintenance and operational display terminal 10.
Provides a link to the local terminal for 0t functionality. Furthermore, the user interface processor 10
0 provides test bus functionality via the Burrows Direct Interface (801 shown in Figures 1B and 1D).

UIPloo has the ability to communicate with peripheral devices to provide system maintenance, load operator microcode into RAM, perform diagnostics, enable remote maintenance, and provide stop-loading. . The software programs that do this reside on peripheral devices, and the data link processors of these peripheral devices are connected over a data link interface (i.e., a system maintenance program used by user interface processor 100). .

Maintenance terminal and operator dism section: UPI, TDr link (@terminal direct interface)
It communicates with the terminal via. These terminals provide separate windows into the Compute System network. The system is in “maintenance mode” and the terminal is a maintenance display terminal (VDT)
A window occurs when . In this mode, the user may access state, perform system diagnostics, and perform other low-level functions.

Other windows occur when the system is under Master Control Program (MCP) control. This terminal then
DT or operator display terminal. u+
pioo provides operator display terminal-data link processor functionality for the system.

What kind of operator display terminal is there?
may be configured in one computer system network.

Data Link Interface: UIPloo can communicate with the data link processor via the data link interface shown in FIGS. 1B, 1C, and 1D. For the data link processor, the Urp1oo command
Such as the commands sent by the superior subordinate port 500 of Figures C and 1B, the user interface processor 100 has the ability to control devices connected on the data link interface. .

There are eight available addresses (0-7) for the data link processor on the data link interface. UIPlooLlt occupies the first address (0) a on the data link interface. A printer tape-data link processor is logically thought of as a one-card data link processor and two data link processors that communicate with two types of peripherals, so it occupies one slot. Occupied.

The SMD-DLP (Storage Joule Disk Data Link Processor) occupies the fourth address on the data link interface.

This leaves four addresses available for expansion.

User interface processor 100 may communicate with peripheral devices by sending I10 descriptors to and receiving I10 result descriptors from the data link processor.

UIPl to determine the configuration of the system.

○ sends a test I10 operation to the peripheral device on the data link interface. From this information,
A data link interface configuration table may be configured.

The computer system network disclosed herein may have several UIO (Universal Input Output) bases. One base contains all of the data link processors and peripherals on the data link interface. A separate base may also be configured on the Message Level Interface (MLI) port on the )-IDP 500, as shown in FIGS. 1B and 1C.

UIPloo cannot communicate directly with peripherals on message level interfaces. Therefore, the software programs and files used by LIrPloo to perform diagnostic and maintenance functions must reside on the peripheral whose data link processor is on the data link interface.

Computer system network power supply explained −
An up is a sequence of events that generally does not require operator intervention, except in some specific cases. If the failure path is not functional (eg, the system disk is not operational), then other means of shutting down the system are provided. (Some options are: (a) Required to perform a cold start or cool start that requires loading an E-mode program (called a loader). (b) operator intervention on the Message Link interface;
Operator intervention is required to determine the configuration of the 10 system. ...This is also jltil.

requires the loading of an E-mode program called ader; (c) Uses a stop-load unit instead of an abbreviated stop-load unit. intervention is required.

It should be noted that both the Unloader and [ ]-da must be present on the peripheral connected to the data link interface.

User Interface Processor, :UTPL
oo provides some diagnostic capabilities for the I10 subsystem. UIPloo can determine the configuration on the data link interface and perform basic interface testing. Furthermore, urpi
oo is note 1! ! A self-test can be initiated on the module disk and printer tape data link browser.

Finally, UIP uses the Burroughs Direct Interface (B
D r ), ie on other data link processors that are part of the system h1 configuration via the test bus function.

U rPl 00 (via PCC 40) also provides a link to remote support center 50r for remote diagnostics.

Although a preferred embodiment of a knee 11 interface processor and its maintenance system has been described, other equivalent embodiments may be developed within the spirit of this disclosure as defined by the following claims.

[Brief explanation of the drawing]

1-1 and 1-2 are block diagrams of user interface processors used in maintenance system networks. FIG. 1 is a diagram showing the relationship between FIG. 1-1 and FIG. 1-2. Figures 1A, 1B, 1C and 1D are system and sigma network diagrams showing how the user interface processor module connects to other elements of the system network to provide a maintenance subsystem. 1-A diagram of a workpiece. FIG. 2 is a block diagram of the serial communication controller element of the user interface processor. Figures 3A and 3B are block diagrams illustrating the data paths included in the serial communication controller. FIG. 3 is a diagram showing the relationship between FIG. 3Δ and FIG. 3B. FIG. 4 is a block diagram of the communications/output elements of the user interface processor. FIG. 5 is a block diagram showing the ports of the communication unit/output unit. FIG. 6 is a block diagram of a communication input/output port designated as port C. FIG. 7 is a block diagram of the communication personnel/output unit counter unit in FIG. 4. FIG. 8 is a block diagram of the dawn interrupt controller (PR[TC) of the user interface processor. Figures 9A and 9B are block diagrams of units designated as data link interfaces/top subordinate ports. FIG. 9 is a diagram showing the relationship between FIGS. 9A and 9B. In the figure, 30 is a main processor, 32 is a memory control unit, 34 is a main memory, 40 is a processor interface card, 50 is a power control card, 100 is a user interface processor, 110 is a microprocessor, 120 is a peripheral interface, and 180 is a DLI
/HDP controller, 500 indicates an upper subordinate port. ((1 or 2 stones) FIG, 1-!5'. Meb Death - Jirebe Nomushitarian Isu MCU - Memo,
So Gentai P Unit HOP/ Upper It Lt Friend, Tameki Ito t Te Name f) PCC

Claims (1)

[Claims] (1) Data link processor (I/O controller)
A user interface processor for supporting and maintaining operations in a computer network having a host computer and an I/O subsystem connected to a peripheral unit via: (a) a microprocessor subsystem; The system includes (a1) microprocessor means for executing instruction and data transfer operations, the microprocessor means having memory means, a plurality of serial communication controllers, and a plurality of I/O
(a2) the memory means is connected to a port means and a programmable priority interrupt controller; (a2) the memory means includes a PR for storing firmware instruction data;
OM memory means; (a2b) RAM memory means for temporarily storing code for performing initialization and maintenance routines; (a4) the plurality of I/O port means are for bidirectional parallel data transfer connections to a second set of external units; (a5) ) further comprising programmable priority interrupt controller means connected to said microprocessor means for receiving interrupt signals from said serial communication controller and said I/O port means and providing priorities; (a5a) means for outputting a vector data signal to the microprocessor means to select a service routine; and (a6) receiving instruction data from the microprocessor means and transmitting the command data to the priority interrupt controller means. further comprising a plurality of programmable interval timers providing time-interval signals; (6) connected to said microprocessor means, said serial communications controller, said I/O port means, and said priority interrupt controller means; further comprising a dual function controller configured to provide an interface for data transfer and (b1) means for performing transfer operations as a data link transfer interface to the data link processor; b2) means for performing data transfer operations as a message level interface to said host computer. (2) Each of the serial communication controllers provides two independent, serial, full-duplex data-communication channels operable in both synchronous and asynchronous protocols. User interface processor as described. 3. The user interface processor of claim 1, wherein each of said serial communication controllers operates as a slave interrupt controller in accordance with a priority signal from said priority interrupt controller means. (4) Each of the serial communication controllers includes (a) transmitter section means, the transmitter section means comprising: (a1) means for programming a periodic character in a byte-oriented mode; and (a2) a single synchronous mode. for 6-bit or 8-bit
Claim 1 comprising means for programming a bit synchronous character; (a3) means for programming a 15-bit synchronous character in bisynchronous mode; and (a4) means for programming for asynchronous data transmission. User interface processor as described. (5) Each of said serial communication controllers includes (a) receiver section means, said receiver section means comprising: (a1) register means for buffering at least three bytes of incoming data in an asynchronous/synchronous mode; a2) means for delaying at least 3 bits of serial data in a synchronous mode. (6) The receiver section means includes: (a) means for searching for and detecting an incoming bit or byte pattern that matches a programmed bit or byte pattern and further establishing a synchronization signal; 6. User interface processor according to clause 5. (7) The microprocessor means is operable to set each of the serial communication controllers to operate in a polling mode or an interrupt mode; (b) polling means for determining whether a transmit-data operation is requested and performing said data transfer operation without interruption; (b) determining when a receive or transmit operation is requested in the serial communications controller by means of an interrupt signal; 2. A user interface processor according to claim 1, further comprising means for determining. (8) Each of said I/O port means comprises: (a) two 8-bit parallel general purpose ports providing handshake data transfer operations to said second set of external units; and (b) said two 8-bit parallel general purpose ports. 2. A user interface processor as claimed in claim 1, including one 4-bit parallel dedicated port providing a handshake line to each of the bit general purpose ports. (9) Each of said I/O port means comprises: (a) means for detecting when an incoming data pattern matches a preprogrammed pattern; and (b) means for detecting when said match occurs. (c) polling means for determining whether the serial communication controller requests a receive data or transmit data operation and performs the data transfer operation without interrupt; 9. The user interface processor of claim 8, further comprising: (d) means for determining when a receive or transmit operation is requested at the communications controller by an interrupt signal. (10) said programmable priority interrupt controller means: (a) means for receiving an interrupt signal from each of said serial communication controllers; and (b) means for receiving an interrupt signal from each of said I/O port means. (c) means for receiving an interrupt signal from each of said programmable interval timers; and (d) means for receiving an interrupt signal from said dual function controller. 2. The user interface processor of claim 1. 11. The dual-purpose controller: (a) means for performing burst mode data transfer of blocks of data to the first and second sets of external units; User interface processor as described. (12) the dual-purpose controller: (a) includes means for performing data transfer to/from the data link processor;
A user interface processor according to claim 1. 13. The user interface processor of claim 1, further comprising buffered interface means including (a) means for data transfer to/from the primary host computer.