JPS61180349A - Data processor - Google Patents

Abstract

PURPOSE:To attain plural main memory accesses with less hardware quantities with a data processor which performs the address conversion, by controlling the number of array elements to receive accesses in each cycle to the maximum number of elements that can be converted at a time. CONSTITUTION:A processing part 1 performs a vector operation. Array elements needed for operations are obtained by performing the address calculations from the head element address B and the inter-element distance D like B, B+D and B+2D and according to B+iXD (i=n-1, n: number of elements). In case the access is possible for maximum four array elements at a time in a vector processing mode, the 1st access is carried out with B, B+D, B+2D and B+3D and the 2nd access with b+4D, B+5D, B+6D and B+7D respectively. Then the 2nd access is also defined as B1, B1+D, B1+2D and B1+3D as long as B1=b+4D is satisfied. Then the value of B is increased by (DX4) for each machine cycle, and O, D, DX2 and DX3 are added to the value of B. Thus the element address is obtained for each access.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to address translation in a data processing device,
In particular, it relates to address conversion when multiple memory accesses are performed simultaneously.

(Prior Art) In recent years, the need for ultra-high-speed scientific and technological computers (supercomputers) has been increasing for simulations in the fields of weather prediction and nuclear power, and image processing in the field of resource exploration. Supercomputers mainly perform so-called vector operations in which the same operation is performed on each set of a large amount of data arranged in an array. Each element in the array is stored in the main memory, which is relatively slow, and is stored in the main memory, which has a relatively slow speed.
The array row, column, and diagonal direction (B+1
D) (where l is an integer) is read out to the processing device at regular intervals and stored at the same or different address after arithmetic processing. Since the array data to be handled is generally larger than the capacity of the main memory, a so-called virtual memory method is used in which the logical addresses on the program are converted to real addresses according to an address conversion table and the main memory is accessed. It is common to adopt

In order to perform address translation at high speed, an address translation buffer is often provided to hold a copy of the address translation table stored in the main memory. In order to improve the performance of a processing device that executes vector operations, it is important to have access to the main memory that is commensurate with the internal processing speed.

Conventionally, in this type of address translation method, multiple address translation buffers are provided for each access in order to access multiple main memory addresses simultaneously, and address translation data for multiple pages are simultaneously read, thereby providing main memory access to multiple pages. Simultaneous processing has improved data throughput with the main memory. Such a technique is described in, for example, Japanese Patent Application Laid-Open No. 57-57370.

(Problems to be Solved by the Invention) In such a conventional configuration, since providing a plurality of address translation buffers would require K, there was a drawback that the amount of hardware would increase.

An object of the present invention is to adjust the number of array elements to be accessed in each cycle to the maximum number that can be converted simultaneously in a data processing device that converts addresses to access a main memory by generating multiple addresses simultaneously. The object of the present invention is to provide a data processing device configured to eliminate the above-mentioned drawbacks and to allow access to a plurality of main memories with a small amount of hardware.

(Means for Solving the Problems) A data processing device according to the present invention includes a storage device for storing array element data, and when accessing the array element data stored in the storage device, the data processing device according to the present invention The device is configured to access data after performing address conversion, and is particularly equipped with address generation means, address conversion means, detection means, and request adjustment means, and is configured to handle requests in each cycle for multiple addresses. Within the range, the unit address including the first element is suppressed, and the real address of the request to the storage device is generated based on the output of the address conversion means and the plurality of outputs from the address generation means.

The address generating means is for generating a plurality of addresses simultaneously from the leading element address and the inter-element distance for each access cycle in order to access a specific set of array element data.

The address conversion means is accessed at the first element address of each cycle and holds a copy of a portion of the address conversion data in order to quickly convert the plurality of logical addresses generated by the address generation means into real addresses of the storage device. belongs to.

The detection means is connected to the address generation means and is for detecting whether the logical addresses generated simultaneously in each cycle are within a unit address range including the leading element address.

The request adjustment means limits the request in each cycle to a logical address within a unit address based on the detection result of the detection means, and determines the leading element address in the next cycle.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In FIG. 1, 1 is a processing section;
0 is the address register, 20 is the required cumulative distance register, 3
o is a multiple generation circuit, 40 is an address conversion circuit, 50 is a selection circuit, 60 to 63 are adders, and 70 is a page overflow detection circuit.

The processing unit 1 is for performing vector calculations. The array elements required for the operation are B+1XD (like B, B+DXB+2D) from the destination-element address B and the distance between elements
1=n-1: n is the number of elements). The data processing device of this embodiment can access up to four array elements simultaneously during vector processing. In this case, the first access is BXB+D, B+2D, as described above.

It was B+3D, and the second time was B+4DXB+5D.

B+6D, B+7D. Here, if B1=B+4D, the second access is Bl, B+4XB+5D,
B1+3D, the value of B is changed every machine cycle (DX4
), and add 0. to the value of B above. DXDX2, DX3
By adding , we can obtain the element address for each access.

Similarly, if the requests to be output simultaneously are 1.2.3, it can be seen that 2D and 3D can be used instead of 4D.

Referring to FIG. 2, the relationship between logical addresses and real addresses in a data processing device according to an embodiment of the present invention is shown. In Fig. 1, to simplify the explanation, L=1
0. Let m=20, n=5, and the least significant bit of the address is the array element address (word). Logical address space is 2
m = 2" = 1.048,576 word units (hereinafter referred to as pages, 2' = 2" = 1024 words) divided into K, L
, P indicates a logical page number, and A indicates an intra-page address. The real address space is also a page with the same capacity (2n=2'
=32 pieces), RP indicates the real page number, and the intra-page address A is the same as that in the logical address space. The process of indexing an address conversion table indicating the position of the logical page in the real address space from the logical page number LP and obtaining the real page number RP from this is called logical-to-real address conversion. This address translation is
In the figure, it is indicated as AT. By configuring like this,
Even if the storage device has a capacity of 32 pages, by loading the required 32 pages or less into the storage device at the same time, the program will be able to store 1024 pages, which is 32 times as large.
Data can be handled as if it were a page.

FIG. 3 is an explanatory diagram showing the relationship between each element of the logical space and the page. In FIG. 3, in (a), the distance between the elements is relatively small, and the first and second requests are within the same page given by LP=C, but the third request is Regarding the request, the request from the top element address B2 to B2+2Dt at the time of the above request exists in the page given by LP=C, and the request for B2+3D is LP
= exists on the page given by C+1.

Here, it is assumed that D>0. In FIG. 3, in (b), the distance between the elements is relatively large, and in the first request, the leading element addresses BO1BO+D, B
The request for O+2D is contained in the page given by LP=C, but the request for B+3D is on another page given by LP=C+1. Here, in this embodiment, it is assumed that D<LP.

In the above description, for ease of handling, it is assumed that address translation is performed for only one page per machine cycle. Therefore, if the adjustment is made so that the number of requests that fit within the page where the first address exists is adjusted, the maximum number of real addresses that can be sent in the machine cycle described above can be obtained. .

FIG. 4 is a timing chart showing the operation of the data processing device shown in FIG. Next, the operation of each part shown in FIG. 1 will be explained with reference to the timing chart shown in FIG. Fourth
In the timing chart shown in the figure, (A), (B)
correspond to (L) and (b) in FIG. 3 above, respectively. The above top element address B and inter-element distance are:
It is assumed that the relationship shown in FIG. 3(L) exists, and that the timing is determined according to the timing chart of FIG. 4(A).

When the processing unit 1 needs to access a vector element, the first element address B is sent at timing To. 101
The element distance is set in the address register 10 via the signal line 102, and the inter-element distance is set in the inter-element distance register 20 via the signal line . The inter-element distance set in the inter-element distance register 20 is sent to the multiple generation circuit 30 via the signal line 103.
will be sent to. The multiple generation circuit 30 generates D, 2D, 3D, and 4D from the distance between the elements, and each signal line 1
The signals are sent to adder circuits 60 to 63 via signals 01 to 110. Also, the first element address B of the address register 10
are also sent to adder circuits 60 to 63 via signal line 105. In addition circuits 60 to 63, addresses B+DXB+2D, respectively.

B+3D and B+4D are calculated. Here, of the first element address B existing on the address register 10, the upper 10 bits indicating the logical page number LP are connected to the signal line 104.
The data is sent to the address conversion circuit 40 via the address conversion circuit 40. The address conversion circuit 40 has a copy of a part of the address conversion table necessary for converting a logical address into a real address, and when a 10-bit page number of the logical address is given from the signal line 104, the corresponding real address is Page number RP 5
It is converted into bits and output from the signal line 118. Also, of the first element address B existing on the address register 10, the lower 20 bits indicating the intra-page address A and the logical address B generated by the adder circuits 60 to 62
+DXB+2D, B+3D, in-page address A
The lower 20 bits indicating the value are output via outputs 119-122, respectively. Here, for example, if the content of the output 119 is represented by AO, the contents of the outputs 120 to 122 are represented by AO+D, AO+2D, and AO+3D, respectively.

The desired real address is generated by a combination of the 5 bits of the real page number RP and the 10 bits of the intra-page address A. At timing TO, all requests are within the same page, so the above combination,
In other words, the combinations of outputs 118 and 119, outputs 118 and 1201, outputs 118 and 121, and outputs 11B and 122 are all obtained as real addresses.Furthermore, the maximum number of requests at timing TO and the leading element address B at the next machine cycle T1
In order to determine l, signal line 1 is connected from adder circuits 60 to 62.
The carry from the 10th bit to the 11th bit of the adder circuits 60 to 620 is sent to the page overflow detection circuit TO via 1b to 117.

Here, the page overflow detection circuit TO will be explained.

If the request spans multiple pages K, then D<LP.

Therefore, since the carry of the request in which a page overflow occurs for the first time always has a logical value of 12, it can be seen from the above request that a page overflow has occurred. For example, if the first element address B exists on the page given by LP=C and the value of the signal line 116.117 is a logical value 1, the page overflow detection circuit 70 detects that the requests after B+2D are given by LP=C. It is determined that the requested page does not exist, and the output 124 sends out .degree.2" as the number of requests so as to limit the number of requests to two, B and B+D.

Furthermore, in order to set the first element address in the next machine cycle to B+2D, the selection circuit 50
12, and send the above signal to signal line 1.
I'll send it out on the 23rd.

The above is an example of the operation of the page overflow detection circuit TO.

At timing TO, all requests are within the same page, so the states on signal lines 115 to 117 are all "0", and the page overflow detection circuit 10 outputs the number of requests = 4 on the signal line. It is sent from 124. Furthermore, since the leading element address at the time of the next machine cycle T1 is B+4D, the selection circuit 50 selects the signal line 1.
A selection signal for selecting 14 is sent via signal line 123. The selection circuit 50 sends the first element address B+4D to the address register 10 via the signal line 125.

A series of operations per machine cycle has been described above, but in the next machine cycle T1, the head element address B becomes B=B+4D=B1, and exactly the same operation is performed. However, the next machine cycle T2
In, if the first element address is B2, then B2+
It can be seen from FIG. 3(A) that the 3D request exists inside a page different from B2. In this case, the signal line 11
7 above, the value 3 is output as the requested number from the output signal line 124, and the selection circuit 50 selects B2+3D via the signal line 113 as the first element address in the next machine cycle T3. , signal line 12
5 to the address register 10.

In the next machine cycle T3, the first element address is B2.
+3D, and the same operation is performed thereafter. As explained above, up to four real addresses can be accessed per machine cycle.

On the other hand, when operating according to the timing chart in Figure 4(B), the distance between elements is relatively large, so the B+3D request from timing 10 o'clock causes a page overflow, and the number of requests is kept to 3. It will be done. The operation of each part is similar to the explanation given in FIG. 4(A) above. The correspondence between the general configuration requirements of the present invention and the embodiment shown in FIG. 1 will be explained as follows. That is, the address generation means corresponds to the adders 60 to 63, the address conversion means corresponds to the address conversion circuit 40, the detection means corresponds to the overpage detection circuit TO1, and the request adjustment means corresponds to the selection circuit 5OK.

(Effects of the Invention) As explained above, the present invention is capable of performing multiple main memory accesses simultaneously with a small amount of hardware by performing the maximum number of address conversions that can always be requested based on the distance between elements. This has the effect of improving data processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the relationship between logical addresses and real addresses in the embodiment shown in FIG. 1. FIG. 3 is an explanatory diagram showing the relationship between the positions of array elements in logical space and pages. FIG. 4 is a timing chart showing the operation of the embodiment shown in FIG. 1. 1... Processing unit 1Q@... Address register 20... Inter-element distance register 30... Multiple generation circuit 40... Address conversion circuit 50... Selection circuits 60 to 63... Adder 70...・Page crossing detection circuit

Claims (1)

[Claims] A storage device for storing array element data is provided, and when accessing the array element data stored in the storage device, address conversion is performed for each unit address according to address conversion data, and then the data is accessed. In the data processing device configured, address generating means for simultaneously generating a plurality of addresses from a leading element address and an inter-element distance for each access cycle in order to access a specific set of array element data; address conversion means for holding a copy of a portion of the address conversion data in order to quickly convert a plurality of logical addresses generated by the address generation means into real addresses of the storage device; and a detection means connected to the address generation means for detecting whether or not the logical addresses generated simultaneously in each cycle are within a unit address range including the leading element address; request adjusting means for limiting the request in each cycle to a logical address within the unit address based on the detection result and determining a leading element address in the next cycle;
The request in each cycle is suppressed within the range of the plurality of addresses to a unit address including the head element, and the request to the storage device is suppressed by the output of the address conversion means and the plurality of outputs from the address generation means. A data processing device configured to generate a real address of a request.