JPS61179885U - - Google Patents
Info
- Publication number
- JPS61179885U JPS61179885U JP6435185U JP6435185U JPS61179885U JP S61179885 U JPS61179885 U JP S61179885U JP 6435185 U JP6435185 U JP 6435185U JP 6435185 U JP6435185 U JP 6435185U JP S61179885 U JPS61179885 U JP S61179885U
- Authority
- JP
- Japan
- Prior art keywords
- limiting circuit
- level
- screen
- voltage
- clamps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
第１図はこの考案の一実施例を示す概略構成図
、第２図及び第３図は夫々従来の装置を示す概略
図である。
図中、１はビデオ信号の出力回路、２はその出
力端子、３，５はビデオミユートスイツチ、４は
同期信号発生回路、６はビデオ信号の入力端子、
７は抵抗、８，９はツエナーダイクオード、１０
はコンデンデンサ、１１はミユートスイツチ、１
２はトランジスタ、１３はエミツタ抵抗、１４は
カツプリングコンデンサ、１５は出力抵抗、１６
は出力端子である。なお、同一符号は相当部分を
示す。
FIG. 1 is a schematic diagram showing an embodiment of this invention, and FIGS. 2 and 3 are schematic diagrams showing conventional devices, respectively. In the figure, 1 is a video signal output circuit, 2 is its output terminal, 3 and 5 are video mute switches, 4 is a synchronization signal generation circuit, 6 is a video signal input terminal,
7 is a resistor, 8 and 9 are Zener diodes, 10
is a capacitor, 11 is a miyuto switch, 1
2 is a transistor, 13 is an emitter resistor, 14 is a coupling capacitor, 15 is an output resistor, 16
is the output terminal. Note that the same reference numerals indicate corresponding parts.
Claims (1)
圧をクランプする第１の制限回路と、画面消去時
に上記制限回路のレベルとは異なつた第２レベル
以上の電圧をクランプすると共に、上記第２レベ
ル以下の色信号を除去する第２の制限回路とを設
け、画面消去時には同期信号のみを含んだ消去画
面信号を出力するようにしたことを特徴とする記
録再生装置。 (2) 第２の制限回路は、これと直列に接続され
たスイツチによつてオンオフするようにしたこと
を特徴とする実用新案登録請求の範囲第１項記載
の記録再生装置。 (3) 第２の制限回路は、ツエナーダイオードと
、コンデンサとを並列関係に接続して構成したこ
とを特徴とする実用新案登録請求の範囲第１項又
は第２項記載の記録再生装置。[Claims for Utility Model Registration] (1) A first limiting circuit that clamps a voltage of a first level or higher to the image signal input circuit, and a second level or higher voltage that is different from the level of the limiting circuit when the screen is erased. A record characterized in that it is provided with a second limiting circuit that clamps the voltage and removes color signals below the second level, and outputs an erased screen signal containing only a synchronizing signal when erasing the screen. playback device. (2) The recording and reproducing apparatus according to claim 1, wherein the second limiting circuit is turned on and off by a switch connected in series with the second limiting circuit. (3) The recording and reproducing apparatus according to claim 1 or 2, wherein the second limiting circuit is constructed by connecting a Zener diode and a capacitor in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6435185U JPS61179885U (en) | 1985-04-29 | 1985-04-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6435185U JPS61179885U (en) | 1985-04-29 | 1985-04-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61179885U true JPS61179885U (en) | 1986-11-10 |
Family
ID=30595354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6435185U Pending JPS61179885U (en) | 1985-04-29 | 1985-04-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61179885U (en) |
-
1985
- 1985-04-29 JP JP6435185U patent/JPS61179885U/ja active Pending
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