JPS5966912U - Recording muting circuit - Google Patents
Recording muting circuitInfo
- Publication number
- JPS5966912U JPS5966912U JP16151682U JP16151682U JPS5966912U JP S5966912 U JPS5966912 U JP S5966912U JP 16151682 U JP16151682 U JP 16151682U JP 16151682 U JP16151682 U JP 16151682U JP S5966912 U JPS5966912 U JP S5966912U
- Authority
- JP
- Japan
- Prior art keywords
- recording
- circuit
- muting circuit
- monitor output
- muting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案回路の一実施例の回路図、第２図Ａ、
Ｂは本考案回路のモードを説明するための二、 タイミ
ングチャートである。
１１・・・・・・入力端子、２・・・・・・増幅器、３
・・曲録音回！ 路、４・・・・・・録再ヘッド、６
・・・・・・ソースモニタ出力乏 端子、７・・・・・
・制御回路、７ａ、 ７ｂ・・・・・・制御信号出力端
子、Ｘｌ、ｘ２・・・・・・トランジスタ、Ｒ１・・・
・・・抵抗、Ｃ１・・・・・・コンデンサ。Fig. 1 is a circuit diagram of an embodiment of the circuit of the present invention, Fig. 2A,
B is a timing chart for explaining the modes of the circuit of the present invention. 11...Input terminal, 2...Amplifier, 3
・Song recording time! Road, 4...Recording/playback head, 6
・・・・・・Loss of source monitor output Terminal 7・・・・・・
・Control circuit, 7a, 7b... Control signal output terminal, Xl, x2... Transistor, R1...
...Resistor, C1...Capacitor.
Claims (1)
ズ状態からポーズ解除を行なう時、所ガ時間ソースモニ
タ出力及び磁気テープへの録音等同時にミューティング
する回路を接続してなる録音ミューティング回路。A recording muting circuit comprising a circuit for simultaneously muting the source monitor output and recording to a magnetic tape for a certain period of time when the recording pause state is released from the recording pause state, to the connection point between the recording circuit and the source monitor output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16151682U JPS5966912U (en) | 1982-10-25 | 1982-10-25 | Recording muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16151682U JPS5966912U (en) | 1982-10-25 | 1982-10-25 | Recording muting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5966912U true JPS5966912U (en) | 1984-05-07 |
Family
ID=30354938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16151682U Pending JPS5966912U (en) | 1982-10-25 | 1982-10-25 | Recording muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5966912U (en) |
-
1982
- 1982-10-25 JP JP16151682U patent/JPS5966912U/en active Pending
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