JPS61179833U - - Google Patents

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Publication number
JPS61179833U
JPS61179833U JP6160785U JP6160785U JPS61179833U JP S61179833 U JPS61179833 U JP S61179833U JP 6160785 U JP6160785 U JP 6160785U JP 6160785 U JP6160785 U JP 6160785U JP S61179833 U JPS61179833 U JP S61179833U
Authority
JP
Japan
Prior art keywords
mos
gate
fet
source
pulse transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6160785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6160785U priority Critical patent/JPS61179833U/ja
Publication of JPS61179833U publication Critical patent/JPS61179833U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るMOS・FETの駆動回
路の一実施例を示す図、第2図は第1図を説明す
るための波形図、第3図は本考案の他の一実施例
を示す図である。 1,2……主回路端子、3……負荷、4……M
OS・FET、5,5′……ダイオード、6,9
……パルストランス、7……制御回路、8,8′
……半導体スイツチ。
FIG. 1 is a diagram showing an embodiment of a MOS/FET drive circuit according to the present invention, FIG. 2 is a waveform diagram for explaining FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 1, 2...Main circuit terminal, 3...Load, 4...M
OS・FET, 5, 5'...Diode, 6, 9
...Pulse transformer, 7...Control circuit, 8, 8'
...Semiconductor switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パルストランスを介してMOS・FETのゲー
ト―ソース間に複数の細分化パルスからなるオン
信号を与えるオン信号発生器、前記パルストラン
スの2次巻線とMOS・FETのゲート―ソース
間に直列接続されてそのゲート容量の電荷が前記
パルストランスの2次巻線を介して放電されるの
を防止するダイオード、及び前記MOS・FET
のゲート―ソース間に接続されたオフ用の半導体
スイツチからなることを特徴とするMOS・FE
Tの駆動回路。
An on-signal generator that provides an on-signal consisting of a plurality of subdivided pulses between the gate and source of the MOS/FET via a pulse transformer, and a series connection between the secondary winding of the pulse transformer and the gate and source of the MOS/FET. a diode that prevents the charge of its gate capacitance from being discharged through the secondary winding of the pulse transformer; and the MOS-FET.
MOS/FE characterized by consisting of an off semiconductor switch connected between the gate and source of
T drive circuit.
JP6160785U 1985-04-24 1985-04-24 Pending JPS61179833U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6160785U JPS61179833U (en) 1985-04-24 1985-04-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6160785U JPS61179833U (en) 1985-04-24 1985-04-24

Publications (1)

Publication Number Publication Date
JPS61179833U true JPS61179833U (en) 1986-11-10

Family

ID=30590035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6160785U Pending JPS61179833U (en) 1985-04-24 1985-04-24

Country Status (1)

Country Link
JP (1) JPS61179833U (en)

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