JPS61178800A - Memory check device - Google Patents

Abstract

PURPOSE:To form a memory check device with a reduced memory capacity by comparing and adjudicating two output data, that is, an output of an expected value data memory reading expected value data in accordance with addresses and an output of a memory to be checked. CONSTITUTION:The addresses produced by an address generator 4 are converted by an address converter 52 as a function of the location of the memory cell in a data memory 71 storing 'a portion in which real memory portions with existence of the actual memory cell are re-arranged' and 'a portion in which only memory cell void portions are compressed and re-arranged' of a ROM6 to be checked. Hence, output data applied to and read from the ROM6 to be checked is applied to one data comparator 8 while the data read from the ROM6 to be checked are applied to the other comparator 8 and the two output data are sequentially compared to each other to check the ROM6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory testing device for testing the functionality of a semiconductor read-only memory (hereinafter referred to as ROM).

(Prior Art and its Problems) Conventionally, this type of memory testing device incorporates an address generator, an expected value data memory, an address converter for the ROM to be tested, and a data comparator. FIG. 3 is a block diagram of a bang generation section and a data comparison section of a conventional memory testing device. In the figure, 4 is an address generator, 5 is an address converter, 6 is a ROM to be tested, 7 is a data memory, and 8 is a data comparator.

First, the address generated by the address generator 4 is converted by the address converter 5 into an address that conforms to the physical arrangement of the memory cells of the ROM 6 to be tested, and the data memory 7
and the ROM 6 to be tested, and when the output data from both of them is read out, the data comparator 8 successively compares the two output data to test the ROM 6 to be tested.

However, in conventional memory testing devices of this type, the expected value data memory 7 requires a capacity that is the same as or slightly larger than the memory capacity of the ROM 6 to be tested, and the address at the time of reading is 1 to 1 of the RObf 6 to be tested. = 1, therefore, if the memory configuration of the ROM to be tested is special, there is a problem that the address range becomes extremely larger than the actual memory capacity in which the memory cells actually exist. An example of a special ROM with gaps in the actual memory cell arrangement is one in which the virtual area is 12 megabits and the actual memory area is L2 megabits (Magazine "Electronic Materials", published January 1, 1980). Volume 23μ
(See No. m).

FIG. 4 is a memory configuration diagram for explaining this special ROM, showing an example in which the virtual area is 64 bits and the real memory area is 16 bits. In the figure, 1 is an X decoder, 2 is an X decoder, and 3 is a memory cell array. These X decoders 1, A total of 64 bits of memory cells consisting of 0 and 48 bits can be addressed. Of these, (1) to (9) and (8 to 0) are real memory areas where memory cells actually exist, and 48 (to) are areas where there is a gap in the arrangement of memory cells.This special ROM When testing, it is necessary to configure the expected value data memory capacity to be equal to or slightly larger than the virtual memory capacity, that is, the address space of the ROM to be tested, which is not economical, and the data It was unreasonable and undesirable from a management standpoint.

(Object of the Invention) An object of the present invention is to develop a memory with a reduced memory capacity to the extent that the expected value data memory capacity of the ROM does not significantly exceed the actual real memory capacity when inspecting such a special ROM. Our objective is to provide inspection equipment.

(Configuration of the Invention) The configuration of the present invention includes an address generator, and an address signal generated from the address generator that is used for testing the memory contents of a memory under test that stores expected value data. a first address converter that converts the address signal into an address that conforms to the physical arrangement of memory cells of the memory; and a second address converter that converts the address signal generated from the address generator into an address that conforms to the storage state of the expected value data.
an address converter, an expected value data memory that reads the expected value data according to the address of the second address converter, and a data comparison that compares and determines the output data of both the expected value data memory and the memory under test. equipped with a vessel,
The present invention is characterized in that the storage capacity of the data memory is reduced.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the memory testing device according to the present invention, and FIG. It is a layout diagram. In the figure, 4 is an address generator, 51.52 is an address converter, and 6 is an RO to be tested.
M, 7 is a decoder memory, and 8 is a data comparator.

First, the address generated by the address generator 4 is converted by the address converter 51 into an address that conforms to the physical arrangement of the memory cells of the ROM 6 to be tested, and then
The read output data is input to one of the data comparators 8. address generator 4
The address generated in is converted by the address converter 52 into
Memory cells of the data memory 7 that store "a part where only the missing memory cells are compressed and rearranged" and "a part where only the real memory part where memory cells actually exist are rearranged" of the ROMg to be inspected. The address is converted according to the location of the address.

FIG. 2 is a diagram showing an example of the arrangement of this memory cell.

A total of 25 bits of memory cells consisting of (1) to (9), (8 to 0, and 9 (to)) allocated to this memory cell array 3 are transferred to a 5-bit X decoder 1 and a 5-bit X decoder 2. Address can be specified by

Among these, data of (1) to (9) and (8 to 0) is the fourth
It is equal to the data of (1) to (9) and (6) to 0 of the real memory area where the memory cells actually exist in the special ROM shown in the figure, and the gaps in the memory cell arrangement are filled in and rearranged. The 25 numbers are compressed and stored in nine rows each consisting of one row address and one column address in the data memory.

This address conversion of the memory cell array 3 is performed using a special R
(2) of the real memory area where memory cells actually exist in OM
) , (4) , (5) , (7) in the data memory (0) , (1) , (2) , (3) ,
Also, there are gaps in the arrangement of memory cells, (o),
(1), (a), and (6) are converted to correspond to (4) in the data memory. Therefore, the output data added to the data memory 71 of this embodiment and read out is inputted to one side of the data comparator 8, and the R
The data read from the OM6 is input to the other side of the data comparator 8, the output data of both are successively compared, and the data is output to the RO under test.
M6 can be inspected.

(Effects of the Invention) As explained above, according to the present invention, it is sufficient to prepare a data memory that stores only special storage contents, so that the expected value data of a ROM of the same capacity as the virtual memory space is stored in the device. There is no need to provide memory, which is advantageous both economically and in terms of data management.

Therefore, when testing a special ROM, it is possible to obtain a memory testing device with a walking capacity in which the expected value data memory capacity of the ROM does not significantly exceed the actual memory capacity that actually exists.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of a conventional memory inspection device, and FIG. 4 is a memory layout diagram of an example of the data memory shown in FIG. In the figure, 1...Y decoder, 2...X decoder, 3...memory cell array, 4...address generator, 5°51.52. ... Address converter, 6 ... ROM to be inspected. 7.71...Data memory, 8...Data comparator, Figure 2I! T field 4 m

Claims (1)

[Claims] A memory testing device for testing the storage contents of a memory to be tested that stores expected value data includes an address generator and an address signal generated from the address generator that corresponds to the physical arrangement of memory cells of the memory to be tested. a first address converter that converts the address signal into an address; a second address converter that converts the address signal generated from the address generator into an address that conforms to the storage state of the expected value data; It comprises an expected value data memory that reads out the expected value data according to the address of the converter, and a data comparator that compares and determines the output data of both the expected value data memory and the memory under test, and the storage capacity of the data memory is A memory inspection device characterized by a small amount of memory.