JPS61177051A - Lsi for packet control - Google Patents

Lsi for packet control

Info

Publication number
JPS61177051A
JPS61177051A JP60017936A JP1793685A JPS61177051A JP S61177051 A JPS61177051 A JP S61177051A JP 60017936 A JP60017936 A JP 60017936A JP 1793685 A JP1793685 A JP 1793685A JP S61177051 A JPS61177051 A JP S61177051A
Authority
JP
Japan
Prior art keywords
frame
terminal
lsi
control part
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60017936A
Other languages
Japanese (ja)
Inventor
Kiichiro Ito
伊藤　喜一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60017936A priority Critical patent/JPS61177051A/en
Publication of JPS61177051A publication Critical patent/JPS61177051A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To allow an external circuit to detect a transfer request of cause information only by monitoring an LSI terminal by forming a means for receiving a frame having a specific rink address and the LSI terminal for outputting the reception of the frame and the contents of a control part of the frame to the external at the reception. CONSTITUTION:A protocol control part 10 receives data from an interface terminal 20 of a packet communication circuit, executes protocol control and has a function for receiving a specific rink address in addition to reference protocol processing. Receiving the frame having said address, the control part 10 turns on a specific rink address frame reception display part 11, so that a terminal 30 is turned on. In addition, the control part 10 sets up a value of a control part included in said frame on a command register 12. When the display part 11 is turned on, a selector 13 is turned to the register 12 side and the value of the register 12 is displayed on a terminal 31.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はデータ通信の分野に於けるパケットプロトコル
制御方式に関し、％ＶｃＬＳＩ化されたパケットプロト
コル制御用ＬＳＩの構成に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a packet protocol control system in the field of data communication, and more particularly to the configuration of a packet protocol control LSI that is converted into a %VcLSI.

（従来技術） 従来、この種のＬＳＩは、マイクロプロセッサに接続さ
れマイクロプロセッサからの初期設定やデータ送受のた
めのコマンドにしたがって動作する構成となっていえ。(Prior Art) Conventionally, this type of LSI has been configured to be connected to a microprocessor and to operate according to commands for initial settings and data transmission/reception from the microprocessor.

このように従来のＬＳＩは該ＬＳＩを制御するマイクロ
プロセッサが動作していて始めてプロトコルの制御が実
行できる構成となっている。このため、パケット通信回
線を介してのプロセッサ部のパワーオンやプロセッサス
トップ原因情報の転送は不可能であるという欠点があっ
た。In this way, conventional LSIs have a configuration in which protocol control can only be executed when the microprocessor controlling the LSI is operating. For this reason, there was a drawback in that it was impossible to power on the processor section or transfer processor stop cause information via the packet communication line.

（発明の目的） 本発明は、上述した欠点をなくシ、外部回路はＬＳＩの
特定端子をレベル監視することのみでパワーオンやプロ
セッサストップ原因情報の転送要求を検出することので
きるパケット制御用ＬＳＩを提供することを目的とする
ものである。(Object of the Invention) The present invention eliminates the above-mentioned drawbacks, and provides an LSI for packet control in which an external circuit can detect a request for power-on or transfer of processor stop cause information only by monitoring the level of a specific terminal of the LSI. The purpose is to provide the following.

（問題点を解決する念めの手段） 本発明のパケット制御用ＬＳＩは、パワーオンやプロセ
ッサストップ原因情報転送要求を転送するために割シ当
てられた特定リンクアドレスを有するフレームを受信す
る手段と、該フレームを受信した時その旨を外部へ通知
するためのＬＳＩ端子と、該フレームを受信した時その
フレームの制両部の内容を外部へ出すためのＬＳＩ端子
とを有して構成される。(Measures to Solve the Problem) The packet control LSI of the present invention is a means for receiving a frame having a specific link address assigned for transmitting a power-on or processor stop cause information transfer request. , is configured with an LSI terminal for notifying the outside when the frame is received, and an LSI terminal for outputting the contents of the control section of the frame when the frame is received. .

（実施例） 次に、本発明を、図面を参照して実施例につき説明する
。(Example) Next, the present invention will be described with reference to the drawings.

図面は本発明の一実施例を示したＬＳＩのブロック構成
図である。プロトコル制御部ｌＯは、パケット通信回線
インタフェース端子２０からのデータを受信し、プロト
コル制御を行い、標準のプロトコル処理の他に特定のリ
ンクアドレスモ受信する機能を有している。このプロト
コル制御部１０は特定リンクアドレスを有するフレーム
を受信すると特定リンクアドレスフレーム受信表示部１
１をオンとし、これによって端子３０がオンとなる。又
プロトコル制御部ｌＯは前記特定リンクアドレスのフレ
ームに含まれていた制御部の値をコマンドレジスタ１２
にセットする。４１［ＩＪンクアドレスフレーム受信表
示部１１がオンになると。The drawing is a block diagram of an LSI showing an embodiment of the present invention. The protocol control unit 1O receives data from the packet communication line interface terminal 20, performs protocol control, and has a function of receiving specific link addresses in addition to standard protocol processing. When this protocol control unit 10 receives a frame having a specific link address, the specific link address frame reception display unit 1
1 is turned on, thereby turning on the terminal 30. Further, the protocol control unit 10 stores the value of the control unit included in the frame of the specific link address in the command register 12.
Set to . 41 [When the IJ link address frame reception display section 11 is turned on.

セレクタ１３はコマンドレジスタ１２側に切す替わシ、
コマンドレジスタ１２の値はセレクタ１３を経て端子３
１へ表示される。The selector 13 is switched to the command register 12 side,
The value of command register 12 is sent to terminal 3 via selector 13.
1 will be displayed.

（発明の効果） 以上説明したように本発明のパケット制御用ＬＳＩを使
うことにより、外部回路はＬＳＩの特定端子をレベル監
視することだけでパワーオンやプロセッサストップ原因
情報転送要求を検出することができる。(Effects of the Invention) As explained above, by using the packet control LSI of the present invention, the external circuit can detect a power-on or processor stop cause information transfer request simply by monitoring the level of a specific terminal of the LSI. can.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の一実施例に係るＬＳＩのブロック構成図
である。 １０・・・プロトコル制御部、 １１・・・特定リンクアドレスフレーム受信表示部、１
２・・・コマンドレジスタ、 １３・・・セレクタ、 ２０．３０，３１・・・ＬＳＩ端子。The drawing is a block diagram of an LSI according to an embodiment of the present invention. 10... Protocol control section, 11... Specific link address frame reception display section, 1
2...Command register, 13...Selector, 20.30, 31...LSI terminal.

Claims (1)

【特許請求の範囲】[Claims] 　パケット通信のプロトコル制御を行うパケット制御用
ＬＳＩに於いて、特定のリンクアドレスを有するフレー
ムを受信する手段と、該フレームを受信した事をＬＳＩ
端子に表示する手段と、該フレームの制御部の内容をＬ
ＳＩ端子へ出力する手段とを有することを特徴とするパ
ケット制御用ＬＳＩ。In a packet control LSI that controls packet communication protocols, there is a means for receiving a frame having a specific link address, and an LSI that indicates that the frame has been received.
The means to display on the terminal and the contents of the control section of the frame
1. A packet control LSI comprising means for outputting to an SI terminal.
JP60017936A 1985-02-01 1985-02-01 Lsi for packet control Pending JPS61177051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60017936A JPS61177051A (en) 1985-02-01 1985-02-01 Lsi for packet control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60017936A JPS61177051A (en) 1985-02-01 1985-02-01 Lsi for packet control

Publications (1)

Publication Number Publication Date
JPS61177051A true JPS61177051A (en) 1986-08-08

Family

ID=11957661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60017936A Pending JPS61177051A (en) 1985-02-01 1985-02-01 Lsi for packet control

Country Status (1)

Country Link
JP (1) JPS61177051A (en)

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