JPS61174594A - Drive circuit for display body - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a fluorescent display having a plurality of segments or a number of dots, an LED display (light emitting diode display), an L
The present invention relates to a drive circuit for driving a display such as a CD display (liquid crystal display).

(Prior Art) Conventionally, as a technology in this field, there has been a technology as shown in FIG. 2, for example.

Fig. 2 is an overall configuration diagram of a conventional display drive circuit (hereinafter referred to as a drive device equipped with a plurality of dryers). This display body l is driven by two drivers 10.20.Output terminals 10-1 to 10-n of one of the drivers lO are located on the left side of the display body l.
The output terminals 20-1 to 20-n of the other driver 20 are respectively connected to the right side of the display 1, and one driver 10 connects the left half of the display 1, and the other driver 20 connects the right half of the display 1. are each driven separately. Each driver 10.20 has a plurality of input terminals 50, 80.
, 71, and 72 are connected to each other. Here, the input terminal 50 is a terminal for inputting a serial data signal that is the basis of display, and the input terminal 60 is for inputting a clock pulse CP for shifting the data signal into each driver 10.20 and accumulating it. terminal, input terminal 71 is driver 1
A terminal for inputting a chip select signal C51 for specifying whether to shift in a data signal to the driver 20, and an input terminal 71 for specifying whether to shift in a data signal to the driver 20. Select signal CS
This is a terminal for inputting 2.

During data signal transfer to the right half of the display body 1, the chip select signal CS2 is turned on and the chip select signal C9I is turned off. On the other hand, during the data signal transfer to the left half of the display body l, the chip select signal CS
I is turned on and the chip select signal C52 is turned off. As a result, driver 1 corresponding to the display position
Transfer the data signal at 0.20.

FIG. 3 is a circuit diagram of the driver 10 in FIG. 2. Note that the driver 20 has the same circuit configuration as the driver 10.

The driver 10 includes an AND gate circuit 11, a shift register 12 . It is composed of a latch circuit 13 and an output stage 14. The AND gate circuit 11 receives the clock pulse CP and the chip select signal C8I, and controls the sending of the clock pulse CP based on the chip select signal C9I.

The shift register 12 inputs the clock pulse CP and data signal output from the gate circuit 11, sequentially inputs the data signal based on the clock pulse CP, and sends parallel outputs to the latch circuit 13. The latch circuit 13 stores the parallel outputs of the shift register 12 at predetermined timing based on the load signal LD applied from the input terminal 80. The output stage 14 outputs an image display signal from output terminals 10-1 to 10-n based on the output data of the latch circuit 13. That is, the output stage 14 is the latch circuit 13
The output data of 1 is converted into a high voltage signal when the display 1 is a fluorescent display, a large current signal when it is an LED display, and a multi-value voltage signal corresponding to a data signal when it is an LCD display.
Each is converted and output to output terminals 10-1 to 10-n.

Next, the operation of the drive device configured as described above will be explained. First, in FIG. 2, when a serial data signal is transferred to the drivers 10 and 20 and display data for one line is accumulated, the output terminals 10-1 to 10-n, 20- of the driver 10.20 are An image display signal is output from 1 to 20-n, and an image is displayed depending on the displayed weight.

The issue at this time is the data transfer speed. For example, if TV image data (TV image data) is
When displaying on an LCD screen with 200 vertical dots, the effective screen is approximately 501 LS out of 63.5 LS of one horizontal time of the TV signal, so it is necessary to transfer serial data for 320 dots during this time. be. Therefore, a data transfer rate of 320/50p S = 8.4 MHz is required.

However, it is extremely difficult to obtain a driver composed of such a high-speed IC (integrated circuit). and,
Advances in IC technology have increased the data transfer rate Ef to 4MHz.
Even if this becomes possible, if larger screens are required, there will be no end to the demand for faster data transfer speeds.

For this reason, a drive device as shown in FIG. 4, for example, has been proposed as a system for effectively increasing the data transfer speed even if the transfer response speed of the driver is low.

Figure 4 shows a driving device that uses a different driver for every other pixel (hereinafter referred to as odd/even system, ODD/EVEN system). A specific example is shown in which the number of pixels in the direction (number of segments or dots) is 320, and the number of outputs per driver is 80.

In FIG. 4, 101 is a display body, and this display body 1
01 has 320 pixels in the horizontal direction and has a large number of pixel input terminals x1 to X320. And this display body 101
has four drivers 110, 120, 130, 14
0 is connected. Each of the drivers 110 to 140 has a basic circuit configured in the same manner as shown in FIG.
EIo, 130-1 to 130-80, 140-1 to 14
0-80, and are connected to the pixel input terminals X1 to X320 of the display body 101, respectively.

Each driver/<110-140 is assigned a role; the driver 110 controls the odd-numbered pixels on the left side of the display body 101, the driver 120 controls the even-numbered pixels on the left side of the display body 101, and the driver 130 controls the odd-numbered pixels on the right side of the display body 101. pixels of
The driver 140 drives each even-numbered pixel on the right side of the display body 101.

In order to provide signals to each driver 110-140, a large number of input terminals 150, 181, 182, 171, 173,
174 are provided. The input terminal 150 inputs the serial data signal 010 to each driver 110 to 14G.
and input terminal 18! The input terminal 162 inputs the clock pulse CPII to the drivers 110 and 130, and the input terminal 162 inputs the clock pulse CP12 to the drivers 120 and 1.
40 each. Also, each input terminal 171~! 7
4 are chip select signals C511, C512, and
Input C513 and C514 to each driver 110-14
Give to 0.

Next, the operation of the drive device shown in FIG. 4 will be explained with reference to FIG. 5. In addition, FIG. 5 is a signal waveform diagram of the numbered part of the fourth diagram, in which OD represents odd-numbered data and ED represents even-numbered data, respectively.

The drivers 110-140 receive clock pulses CPII, 1
Assuming that data signal 010 is shifted in at the rising edge of 2, in order to read data signal 010 accurately,
For serial data signal 010, in which odd-numbered data OD and even-numbered data ED are transferred alternately, clock pulse CPII goes to a low level (hereinafter referred to as L) approximately in the middle of the timing when odd-numbered data OD is transferred. ) to a high level (hereinafter referred to as H), and the clock pulse cpt2 is inverted from L to H at approximately the center of the timing when the even-numbered data HD is being transferred, and has an opposite phase relationship with the clock pulse CPII. let

On the other hand, the chip select signal C9II is the odd-numbered data O.
The chip select signal G512 changes from L to H (ON state) before D is input, and the chip select signal G512 becomes ON state before even-numbered data ED is input. Chip select signals C5II and C812 are clock pulses CPII,
The waveform is shifted by one cycle of CP12. Similarly, chip select signals C913 and csi4 have waveforms that are shifted by one period of clock pulse CPII, 12.

Chip select signals GSII and C512 are displayed on the display body 101
It is turned on at the time of transferring data signal 010 corresponding to the left screen of the chip select signal C513 and C51.
4 is a data signal 01 corresponding to the right screen of the display 101
It is turned on at the transfer timing of 0 and causes the display body 101 to display a predetermined image.

As described above, in the drive device shown in FIG. 4, the odd numbered data OD and the even numbered data ED are alternately transferred, so the drivers 110 and 130 take in only the odd numbered data OD, and the drivers 120 and 140 take in only the odd numbered data OD. Since it is only necessary to import even-numbered data HD, each driver 110 to
140, it is sufficient to perform the shift operation at a frequency that is half the data transfer rate.

(Problem to be Solved by the Invention) However, in the drive device having the above configuration, the drivers 110 and 130 that receive the odd-numbered data OD and the drivers 120 and 140 that receive the even-numbered data ED have different chip selects. Since signals C5II to C514 and clock pulses CPII and CP12 are required, these signals C511 to C:S14. CPII, C:PI
This not only complicates the circuit configuration for generating 3, but also increases the number of signal wires and their routing.

This invention solves the problems that the prior art had,
The present invention provides a display driver (driving circuit) that solves the problem of a large number of signal wires.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an ODD/EVE that is equipped with a gate circuit, a shift register, a latch means, and an output throw, and is capable of high-speed data transfer for large screen display.
In the dryer of a display body adopting the N method, a control signal and a clock pulse are inputted, and an inverting circuit that supplies the clock pulse as it is or inverted based on the control signal to the gate circuit, and a control signal and a chip select signal. is inputted and, based on the control signal, the chip select signal is applied to the gate circuit either as is or after being delayed by a predetermined time.

(Function) According to the present invention, since the display driver is configured as described above, the inversion circuit and the delay selection means work to change the timing of the clock pulse and the chip select signal based on the control signal. , Therefore, depending on the control signal, it is possible to select whether the driver of the present invention handles odd-numbered data or even-numbered data. Therefore, by configuring a drive device using a plurality of drivers of the present invention, it becomes possible to share the clock pulse and chip select signal supplied to the driver that handles odd-numbered data and the driver that handles even-numbered data. This allows the number of signal wires to be reduced. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a driver showing an embodiment of the present invention.

In FIG. 1, 210 is a driver, and this driver 210 is a two-man power output AN, as in FIG.
A D gate 211, a shift register 212 that sequentially inputs the data signal 020 based on the output signal of the AND gate 211, a latch circuit 213 that inputs the parallel output of the shift register 212 based on the load signal LD20, and a large number of output terminals 210- 1 to 210-n, and an output stage 214 that converts the output of the latch circuit 213 into an image display signal. In addition, the driver 210 outputs the clock pulse CP2O as it is or inverts it based on the control signal C20 and outputs the clock pulse CP2O to the AND gate circuit 211.
1 and the chip select signal C8.
21 by a predetermined amount (for example, half a cycle of clock pulse CP2O), and a control signal C2.
0, and a selection circuit 217 that selects either the chip select signal C521 or the delay circuit 216 based on the signal C521 based on the output signal C521 and provides the output signal 022 to the AND gate circuit 211.

In addition, in order to input each of the above-mentioned signals, an input terminal 250 is used to input a one-bit or multiple-bit sequential data signal (serial or parallel data signal) to be displayed (serial or parallel data signal).
．． Input terminal 28 for inputting clock pulse CP2O for introducing data signal 020 into shift register 212
0, an input terminal 2 that inputs a chip select signal C521 for specifying whether or not to input the data signal 020 by giving the output signal 023 of the AND gate circuit 211 (i.e., clock pulse CP20) to the shift register 212;
71, parallel output of shift register 212 to latch circuit 2
An input terminal 280 inputs a load signal LD20 that controls whether or not 13 is captured, and a control signal C20 that is L when handling odd-numbered pixel data and H when handling even-numbered pixel data. An input terminal 290 is provided.

When the control signal C20 is L, the clock signal CP2
O is connected to the chip select signal C92 via the inversion circuit 215.
1 is input to the AND gate circuit 211 via the selection circuit 217. Further, when the control signal C20 is H, the clock signal CP2O is inverted by the inverting circuit 215, and the chip select signal GS21 is inverted by the delay circuit 215.
After being delayed by a half period of the clock pulse CP2O, the signals are input to the AND gate circuit 211 via the selection circuit 217, respectively.

FIG. 6 is an overall configuration diagram of a drive device configured using a plurality of drivers 210 configured as described above.

In FIG. 6, 201 is the same display body as the display body 101 in FIG. 4, and this display body 201 has a large number of pixel input terminals x1 to X320. This display body 201 includes a driver 21O1 shown in FIG.
drivers 220, 230, and 240 are connected. Each driver 210-240 has 80 output terminals 210-1-210-n, 220-1-220-n, 2
30-1 to 230-n, 240-1 to 240-n, and the output terminals 210-1 to 21G-n are the odd-numbered pixel input terminals XIJ3. -...-, to X15G,
The output terminals 220-1 to 220-n are the left even-numbered pixel input terminals X2. XE, . X183. . X184. ..., X320 2. Make sure the connection is smooth.

Input terminals 250, 280, 271 shown in FIG. 1 are provided to provide signals to each driver 210-240, and
An input terminal 272 is provided for inputting a chip select signal C522. The data signal 020 inputted from the input terminal 250 and the clock pulse CP2O inputted from the input terminal 260 are given in common to each driver 210 to 240, respectively.

Furthermore, the chip select signal C821 inputted from the input terminal 271 is transmitted to the left screen display driver 210.2.
The chip select signal C522 input from the input terminal 272 to the right side screen display driver 230.24
0, respectively.

Further, an L control signal C20 is applied to the drivers 210 and 230 that handle odd-numbered data, and an H signal obtained by inverting the control signal 020 using an inverter etc. is applied to the drivers 210 and 240 that handle even-numbered data. It will be done. Although not shown, the load signal LD20 in FIG. 1 is input to each of the drivers 210 to 240, respectively.

Next, the operation of the driver configured as described above and the driving device using the same will be explained with reference to FIGS. 7 and 8. Note that FIG. 7 is a diagram of each signal waveform of the drivers 210 and 230 when the control signal C20 is L, and FIG. 8 is a diagram of each signal waveform of the drivers 220 and 240 when the control signal C20 is H. Further, OD of the data signal 020 represents odd-numbered data, and ED represents even-numbered data.

Then, the shift register 212 provided in each of the drivers 210 to 240 in FIG. 6 receives the clock pulse CP2O.
At the rising edge of the data signal 02 (at the time of inversion from L to H)
Assuming that 0 is shifted in, in order to correctly read the data signal 020, as shown in the 7th Yg:J and FIG. Clock pulse CP inverted to H
2O is applied to the inverting circuit 215 in each driver 210-240. In addition, the delay circuit 218 and the selection circuit 217 provided in each driver 210 to 240 are provided with a chip select signal that is inverted from L to H before the odd-numbered data OD to be first taken into the shift register 212 starts. C321 (or CS22) is input.

First, the driver 210. which handles only odd numbered data OD.
230 will be explained.

Since the L control signal C20 is input to the drivers 210, 230, the inversion circuit 215 in each driver 210, 230 sends out the output signal 021 which is the same as the clock pulse CP2O, and the selection circuit 217 selects the chip. The output signal 022, which is the same as the signal C521 (or CFj22), is sent out and input to the AND gate circuit 211, respectively. As shown in FIG. 7, the AND gate circuit 211 outputs an output signal 0'21 when the output signal 022 is H.
, the output signal 023 of the AND gate circuit 211 rises from L to H when odd-numbered data OD is transferred. Therefore, when the chip select signal CS21 (or C522) is H, only the odd numbered data OD is transferred to the shift register 212 and stored.

When the data signal 020 is accumulated in the shift register 212, the latch circuit 213 is activated by the load signal L port 20.
The parallel output data of the shift register 212 is taken in and supplied to the output stage 214. The output stage 214 converts the applied input signal into an image display signal and outputs it to output terminals XI, X3 .・−
・-, X15i3. X181. XIEf3. −・−・、
X319 is sent to the display body 201. As a result, the display body 201 displays the odd-numbered data OD.

Next, a driver 220. which handles only the even-numbered data HD.
240 will be explained.

Since the H control signal C20 is input to the drivers 220 and 240, the inversion circuit 215 in each driver 220 and 240 sends out an output signal 021 which is an inversion of the clock pulse CP2O, and provides it to the AND gate circuit 211. . On the other hand, chip select signal CS21 (CS22
) is delayed by a half period of the clock pulse CP by the delay circuit 216, which is selected by the selection circuit 216, and its output signal 022 is applied to the AND gate circuit 211. As shown in FIG. 8, the AND gate circuit 211 passes the output signal 021 when the output signal 022 is H, so the output signal 023 of the AND gate circuit 211 passes through the output signal 021.
is inverted from L to H at the time of even-numbered data transfer after the even-numbered data ED following the first odd-numbered data OD when the chip select signal C521 (or CS22) becomes H. Therefore, the chip select signal 0921 (or 0S22) is inverted from L to H, and only the even-numbered data ED from the even-numbered data HD following the first odd-numbered data OD is transferred to the shift register 212 and stored. Then, in the same manner as above, the shift register 21
2 parallel outputs are sent to the output stage 214 via the latch circuit 213.
is converted into an image display signal by this output stage 214, and output to the output terminals X2. X4. ...,X180.
X181°X183. ..., is given to the display body 201 via X320. As a result, the display body 201 displays the even-numbered data EO.

According to this embodiment, since the inversion circuit 215, the delay circuit 218, and the selection circuit 217 controlled by the control signal C20 are provided in the drivers 210 to 240, the control signal C20 cannot be set to H or L. Accordingly, clock pulse CP20 and chip select signals CS21 and C822
Change the timing and handle odd numbered data 00, or
You can choose whether to handle even-numbered data HD. Therefore, if a drive device is configured using such drivers 210 to 240, the chip select signal C821 supplied to the drivers 210 and 220 that sends left screen data,
Drivers 230 and 240 that send right screen data
This makes it possible to share the chip select signal C522 supplied to the chip select signal C522. Furthermore, each driver 210 to 2
It also becomes possible to share the clock pulse CP2O with 4G.

Therefore, the number of wiring lines can be reduced compared to the conventional method.

Note that the drive device using the driver 210 in the above embodiment can have various configurations other than the one shown in FIG.

(Effects of the Invention) As described above in detail, according to the present invention, since the conventional driver is provided with an inverting circuit and a delay selection means, the timing of the clock pulse and chip select signal based on the control signal is changed to You can choose whether to handle data or even-numbered data. Therefore, if a display drive device is configured using a plurality of drivers of the present invention, it is possible to
This makes it possible to share pulses and chip select signals, thereby reducing the number of wires in the entire device.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a driver showing an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a drive device configured using a conventional driver, and FIG. 3 is a circuit configuration diagram of the driver shown in FIG. 2.
FIG. 4 is an overall configuration diagram of another drive device configured using a conventional driver, FIG. 5 is a signal waveform diagram of each part of FIG. 4, and FIG. FIGS. 7 and 8 are signal waveform diagrams of each part of FIG. 6. 201...Display body, 210-240...Drive circuit (dry/su), 211...Gate circuit,
212...Shift register, 213...Latch circuit, 214...Output stage, 215...
Inversion circuit, 216...Delay circuit, 217...
・Selection circuit, C20... Control signal, CP2O...
...Clock pulse, 0921. CS22...
Chip select signal, 020...data signal, L
I]20... Own load signal.

Claims (1)

[Scope of Claims] A gate circuit to which a clock pulse and a chip select signal are input and which controls the transmission of the clock pulse based on the chip select signal; a shift register for sequentially inputting the data signals based on clock pulses and sending out parallel outputs; a latch means for storing the parallel outputs at a predetermined timing; and a shift register for driving the display body based on the output data of the latch means. an inversion circuit to which a control signal and the clock pulse are input and which supplies the clock pulse as it is or inverted based on the control signal to the gate circuit; 1. A display driving circuit comprising: a delay selection means to which a select signal is input and, based on the control signal, the chip select signal is applied as is or after being delayed by a predetermined time to a gate circuit.