JPS6117289A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To make a read voltage of memory to a large amplitude by boosting selectively a voltage of a data line, where a fine potential change appears in accordance with memory information of a memory cell, according to the voltage. CONSTITUTION:A gate voltage VG of transistors Q1 and Q2 immediately after a pulse input is impressed to a bootstrap circuit connected to digit sense lines D and -D is denoted by an equation, where VGO and VDD are an initial gate voltage and drain voltage, respectively, and the former and latter correspond to a voltage on the digit sense lines D and -D and an amplitude of an input pulse BT of the bootstrap circuit, respectively. A simbol Cb shows a connection capacity across a gate and drain of the transistor Q1 or Q2 and most of the Cb is a capacity value of a bootstrap feedback capacity, while a Cs is a gate stray capacity. The 2nd term of the right side shows an instantaneously rising amount of a gate voltage due to the capacity division in correspondence to a rise of the input pulse BT, and the rising amount is substantially different from the value of the VGO.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to peripheral circuits of semiconductor memories, more specifically,
The present invention relates to a semiconductor memory circuit having a circuit that selectively increases the voltage of a data line, which causes a minute potential change depending on the stored information when reading stored information in a memory cell, in accordance with the changed voltage.

[Background of the invention]

Conventionally, as a peripheral circuit of this type of semiconductor memory, the first
A circuit using a high-sensitivity sense amplifier SA made up of a flip-flop made up of two inverters as shown in the figure has been proposed. Examples of this are U.S. Pat.
It is described in the publication No. 00,609. The operation of this circuit is as follows.

Normally, the precharge signal O8 is at a high level until just before the start of operation, and the two electrically balanced digit sense lines D are both precharged to a high level. Digit sense line.

Assume that the memory cell connected to D is selected and, for example, the sense line is at a high level and the sense line is at a low level (at this time, the precharge signal C8 is at a low level). In this state, when the set signal SET is applied, positive feedback is applied to both inverters constituting the sense amplifier SA, and the voltage on the digit sense line rapidly drops to Ov. The voltage of the sense line is
At first, the voltage drops to the extent that the sense line is precharged to a high level, but when the sense line becomes O
In response to the voltage settling at v, the voltage settles to a voltage higher than the threshold voltage. FIG. 2 shows the relationship between the voltage of both digit sense lines D and the set signal SET. Here, vl represents a voltage on the high level side, and vO represents a voltage on the low level side.

By the way, in order to operate at higher speed using this conventional circuit, as shown in FIG. 2, the #171.
, it□n, the set signal SET must be turned on when the voltage difference between it and n is small. However, in FIG. 2, the voltage drop on the high level vl side of the digit sense line voltage after setting is more significant in 5ETI than in 5ET2. Normally, the gates of the transistors are connected to both sense lines in order to extract this digit sense line voltage to the outside.

Therefore, if the voltage of the digit sense line is significantly reduced, the gate voltage of this transistor will be reduced, the ability to drive an external load will be reduced, and there will be a limit to how high the speed can be increased. FIG. 3 shows the relationship between the digit sense line voltage on the high level vI side after setting and the setting time t. Here, vth is a threshold voltage.

[Purpose of the invention]

The present invention provides the above-mentioned conventional digit sense line D',
It is possible to selectively boost the voltage of a data line, such as D', which shows a minute potential change depending on the memory status of the memory cell, and thereby make the read voltage of the memory have a large amplitude. purpose.

Another object of the present invention is to reduce the load capacity when driving;
The purpose is to operate at high speed and increase the voltage boost.

[Summary of the invention]

The present invention provides a sense (data) in which a read voltage of a memory cell appears at one end of a variable capacitance element that has a capacitance when a voltage across a predetermined voltage is a predetermined threshold voltage or more, and has no capacitance below the threshold voltage. line and drives the other end to selectively boost the voltage of the sense (data) line in accordance with the read voltage.

Furthermore, the present invention divides the sense line to separate the load (5 parasitic) capacitance of the sense line from the sense amplifier and the bootstrap circuit.

[Embodiments of the invention]

The present invention provides a semiconductor memory peripheral circuit that eliminates such a drop in digit sense line voltage and enables higher-speed operation. It is characterized by a combination of circuits. Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

Embodiment 1 FIG. 4 shows an embodiment of the present invention, in which Q□lQ2 is a transistor constituting a bootstrap circuit, C0b is a bootstrap feedback capacitor, and BT is an input pulse to the bootstrap circuit. After precharging each node with precharge signal C8, when chip select signal O8 and sense gate signal SGI are applied, memory array M
The storage contents of the desired area in A are read out, and a voltage difference appears on the digit sense lines D', D', D, and D.

SGI goes high long enough for a voltage difference to appear and transistors Q5. The first and second sense lines are connected via QB. After the information is read, the first sense line is disconnected to increase the speed of the sense amplifier (FIG. 5). At this point, if you turn on the set signal and operate the sense amplifier SA, as explained in Figure 1,
The sense line voltage on the low level side drops to Ov, and the other sense line voltage is always set and held at a voltage equal to or higher than the threshold voltage Vth due to its operating principle.

Next, it is detected that either the digit sense line or D becomes Ov, and the set signal is turned off. The operation so far is the same as in the conventional circuit.

Now, in FIG. 4, a Pootstrap circuit is connected to the digit sense line D. The transistor immediately after the pulse input is applied to this Pootstrap circuit.
The gate voltage VO of Q□tQz is expressed by the following equation.

Here, Voo is the initial gate voltage, vDD is the drain voltage, and in the case shown, VOO corresponds to the voltage on the digit sense line, D, and VDD corresponds to the amplitude of the input pulses B and T of the Pootstrap circuit. . Further, C is the coupling capacitance between the gate and drain of the transistor Q□ or Q2, and most of it is the capacitance value of the bootstrap feedback capacitance mentioned above. C8 is the gate stray capacitance. The second term on the right side of equation (1) indicates the instantaneous increase in gate voltage due to capacitance division in response to the rising edge of input pulse BT, and this increase is V. It varies greatly depending on the value of 0. That is, V
When oo>Vth, an inversion layer is formed on the surface of the semiconductor substrate facing the gate of the transistor and the electrode connected to it, and is connected to the drain of the transistor, so the value of C can be compared with the value of C8. Since it becomes a large value, vo increases greatly. On the other hand, when Voo<Vth, there is no inversion layer facing the gate and electrode, and therefore the value of Ck is very small;
) The second term on the right side of the equation is small, and V'G hardly changes. That is, the gate voltage is selectively boosted by a variable capacitor whose capacitance value depends on the potential on the gate side of the transistor.

In this case, disconnection transistor Q5. Although it is possible to operate as a memory circuit without using Q6, since the parasitic capacitance within the memory array is added to C6, the voltage to be boosted will be reduced. Furthermore, as the parasitic capacitance increases, the driving of the sense amplifier becomes slower.

Now, in Fig. 4, the configuration is such that when it is detected that the set signal of the sense amplifier SA is turned off, the input pulse BT is applied to the Pootstrap circuit, and the Pootstrap circuit starts operating. do. At this time,
The voltage of the digit sense line having a voltage higher than the threshold voltage Vth is effectively activated by the capacitor C1) and rapidly becomes higher than the power supply voltage VDD, and the output VO or VO
A high voltage is generated at high speed. The other digit sense line voltage, which has a voltage of Ov, remains at Ov even when pulse BT is applied. From the above, the drop in level due to the setting of the sense amplifier is completely eliminated at the output of the final stage, making it possible to speed up the peripheral circuitry. FIG. 5 shows the operation timing of FIG. 4. Here, the dotted line is the operating waveform when the Pootstrap circuit is not used.

Embodiment 2 FIG. 6 shows another embodiment of the present invention. In order to reduce the capacitance C in Figure 4, gate transistors Q31 and Q4 are further provided, and the capacitance C8 here is the 4th transistor.
Since it is smaller than CS in the figure, the bootstrap feedback capacitance Ck required to obtain a predetermined gate voltage can be small, and the chip occupation area can be made smaller. That is, in this embodiment, when the sense amplifier operates, the first sense line D'.

The parasitic capacitance of the memory cell portion parasitic to D' and the parasitic capacitance of the bootstrap circuit parasitic to the third sense lines D'' and D' are eliminated, allowing even higher speed operation.

Further, when the bootstrap circuit operates, the parasitic capacitance of the sense amplifier section and the parasitic capacitance of the memory cell section parasitic to the second sense line D are eliminated, making it possible to boost the voltage more effectively. The timing relationship is shown in FIG. 7 and FIG. 6.

As described above, according to the present invention, by combining a conventional sense amplifier and a bootstrap circuit, it is possible to eliminate a drop in the voltage level of the digit sense line after the sense amplifier is set, and to provide a high-speed memory. I can do it.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to selectively boost the read signal of a memory cell, which has only a small voltage change, by simply driving it with a high pulse voltage. It can be done.

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional high-sensitivity sense amplifier, Figure 2 is a diagram showing the relationship between the set signal in Figure 1 and the digit sense line voltage, and Figure 3 is a diagram showing the time to apply the set signal and the time after the set signal is applied. FIG. 4 is a diagram showing the relationship between the digit sense line voltage on the high level side and FIG. 5 is a diagram showing the operating timing of FIG. 4, FIG. 6 is a diagram showing another embodiment of the present invention using an effective bootstrap circuit, and FIG. 7 is a diagram showing the operating timing of FIG. 5. It is. ■DD...Power supply voltage, SET, SET'l. 5ET2...Set signal, S'A...
Sense amplifier, O8... Precharge signal, C
8...Chip seredigit sense line, vi
, vo...... High level and low level sense line voltage after setting the sense amplifier, t... Time from O8, v th...... Transistor threshold voltage, MA. ...Memory array, SGI
, SG2...Sense gate signal, cB, cl,
Cso...load capacitance, Cwa...bootstrap feedback capacitance, Vo, Vo...output voltage,'BT...bootstrap circuit input pulse, Q1tQ2・・・・・・Transistor of bootstrap circuit, Q 3. Q4. Q s ,'Q E+...
...Sense gate transistor to make the bootstrap circuit work effectively.萬/圀A 2nd pattern O 躬 3 4th evil 5th day Otsuka 7th

Claims (1)

[Scope of Claims] 1. A memory array in which a plurality of memory cells are arranged, a plurality of first sense lines to which the memory cells are connected, and a first sense line corresponding to the first sense line; In a semiconductor memory circuit in which a second sense line having the same information as the sense line is provided via a switching means, the second sense line voltage has a capacitance above a predetermined threshold voltage, and the second sense line has a capacitance above a predetermined threshold voltage; When the read voltage of the memory cell is not reached, the first terminal of the variable capacitance element having substantially no capacitance is connected, and the second terminal of the variable capacitance element is driven to cause the read voltage of the memory cell to appear on the second sense line. A semiconductor memory circuit characterized in that the voltage is selectively increased according to the applied voltage.