JPS61171127A - Plasma etching method - Google Patents
Plasma etching methodInfo
- Publication number
- JPS61171127A JPS61171127A JP1080785A JP1080785A JPS61171127A JP S61171127 A JPS61171127 A JP S61171127A JP 1080785 A JP1080785 A JP 1080785A JP 1080785 A JP1080785 A JP 1080785A JP S61171127 A JPS61171127 A JP S61171127A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- processing
- gas supply
- wafer
- supply pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000001020 plasma etching Methods 0.000 title claims description 5
- 239000000203 mixture Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 abstract description 19
- 239000006185 dispersion Substances 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 61
- 239000011799 hole material Substances 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、プラズマエツチング方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a plasma etching method.
処理ガスをプラズマ化して該プラズマにより試料の被処
理面をエツチング処理する技術としては、サセプタに載
置された各ウェハに対する反応ガスの関係を一様にする
ことで、プラズマ処理のバラツキを減少させるものが知
られている。（特開昭５７−１２１２３４号〜１２１２
３６号公報）しかし、このような技術では、試料の被処
理面に対応する処理ガスの組成比を調節することで。As a technique for converting processing gas into plasma and etching the surface of the sample to be processed using the plasma, variations in plasma processing are reduced by making the relationship of reaction gas uniform for each wafer placed on a susceptor. something is known. (Unexamined Japanese Patent Publication No. 57-121234-1212
However, in such a technique, by adjusting the composition ratio of the processing gas corresponding to the surface to be processed of the sample.
試料のエツチング処理の均一性を向上させるといった認
識を有していない。There is no recognition that the uniformity of the etching process on the sample can be improved.
本発明の目的は、試料の被処理面に対応する処理ガスの
組成比を調節して試料の被処理面内の各位置での二雫チ
ング速度の均一性を向上させることで、試料のエツチン
グ処理の均一性を向上できるプラズマエツチング方法を
提供することにある。An object of the present invention is to improve the uniformity of the two-drop etching rate at each position on the surface of the sample by adjusting the composition ratio of the processing gas corresponding to the surface of the sample to be processed. An object of the present invention is to provide a plasma etching method that can improve the uniformity of processing.
本発明は、試料の被処理−に対応する処理ガスの組成比
を調節し、組成比を調節された前記処理ガスをプラズマ
化して該プラズマにより前記試料の被処理面をエツチン
グ処理することを特徴とするもので、試料の被処理面内
の各位置でのエツチング速度の均一性を向上させようと
するものである。The present invention is characterized in that the composition ratio of the processing gas corresponding to the sample to be processed is adjusted, the processing gas with the adjusted composition ratio is turned into plasma, and the processing target surface of the sample is etched by the plasma. This is intended to improve the uniformity of the etching rate at each position within the surface of the sample to be processed.
本発明の一実施例を第１図〜第４図により説明する。 An embodiment of the present invention will be described with reference to FIGS. 1 to 4.
第１図、第２図で、処理室１０には、対向電極Ｉと試料
電極（資）とが、この場合、上下方向に対向して平行に
内股されている。処理室ｌＯＯ頂壁中央部には、電極軸
４が下端部を処理室１０内に突出し処理室１０と電気的
に絶縁されて設けられている。電極軸乙の下端には、対
向電極加が略平行に設けられている。対向電極田には、
試料電極（９）に載置された試料、例えば、半導体素子
基板（以下、ウェハと略）の被処理面の中央部に対応し
て開口するガス放出孔ｎが穿設され、ガス放出孔ｎと連
通してガス分散室りが形成されている。電極軸乙には、
ガス分散室田と連通してガス供給略々が形成されている
。電極軸４には、ガス供給略々と連通してガス供給管４
０ａの一端が連結され、ガス供給管荀ａの他端は、処理
ガス源４１ ａに連結されている。In FIGS. 1 and 2, in the processing chamber 10, a counter electrode I and a sample electrode (material) are arranged in parallel to each other, facing each other in the vertical direction. An electrode shaft 4 is provided at the center of the top wall of the processing chamber lOO, with its lower end protruding into the processing chamber 10 and electrically insulated from the processing chamber 10. At the lower end of the electrode shaft B, counter electrodes are provided substantially parallel to each other. In the counter electrode field,
A gas release hole n is formed corresponding to the center of the surface to be processed of a sample placed on the sample electrode (9), such as a semiconductor element substrate (hereinafter referred to as a wafer). A gas distribution chamber is formed in communication with the gas distribution chamber. For the electrode shaft B,
A gas supply line is generally formed in communication with the gas distribution room. A gas supply pipe 4 is connected to the electrode shaft 4 and is connected to the gas supply pipe 4.
One end of the gas supply pipe 0a is connected to the gas supply pipe 41a, and the other end of the gas supply pipe 41a is connected to a processing gas source 41a.
ガス供給管４０ａの途中には、ガス流量制御装置Ｉ（以
下、ＭＦＣと略）４２ａが設けられている。電極軸４は
アースされている。ガス供給管４０ａのＭＰ’Ｃ４２ａ
の後流側には、ガス供給管４０ｂの一端が連結され、ガ
ス供給管４０ｂの他端は、処理ガス源４１ｂに連結され
ている。ガス供給管４ｏｂの途中には、ＭＰＣ４２ｂが
設けられている。この場合、処理室１０の上部側壁に対
応し、かつ、その外側位置でガス分散管荀が環装されて
いる。ガス分散管Ｃと対応する処理室１０の側壁には、
処理室ｌＯ内と連通して円周上等間隔にてガス放出孔材
が穿設されている。ガス分散管Ｃとガス放出孔Ｕとは連
通している。ガス供給管４ｏｂのＭＦＣ４２ｂの前流側
でガス供給管４０ｃが分岐され、ガス供給管４０Ｃは、
ガス分散管招に連結されている。ガス供給管４０ｃの途
中には、Ｍ Ｆ Ｃ４２ｃが設けられている。処理室１
０の底壁中央部には、電極軸ｍが上端部を処理室ｌＯ内
に突出し処理室ｌＯと電気的に絶縁されて設けられてい
る。電極軸阻の上端には、試料電極（９）が試料載置面
を上面として略平行に設けられている。A gas flow rate control device I (hereinafter abbreviated as MFC) 42a is provided in the middle of the gas supply pipe 40a. The electrode shaft 4 is grounded. MP'C42a of gas supply pipe 40a
One end of the gas supply pipe 40b is connected to the downstream side, and the other end of the gas supply pipe 40b is connected to a processing gas source 41b. An MPC 42b is provided in the middle of the gas supply pipe 4ob. In this case, a gas dispersion tube is arranged around the upper side wall of the processing chamber 10 at a position outside of the upper side wall. On the side wall of the processing chamber 10 corresponding to the gas dispersion tube C,
Gas release holes are bored at equal intervals on the circumference so as to communicate with the inside of the processing chamber IO. The gas distribution tube C and the gas discharge hole U are in communication. The gas supply pipe 40c is branched on the upstream side of the MFC 42b of the gas supply pipe 4ob, and the gas supply pipe 40C is
Connected to the gas distribution pipe. An MFC 42c is provided in the middle of the gas supply pipe 40c. Processing room 1
An electrode shaft m is provided at the center of the bottom wall of 0, with its upper end protruding into the processing chamber 1O and electrically insulated from the processing chamber 1O. Sample electrodes (9) are provided at the upper end of the electrode axis in parallel with each other with the sample mounting surface as the upper surface.
電極軸五の下端は、電源である高周波電淑父に接
Ｊ続されている。高周波電源父は、アースされてい
る。なお、処理室ｌＯの下部側壁には排気ノズル１１が
設けられ、排気ノズルＨには、真空排気装置（図示省略
）が連結されている。The lower end of the electrode shaft 5 is connected to the high frequency electric power source.
J is continued. The high frequency power source is grounded. Note that an exhaust nozzle 11 is provided on the lower side wall of the processing chamber IO, and the exhaust nozzle H is connected to a vacuum exhaust device (not shown).
のウェハωが、この場合、１枚載置される。処理ガス源
４１ Ｍからの処理ガス、例えば、８Ｆ、は、ＭＦ０４
２ａで流量を制御され、処理ガス源４１ ｂからの処理
ガス、例えば、０２は、ＭＦＣ４２ｂで流量を制御され
る。ＭＦＣ４２ｂで流量制御された０２はガス供給管４
１）ｂを流通した後に、Ｍ Ｆ ０４２ ａで流量制御
されガス供給管４０ａを流通している８Ｆ、に合流され
る。この合流により生じた８Ｆ６＋０２はガス供給管４
０ａを流通した後にガス供給略々に供給される。ガス供
給略々に供給された８Ｆ６＋０２は、その後、ガス分散
室ｎに入り、ここで均一に分散されてガス放出孔ｎより
ウェハωの被処理面の中央部に向って放出される。一方
、処理ガス源４１ ｂからの処理ガスである０２は、Ｍ
ＦＣ４２ｃで流量を制御されガス供給管４０ｃを流通し
た後にガス分散管ぐに供給される。ガス分散管Ｃに供給
された０２は、その後、ガス放出孔材より処理室１０内
に放出される。この状態で、試料型極美には、高周波電
源間より高周波電力が印加される。これにより、対向電
極（９）との間でグロー放電が生じ処理ガスはプラズマ
化され該プラズマによりウェハωの被処理面は、エツチ
ング処理される。In this case, one wafer ω is placed. The processing gas from the processing gas source 41M, for example 8F, is MF04
The flow rate of the processing gas from the processing gas source 41b, for example 02, is controlled by the MFC 42b. 02 is the gas supply pipe 4 whose flow rate is controlled by MFC42b
1) After flowing through b, the flow rate is controlled by M F 042 a and the gas flows into 8F flowing through gas supply pipe 40a. 8F6+02 generated by this merging is the gas supply pipe 4.
After passing through 0a, the gas is supplied approximately. The gas 8F6+02 that has been roughly supplied then enters the gas dispersion chamber n, where it is uniformly dispersed and discharged from the gas discharge hole n toward the center of the surface to be processed of the wafer ω. On the other hand, the processing gas 02 from the processing gas source 41b is M
The flow rate is controlled by the FC 42c, and after flowing through the gas supply pipe 40c, it is supplied to the gas distribution pipe. 02 supplied to the gas dispersion tube C is then released into the processing chamber 10 from the gas release hole material. In this state, high frequency power is applied to the sample mold Gokumi from between the high frequency power sources. As a result, a glow discharge occurs between the counter electrode (9), the processing gas is turned into plasma, and the processing surface of the wafer ω is etched by the plasma.
第３図は、ウェハωの被処理面の中央部に向りて放出さ
れる８Ｆ６＋０．と処理室１０内に放出される０２との
流量比（０２／８Ｆ６＋０２ ）すなわちウェハωの被
処理面に対応する処理ガスの組成比と、ウェハ〇の被処
理面の中央部でのエツチング速度Ｖｌとウェハωの被処
理面の周辺部でのエツチング速度ｖ２との関係を表わし
たものである。第３図から各エツチング速度ｖｉｓ ｖ
２は、処理ガスの特定の組成比で最高値を有することが
わかる。FIG. 3 shows 8F6+0. and 02 discharged into the processing chamber 10 (02/8F6+02), that is, the composition ratio of the processing gas corresponding to the processing surface of wafer ω, and the etching rate Vl at the center of the processing surface of wafer 〇. This represents the relationship between the etching speed v2 at the periphery of the surface to be processed of the wafer ω. From Figure 3, each etching speed vis v
It can be seen that No. 2 has the highest value at a specific composition ratio of the processing gas.
第４図は、第３図における処理ガスの任意の組成比での
ウェハωの被処理面内のエツチング速度分布を示したも
のである。この場合、ウェハ〇の被処理面内のエツチン
グ速度ｖ３は、中央部で遅く周辺部に向うにつれて速畷
なる。FIG. 4 shows the etching rate distribution within the processing surface of the wafer ω at an arbitrary composition ratio of the processing gas shown in FIG. In this case, the etching speed v3 within the processing surface of wafer 0 is slow at the center and becomes faster toward the periphery.
第３図、第４図より、ウェハωの被処理面の中央部に向
つて放出されるＳＦｇ＋０２の流量を一定として処理室
１０内に放出される０２の流量を増減させる（ウェハω
の被処理面に対応する処理ガスの組成比を調節する）こ
とにより、ウェハωの被処理面内のエツチング速度は第
４図にｖ４＊ ｖ５ で示すようになり、ウェハωの
被処理面の中央部でのエツチング速度レベルで均一性が
向上する。また、処理室１０内に放出される０２の流量
を一定としてウェハωの被処理面の中央部に向って放出
されるＳＦｓ ＋ ０２の流量を増減させる（ウェハω
の被処理面に対応する処理ガスの組成比を調節する）こ
とにより、ウェハωの被処理面内のエツチング速度は第
４図にｖ６ｅ ｖ７ で示すようになり、ウェハωの
被処理面の周辺部でのエツチング速度レベルで均一性が
向上する。なお、この場合、その他の条件は、全て同一
条件である。3 and 4, the flow rate of SFg+02 discharged toward the center of the processing surface of the wafer ω is kept constant, and the flow rate of 02 discharged into the processing chamber 10 is increased or decreased (wafer ω
By adjusting the composition ratio of the processing gas corresponding to the surface to be processed of the wafer ω, the etching rate within the surface to be processed of the wafer ω becomes as shown by v4*v5 in FIG. Uniformity is improved at the etching speed level in the center. Further, while keeping the flow rate of 02 discharged into the processing chamber 10 constant, the flow rate of SFs + 02 discharged toward the center of the processing surface of the wafer ω is increased or decreased (wafer ω
By adjusting the composition ratio of the processing gas corresponding to the surface to be processed of the wafer ω, the etching rate within the surface to be processed of the wafer ω becomes as shown by v6e v7 in FIG. Uniformity is improved by increasing the etching speed level. In this case, all other conditions are the same.
本実施例では、ウェハの被処理面に対応する処理ガスの
組成比を調節してウェハの被処理面内の各位置でのエツ
チング速度の均一性を向上でき、ウェハのエツチング処
理の均一性を向上させることができる。In this example, by adjusting the composition ratio of the processing gas corresponding to the surface to be processed of the wafer, the uniformity of the etching rate at each position within the surface to be processed of the wafer can be improved, and the uniformity of the etching process of the wafer can be improved. can be improved.
本発明は、以上説明したように、試料の被処理面に対応
する処理ガスの組成比を調節して試料の被処理面内の各
位置でのエツチング速度の均一性を向上できるので、試
料のエツチング処理の均一性を向上できるという効果が
ある。As explained above, the present invention can improve the uniformity of the etching rate at each position on the surface of the sample by adjusting the composition ratio of the processing gas corresponding to the surface of the sample to be processed. This has the effect of improving the uniformity of the etching process.
第１図は、本発明を実施したプラズマエツチング装置の
一例を示す処理室部の縦断面図、第２図は、第１図のＡ
−Ａ断面図、第３因は、０２／８Ｆ。
＋０２とつ、への被処理面の中央部並びに周辺部でのエ
ツチング速度との関係模式図、第４図は、ウェハ中心か
らの半径方向距離とエツチング速度との関係模式図であ
る。
ｎ、４４・・・・・・ガス放出孔、４１ ａ ｅ ４１
ｂ・・・・・・処理ガス源、４２ａ４いＬ／ ４２
ｃ −−−−−−Ｍ Ｆ Ｃ、６０＝つ８７、
Ｊ代理人 弁理士 小 川 勝 男、／−ゝ
・゛（
才２図
才３図
十４図FIG. 1 is a longitudinal sectional view of a processing chamber showing an example of a plasma etching apparatus embodying the present invention, and FIG.
-A sectional view, the third factor is 02/8F. FIG. 4 is a schematic diagram of the relationship between the radial distance from the wafer center and the etching rate. n, 44... Gas release hole, 41 a e 41
b...Processing gas source, 42a4L/42
c --------M F C, 60=tsu87,
J Agent Patent Attorney Katsuo Ogawa, /-ゝ・゛( Years 2, 3, 14
Claims (1)
し、組成比を調節された前記処理ガスをプラズマ化して
該プラズマにより前記試料の被処理面をエッチング処理
することを特徴とするプラズマエッチング方法。1. The method is characterized in that the composition ratio of a processing gas corresponding to the surface to be processed of the sample is adjusted, the processing gas with the adjusted composition ratio is turned into plasma, and the surface to be processed of the sample is etched by the plasma. Plasma etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1080785A JPS61171127A (en) | 1985-01-25 | 1985-01-25 | Plasma etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1080785A JPS61171127A (en) | 1985-01-25 | 1985-01-25 | Plasma etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61171127A true JPS61171127A (en) | 1986-08-01 |
Family
ID=11760611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1080785A Pending JPS61171127A (en) | 1985-01-25 | 1985-01-25 | Plasma etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61171127A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62250643A (en) * | 1986-04-24 | 1987-10-31 | Fuji Electric Co Ltd | Plasma etching method |
| JPH0536636A (en) * | 1991-07-31 | 1993-02-12 | Nec Yamagata Ltd | Dry etching equipment of semiconductor device |
| JP2001144069A (en) * | 1999-09-03 | 2001-05-25 | Ulvac Japan Ltd | Plasma etching apparatus for film-shaped substrate |
| US6737358B2 (en) * | 2002-02-13 | 2004-05-18 | Intel Corporation | Plasma etching uniformity control |
-
1985
- 1985-01-25 JP JP1080785A patent/JPS61171127A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62250643A (en) * | 1986-04-24 | 1987-10-31 | Fuji Electric Co Ltd | Plasma etching method |
| JPH0536636A (en) * | 1991-07-31 | 1993-02-12 | Nec Yamagata Ltd | Dry etching equipment of semiconductor device |
| JP2001144069A (en) * | 1999-09-03 | 2001-05-25 | Ulvac Japan Ltd | Plasma etching apparatus for film-shaped substrate |
| US6737358B2 (en) * | 2002-02-13 | 2004-05-18 | Intel Corporation | Plasma etching uniformity control |
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