JPS61170282A - Harmonic wave reducing method of 3-phase inverter - Google Patents
Harmonic wave reducing method of 3-phase inverterInfo
- Publication number
- JPS61170282A JPS61170282A JP60010411A JP1041185A JPS61170282A JP S61170282 A JPS61170282 A JP S61170282A JP 60010411 A JP60010411 A JP 60010411A JP 1041185 A JP1041185 A JP 1041185A JP S61170282 A JPS61170282 A JP S61170282A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- harmonic wave
- harmonic
- voltage
- quinary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、強制転流方式によるサイリスタスイッチ、自
己消弧機能をもつゲートクーンオフサイリスク（Ｇ’Ｌ
”０ ）やトランジスタ等のスイッチング素子により構
成さｆる電圧形インバータにおける高調波低減方法に関
するものでおる。Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a thyristor switch using a forced commutation method, and a Gate Kuhn-off thyristor switch (G'L) having a self-extinguishing function.
This invention relates to a method for reducing harmonics in a voltage source inverter constituted by switching elements such as "0" and transistors.
電圧形３相インバータの方形波出力電圧の中には数次の
高調波が含まれているが、このうちろ波が最も困離なも
のは第３および第５高調波であるとされている。The square wave output voltage of a voltage source three-phase inverter contains several harmonics, but it is said that the third and fifth harmonics are the most difficult to filter. .
従来、この第３および第５高調波を除去する方法として
、適当な位相差を持って運転する複数台のインバータを
多重に接続する方法や、コロナ社発行「インバータ回路
」 （奏泉寺、今井訳著）の２３１頁に示されているよ
うに、半周期中に２個所のスリットを設け、５個のパル
スでパルス幅変調（ＰＷＭ）する方法が一般的に用いら
ｆている。Conventionally, methods for removing the third and fifth harmonics include multiple connections of multiple inverters that operate with appropriate phase differences, and methods such as "Inverter Circuit" published by Corona Publishing Co., Ltd. (Sosenji, Imai). As shown on page 231 of the Japanese translation of the same book, generally used is a method in which two slits are provided in a half cycle and pulse width modulation (PWM) is performed using five pulses.
ところが、前者の方法によｆはスイッチング素子数が多
くなり、かつインバータトランスに千鳥結線を要する事
から回路構成が複雑となるという欠点があシ、後者では
、インバータ出力電圧周波数が高調波の場合、スイッチ
ング損失が犬となることやスリット間隔が狭いため、転
流時間が十分に確保でき欧くなるという欠点があった。However, the former method has the drawback that f requires a large number of switching elements and requires staggered wiring in the inverter transformer, making the circuit configuration complex. However, since the switching loss is small and the slit spacing is narrow, the commutation time cannot be secured sufficiently, which is disadvantageous.
本発明の目的は、簡単な構成で、かつスイッチング損失
も少なく、転流時間も十分に確保して第３次、第５次高
調波を除去し得る３相インバータの高調波低減方法を提
供することにある。An object of the present invention is to provide a harmonic reduction method for a three-phase inverter that has a simple configuration, has low switching loss, and can remove third and fifth harmonics by ensuring sufficient commutation time. There is a particular thing.
本発明は、半サイクルの間に３個のパルスを発生させて
直流電圧のパルス幅変調を行ない、かつ半サイクルの間
の特定位相に１つのスリットを設けるようにしたもので
ある。In the present invention, three pulses are generated during a half cycle to perform pulse width modulation of the DC voltage, and one slit is provided at a specific phase during the half cycle.
第１図は本発明を適用した３相インバータの一実施例を
示す回路図であり、直流電源１の出力電圧Ｅａｎ、Ｕ相
〜Ｗ相の各相の正および負の極性Ｕ、、’Ｕ、、Ｖ、、
Ｖｌｌ、Ｗ、、Ｗ、にそｎぞれ対応して設けらｎ、たス
イッチ２Ａ〜４Ｂが各相別に１２０度の位相差を持って
開閉さ扛ることにより、その開閉速度に応じた周波数の
３相方形波電圧に変換さ：ｎ−１出カドランス５を介し
てリアクトル６およびコンデンサから成る波形整形回路
に入力さｒ−１波形整形されて出力される。FIG. 1 is a circuit diagram showing an embodiment of a three-phase inverter to which the present invention is applied, in which the output voltage Ean of the DC power supply 1, the positive and negative polarities U, 'U ,,V,,
By opening and closing the switches 2A to 4B, which are provided corresponding to Vll, W, , W, with a phase difference of 120 degrees for each phase, a frequency corresponding to the opening/closing speed is set. It is converted into a three-phase rectangular wave voltage: input to a waveform shaping circuit consisting of a reactor 6 and a capacitor via an n-1 output transformer 5, and outputted after being shaped into an r-1 waveform.
本発明にこのようなインバータの構成において、各相の
スイッチ２八〜４Ｂを第２図（ａ）〜（ｄ）に示すよう
に（但し、Ｗ相は省略）、他相とラップする区間、すな
わちＶ相でいえは、（２π／３π）間にスリットを設け
、直流電圧Ｅｄの３パルスＰＷＭを行なって出力電圧を
制御するものである。そして、スリットの位相α１とα
２はα２＝２α１に設定し、図示のようにπ位相を対称
軸とする左右対称な出力電圧波形を取出し、Ｕ相と■相
の線間電圧Ｖ（Ｕ−Ｖｌを第２図（ｇ）に示すようなも
のとする。In the configuration of such an inverter according to the present invention, the switches 28 to 4B of each phase are arranged in sections that overlap with other phases, as shown in FIGS. That is, for the V phase, a slit is provided between (2π/3π), and three-pulse PWM of the DC voltage Ed is performed to control the output voltage. Then, the phases α1 and α of the slit are
2 is set to α2=2α1, and as shown in the figure, a symmetrical output voltage waveform with the π phase as the axis of symmetry is taken out, and the line voltage V (U-Vl of the U phase and ■ phase is calculated as shown in Figure 2 (g). It shall be as shown in .
この結果、制御角α１に対する高調波特性は第３図に示
すようなものとなり、α１＝１２．０度において第５高
調波ば０％、α１ ＝ ８．６度において第７高調波は
０％とすることができ、リアクトル６、コンデンサ７と
から成るフィルタによシ波形整形を行なううえでフィル
タの減衰率特性を−２０〔ｄＢ１０ＣＴ〕とｆｆｌは、
第５，７高調波を最小に減衰させ得る制御角α１は１１
．６度となる。この時の基本波電圧は、直流電源１の電
圧Ｅａに対して７４．８％となる。また各矢高調波電圧
は、３倍調波が０％、５次調波が１．２％、７次調波が
１Ｏ０２チ、１１次調波が２１チとなシ、通流角が１２
０度の方形波出力電圧の５次高調波２０チ、７次高調波
１４％に対し、第５調波の含有量を大きく低減でき、フ
ィルタによる波形整形が極めて容易になる。As a result, the harmonic characteristics for the control angle α1 are as shown in Figure 3, where the 5th harmonic is 0% at α1 = 12.0 degrees, and the 7th harmonic is 0% at α1 = 8.6 degrees. %, and when performing waveform shaping with a filter consisting of reactor 6 and capacitor 7, the attenuation rate characteristic of the filter is -20 [dB10CT] and ffl is:
The control angle α1 that can attenuate the 5th and 7th harmonics to the minimum is 11
．． It will be 6 degrees. The fundamental wave voltage at this time is 74.8% of the voltage Ea of the DC power supply 1. In addition, each arrow harmonic voltage is 0% for the 3rd harmonic, 1.2% for the 5th harmonic, 1002 cm for the 7th harmonic, 21 cm for the 11th harmonic, and 12% for the conduction angle.
Compared to 20% of the 5th harmonic and 14% of the 7th harmonic of the 0 degree square wave output voltage, the content of the 5th harmonic can be greatly reduced, and waveform shaping by a filter becomes extremely easy.
また、この方法によれば、スリット間隔α２−α１が１
１６度と大きく、高調波インバータにおいても十分な転
流時間を確保できるものとなる。Further, according to this method, the slit interval α2−α1 is 1
The angle is as large as 16 degrees, ensuring sufficient commutation time even in a harmonic inverter.
第４図は、本発明の他の実施例を示すタイムチャートで
あり、第２図と異なる点は、スリット位相を他相のラッ
プ区間（０−２ｎ／３）にしたものであり、第２図と同
様の出力波形を得ることができる。但し、出力電圧位相
は第２図の場合よシ制御角α１だけ遅れたものとなる。FIG. 4 is a time chart showing another embodiment of the present invention, and the difference from FIG. An output waveform similar to the one shown in the figure can be obtained. However, the output voltage phase is delayed by the control angle α1 compared to the case of FIG.
以上の説明から明らかなように本発明によれば、簡単な
構成で、かつスイッチング損失も少なく、転流時間も十
分に確保して第３次および第５次高調波を除去でき、波
形整形用のフィルタの小型化を促進できるなどの効果が
得られる。As is clear from the above description, according to the present invention, the third and fifth harmonics can be removed with a simple configuration, low switching loss, sufficient commutation time, and waveform shaping. Effects such as promoting miniaturization of the filter can be obtained.
第１図は本発明の一実施例を示す３相インバータの回路
図、第２図は本発明による方法の一実施例を示すタイム
チャート、第３図は第２図の実施例における高調波含有
率を示すグラフ、第４図は本発明による方法の他の実施
例を示すタイムチャートである。
１・・・直流電源、２八〜４Ｂ・・・スイッチ、５・・
・出カドランス、６・・・リアクトル、７・・・コンデ
ンサ。Fig. 1 is a circuit diagram of a three-phase inverter showing an embodiment of the present invention, Fig. 2 is a time chart showing an embodiment of the method according to the invention, and Fig. 3 is a harmonic content in the embodiment of Fig. 2. FIG. 4 is a time chart showing another embodiment of the method according to the invention. 1...DC power supply, 28-4B...switch, 5...
・Output transformer, 6...reactor, 7...capacitor.
Claims (1)
サイクルの間に３個のパルスを発生させて直流電圧のパ
ルス幅変調を行なうこと、各相交流出力の半サイクルの
間の特定位相に前記３個のパルスのうち１つで定まるス
リットを設けることを有して成る３相インバータの高調
波低減方法。 ２、スリットの位相角はｎ−α１〜ｎ−α２であり、α
１＝ｎ／６以下、α２＝２α１であることを特徴とする
特許請求の範囲第１項記載の３相インバータの高調波低
減方法。[Claims] 1. In a voltage-type three-phase inverter, three pulses are generated during a half cycle of a three-phase AC output to perform pulse width modulation of the DC voltage; a half cycle of each phase AC output; A method for reducing harmonics in a three-phase inverter, comprising providing a slit determined by one of the three pulses at a specific phase between the three pulses. 2. The phase angle of the slit is n-α1 to n-α2, and α
2. The harmonic reduction method for a three-phase inverter according to claim 1, wherein 1=n/6 or less and α2=2α1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010411A JPS61170282A (en) | 1985-01-23 | 1985-01-23 | Harmonic wave reducing method of 3-phase inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010411A JPS61170282A (en) | 1985-01-23 | 1985-01-23 | Harmonic wave reducing method of 3-phase inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61170282A true JPS61170282A (en) | 1986-07-31 |
Family
ID=11749400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60010411A Pending JPS61170282A (en) | 1985-01-23 | 1985-01-23 | Harmonic wave reducing method of 3-phase inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61170282A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100974619B1 (en) | 2003-09-15 | 2010-08-06 | 현대중공업 주식회사 | The suppresses system the overvoltage which is input in the electric motor to the inverter system that use filter design method and this |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091717A (en) * | 1973-12-18 | 1975-07-22 |
-
1985
- 1985-01-23 JP JP60010411A patent/JPS61170282A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091717A (en) * | 1973-12-18 | 1975-07-22 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100974619B1 (en) | 2003-09-15 | 2010-08-06 | 현대중공업 주식회사 | The suppresses system the overvoltage which is input in the electric motor to the inverter system that use filter design method and this |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Carrara et al. | A new multilevel PWM method: A theoretical analysis | |
| Mondal et al. | A neural-network-based space-vector PWM controller for a three-level voltage-fed inverter induction motor drive | |
| CN104298107B (en) | Combined local frequency multiplication sampling algorithm for generating SPWM waves | |
| Yun et al. | A new active zero state PWM algorithm for reducing the number of switchings | |
| Hariram et al. | Space vector switching patterns for different applications-a comparative analysis | |
| Bisoyi et al. | SHE PWM technique for three phase three level voltage source inverter | |
| Zuckerberger et al. | Determination of commutation sequence with a view to eliminating harmonics in microprocessor-controlled PWM voltage inverter | |
| JPS61170282A (en) | Harmonic wave reducing method of 3-phase inverter | |
| CN112803823A (en) | Pulse width modulation method, inverter and controller | |
| Uddin et al. | A single phase to single phase step-down cycloconverter for variable speed drive applications | |
| CN106655855A (en) | Frequency-doubling modulation method based on carrier lamination | |
| Khalil et al. | Harmonic Elimination of DC to AC converters using embedded design techniques | |
| Bowes et al. | Transputer-based optimal PWM control of inverter drives | |
| Bowes et al. | PWM switching strategies for current-fed inverter drives | |
| Patil et al. | FPGA implementation of SVPWM control technique for three phase induction motor drive using fixed point realization | |
| Jyothi et al. | Modeling and simulation of five phase induction motor fed with five phase inverter topologies | |
| Roy et al. | A Novel Approach for Space Vector Based PWM Algorithm for Diode Clamped Three level VSI Fed Induction Motor Drive | |
| Biswas | Study of Trapezoidal PWM on a 1ϕ AC-AC frequency converter | |
| Massoud et al. | Mapped phase-shifted space vector modulation for multi-level voltage-source inverters | |
| Janabi et al. | Real-time implementation of selective harmonic elimination with seamless dynamic performance | |
| Preethi et al. | Digital simulation of multicarrier PWM strategy for multi-level inverter | |
| Komolafe et al. | GAPPED ALTERNATE PHASED OPPOSITE DISPOSITION-PULSE WIDTH MODULATION CONTROL FOR MULTILEVEL INVERTERS | |
| Deb et al. | Analysis of pulse-fed power electronic circuits using Walsh function | |
| Nunna et al. | A single-phase simplified DC-AC converter using DC-link capacitors and an H-bridge | |
| GB1190847A (en) | Electric Inverting Apparatus |