JPS61167947A - Method for detecting end point of development - Google Patents

Method for detecting end point of development

Info

Publication number
JPS61167947A
JPS61167947A JP736585A JP736585A JPS61167947A JP S61167947 A JPS61167947 A JP S61167947A JP 736585 A JP736585 A JP 736585A JP 736585 A JP736585 A JP 736585A JP S61167947 A JPS61167947 A JP S61167947A
Authority
JP
Japan
Prior art keywords
development
end point
substrate
current
developing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP736585A
Other languages
Japanese (ja)
Other versions
JPH06103393B2 (en
Inventor
Kaoru Kanda
神田 薫
Kunihiko Kanda
神田 邦彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SIGMA GIJUTSU KOGYO KK
Original Assignee
SIGMA GIJUTSU KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SIGMA GIJUTSU KOGYO KK filed Critical SIGMA GIJUTSU KOGYO KK
Priority to JP60007365A priority Critical patent/JPH06103393B2/en
Priority to DE8585304867T priority patent/DE3581010D1/en
Priority to EP85304867A priority patent/EP0171195B1/en
Priority to US06/752,714 priority patent/US4621037A/en
Publication of JPS61167947A publication Critical patent/JPS61167947A/en
Publication of JPH06103393B2 publication Critical patent/JPH06103393B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/30Imagewise removal using liquid means

Abstract

PURPOSE:To facilitate detection of the end point of development by connecting the first conductor to a conductive layer through the resist of a substrate as one electrode, immersing the second conductor in a developing soln. as the other electrode, applying voltage between both electrodes, and watching the current. CONSTITUTION:The substrate 3, the conductor with 6, and the platinum wire 4 are immersed in the developing soln., and when voltage is applied from an electric cell 15 between the wire 4 as the positive electrode and the wire 6 as the negative electrode, current flows. The material of the conductor 6 to be connected with the conductive layer of the substrate 3 is made of a material same in kind as the material of the conductive layer in order to enhance detection accuracy. When the substrate 3 is immersed in the developing both and a starting switch is pushed, a timer is actuated to count time, and, e.g., at each second, a processing device 11 provided with a computer controller is interrupted and allowed to close the cell 15 for about 20mmsec and to measure the developing current. When the measured current increase rate drops remarkably compare with the value of a developing memory circuit 12, it is judged to reach the end point, thus permitting efficient optimum development and its automation to be attained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は現像の終点検出方法に係り、特に半導体装置の
製造の際に用いられるレジストの現像の終点を確実に検
出する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for detecting the end point of development, and more particularly to a method for reliably detecting the end point of resist development used in the manufacture of semiconductor devices.

従来の技術及び発明が解決しようとする問題点半導体装
置の製造の際に用いられるレジストパターンの現像は露
光部と未露光部の溶解度の差を利用して行なわれる。そ
の際レジストパターンの現像の終点は目視検査によって
主になされている。
Problems to be Solved by the Prior Art and the Invention The development of resist patterns used in the manufacture of semiconductor devices is carried out by utilizing the difference in solubility between exposed areas and unexposed areas. At this time, the end point of development of the resist pattern is mainly determined by visual inspection.

このような目視検査ではレジストパターンの微細化にと
もなって確実な現像の終点が得られなかった。
In such visual inspection, as the resist pattern becomes finer, a reliable end point of development cannot be obtained.

そこで本発明者らは電気的なホトレジスト現像の終点検
出方法に関して出願した(特願昭59−14−0551
号)。しかし半導体装置の製造方法におけるホトプロセ
スではホトレジストパターンの線幅は1〜2μmが限度
であり、将来サブミクロンのパターンの線幅を要する2
56にメモリ及びIM又は4Mビットメモリではホトプ
ロセスは使用し得す電子線描画法等を用いるプロセスを
必要とした。しかしながら解像度のよい電子線用ポジレ
ジストの場合、使用される現像液はイソプロピルアルコ
ール等を主成分とする有機溶剤であり前記出願方式によ
る方法では起電力が微小で終点検出は困難であった。
Therefore, the present inventors filed an application regarding a method for detecting the end point of electrical photoresist development (Japanese Patent Application No. 59-14-0551).
issue). However, in photoprocessing in the manufacturing method of semiconductor devices, the line width of photoresist patterns is limited to 1 to 2 μm, and in the future, line widths of submicron patterns will be required.
For 56-bit memory and IM or 4M bit memory, a process using electron beam lithography or the like was required, although photoprocessing could not be used. However, in the case of a positive electron beam resist with good resolution, the developer used is an organic solvent containing isopropyl alcohol or the like as a main component, and in the method according to the application method, the electromotive force was so small that it was difficult to detect the end point.

問題点を解決するための手段 上記問題点は本発明によれば基板上に形成された導体層
上にレジスト層を形成し、該レジスト層を所望のパター
ンに形成するために光またはX線露光しまたは電子線描
画し、次に該露光した基板の現像の終点検出方法におい
て: 前記光またはX線露光し、または電子線描画した基板の
レジストを通して該導体層に第1の導電材料からなる接
続手段を接続させて一方の電極となし、第2の導電材料
からなる物体を現像液に浸漬して他の電極となし、前記
二つの電極間に電圧を印加しその間に流れる電流を監視
することを特徴とする現像の終点検出方法によって解決
される。
Means for Solving the Problems According to the present invention, the above problems are solved by forming a resist layer on a conductor layer formed on a substrate, and exposing the resist layer to light or X-rays to form a desired pattern. In the method for detecting the end point of development of the exposed substrate after the exposed substrate is exposed to light or X-rays or exposed to electron beam, a connection made of a first conductive material is made to the conductive layer through the resist of the substrate exposed to light or X-rays or exposed to electron beam. Connecting the means to form one electrode, immersing an object made of a second conductive material in a developer to form the other electrode, applying a voltage between the two electrodes, and monitoring the current flowing between the two electrodes. This problem is solved by a method for detecting the end point of development, which is characterized by the following.

作用 本発明によれば、レジストを通して導体層に接続され、
一方の電極となる接続手段と他の電極との間に流れる電
流はレジスト現像の開始時は導体層が完全に非導体レジ
ストに覆われているのではVQであるがレジスト現像が
進み導体層が露出するにつれて徐々に増大し、電流変化
が最大となった時を現像(主現像)の終了とみなすこと
ができる。あるいはレベルが一定値に達した時に現像の
終了としてもよく、またピークに到達した時に現像の終
了としてもよい。
According to the present invention, the conductor layer is connected to the conductor layer through the resist,
The current flowing between the connecting means serving as one electrode and the other electrode is VQ when the conductive layer is completely covered with non-conductive resist at the start of resist development, but as the resist development progresses and the conductive layer The current gradually increases as the exposure progresses, and the time when the current change reaches its maximum can be regarded as the end of development (main development). Alternatively, development may end when the level reaches a certain value, or may end when the level reaches a peak.

実施例 以下、本発明の実施例を図面に基づいて説明する。Example Embodiments of the present invention will be described below based on the drawings.

第1図は本発明の詳細な説明するための一実施例を余す
模式図である。第2A図及び第2B図はレジストの現像
工程を示す概略断面図である。
FIG. 1 is a schematic diagram showing one embodiment for explaining the present invention in detail. FIGS. 2A and 2B are schematic cross-sectional views showing the resist development process.

第1図において、容器1内に例えばイソプロピルアルコ
ールを主成分とする現像液2が収納されており、該現像
液2内には、例えば3000人〜1μm厚の蒸着クロム
層(第2A、2B図で21)と該≠−→クロム層上に電
子線描画工程を完了した例えばポリメチルメタクリレ−
) (PMMA)の電子線用ポジ型レジスト(第2A図
において描画されたポジ型レジスト23、未描画ポジ型
レジスト22)とを配設した例えばガラスからなる基板
3及び白金線4が浸漬されている。
In FIG. 1, a developer 2 whose main component is, for example, isopropyl alcohol is stored in a container 1, and within the developer 2 is a vapor-deposited chromium layer (see FIGS. 2A and 2B) with a thickness of 3,000 to 1 μm, for example. 21) and the ≠-→ for example, polymethyl methacrylate which has undergone an electron beam drawing process on the chromium layer.
) (PMMA) for electron beams (the positive resist 23 drawn in FIG. 2A, the undrawn positive resist 22), a substrate 3 made of, for example, glass and a platinum wire 4 are immersed. There is.

基板3上の電子線描画部(第2A図、23)の現像液2
による現像の進行状態を監視するために、先端に保持具
5を設けたテフロン■被覆導線を基板3上のクロム層に
レジスト膜を破って接触させて一方の電極とし、白金線
4を他方の電極とする。
Developer 2 in the electron beam drawing section (FIG. 2A, 23) on the substrate 3
In order to monitor the progress of development, a Teflon coated conductive wire with a holder 5 at its tip was brought into contact with the chromium layer on the substrate 3 through the resist film as one electrode, and the platinum wire 4 was used as the other electrode. Use as an electrode.

該保持具5の先端はポジ型レジストを容易に破ることが
可能な力を加えることが出来る電極コネクタが好ましい
。導線6と白金線4のそれぞれの上方端にはビニールリ
ード線7a及び7bが接続され増幅器9につながる。更
にビニールリード線7a及び7bは抵抗8を介して接続
されている。
The tip of the holder 5 is preferably an electrode connector capable of applying a force capable of easily breaking the positive resist. Vinyl lead wires 7a and 7b are connected to the upper ends of the conducting wire 6 and the platinum wire 4, respectively, and lead to an amplifier 9. Furthermore, vinyl lead wires 7a and 7b are connected via a resistor 8.

第1図のように基板3と導線6及び白金線4を現像液2
内に浸漬し電池15を印加すると、白金線4を電極、導
線6を一極として電流が流れる。
As shown in Figure 1, the substrate 3, conductive wire 6, and platinum wire 4 are
When the battery 15 is immersed in the battery and the battery 15 is applied, a current flows with the platinum wire 4 as an electrode and the conducting wire 6 as one pole.

基板3上の導体層に接続させる導電材料は検出精度を上
げるために基板上に設けられた導体層と同種の材質の材
料であるのが好ましい。なぜならば該導電材料が導体層
と異種の材料の場合、基板3と接触させた材料が共に有
機溶剤の現像液の中に浸漬せしめられるので電離作用に
よりそこで電池の短絡回路が形成され、現像の正しい監
視が乱されるからである。接続材料が現像液に接触され
ないように例えばシュポン社製力ルレノッ等のフッ素ゴ
ム等で密閉されていれば異種導電材料でもよい。
The conductive material connected to the conductor layer on the substrate 3 is preferably the same type of material as the conductor layer provided on the substrate in order to improve detection accuracy. This is because when the conductive material is of a different type from the conductor layer, the materials in contact with the substrate 3 are both immersed in an organic solvent developer, and a short circuit is formed there due to ionization, causing the development to fail. This is because proper monitoring will be disrupted. A different type of conductive material may be used as long as the connecting material is sealed with fluororubber such as Shpon Co., Ltd., such as fluoro rubber so as not to come into contact with the developer.

基板3を現像槽1に浸漬して起動スイッチを押すとタイ
マが動作して時間計測を行い、例えば、1秒ごとに、演
算制御機能を備えた処理装置11に割り込む。処理装置
11は約20ミリ秒の間電池15を閉として現像電流を
測定する。現像による電流は抵抗6で電圧に変換して、
増幅器9で増幅され、ADコンバータ10を介して処理
装置11に入力され現像電流記憶回路12の値と比較さ
れる。処理装置11に入力された現像電流の電流上昇率
が増大傾向にある時には、新しく測定された電流値が現
像電流記憶回路12に記憶される。
When the substrate 3 is immersed in the developing tank 1 and a start switch is pressed, a timer is activated to measure time, and interrupts the processing device 11 equipped with an arithmetic control function every second, for example. The processing device 11 closes the battery 15 for about 20 milliseconds and measures the developing current. The current due to development is converted to voltage by resistor 6,
The signal is amplified by the amplifier 9, inputted to the processing device 11 via the AD converter 10, and compared with the value in the developing current storage circuit 12. When the rate of increase in the developing current input to the processing device 11 tends to increase, a newly measured current value is stored in the developing current storage circuit 12.

新しく測定された電流上昇率が前に測定された電流値即
ち、現像電流記憶回路12の値より著しく低下した時す
なわち電圧82時、(第3図のA点)に主現像の終点に
達したと判断する。更に現像を続はピークの電圧Eを過
ぎた点Bを追加現像の終点として現像の完了とすること
ができる。追加現像ファクタは追加現像ファクタ記憶回
路13で上記の例のように主現像終了時から所定の時間
を設定してもよく、又主現像に対する時間%で設定して
もよい、また、ピークを検出した時点を主現像の終点と
して更に追加現像を行うことによっても、本発明を実現
できることは明らかである。
The end point of main development was reached when the newly measured current increase rate became significantly lower than the previously measured current value, that is, the value in the developing current storage circuit 12, that is, when the voltage was 82 (point A in FIG. 3). I judge that. Furthermore, development can be completed by setting point B, which has passed the peak voltage E, as the end point of additional development. The additional development factor may be set in the additional development factor storage circuit 13 as a predetermined time from the end of the main development as in the above example, or may be set as a percentage of time with respect to the main development. It is clear that the present invention can also be realized by further performing additional development with the point in time as the end point of the main development.

なお図で14は現像終了を知らせるブザーあるいはタイ
マー等の機構である。
In the figure, 14 is a mechanism such as a buzzer or a timer that notifies the completion of development.

本実施例では基板3に相対する電極として白金線を用い
たが導電材料なら全て可能であり、更にレジスト層下の
導体材料としてクロム以外例えばモリブデン、又はタン
グステン等の他の金属あるいはシリコン、ICマスク等
でも勿論可能である。
In this example, a platinum wire was used as the electrode facing the substrate 3, but any conductive material is possible, and the conductive material under the resist layer may be other metals other than chromium, such as molybdenum or tungsten, silicon, or an IC mask. etc. is of course possible.

第4図は本発明の方法を実施するための現像容器の一実
施例を示した模式図である。
FIG. 4 is a schematic diagram showing an embodiment of a developing container for carrying out the method of the present invention.

第4図によれば、現像容器は外槽30、内槽31からな
り、内槽31内には現像液2が充たされ、該現像液2内
にキャリア32によって搬送される複数枚のマスク33
 (導電層及びレジスト層が形成されている)が浸漬さ
れている。該キャリア32は搬送機構34を介してモー
タ35と接続され、上下に揺動させることによって現像
効率を高めマスク上の均一性を向上させている。複数枚
のマスク33のうちの1つに、導線をマスクの金属膜で
あるクロムに接続するようにして接続されている。また
現像液2には1つの電極となる白金線4が第1図に示し
たと同様に浸漬され、該導線及び白金線は検出装置へ接
続される。現像液2aは内槽31の上部からオーバーフ
ローしポンプ36によって吸上げられ再び内槽31内に
その下部から供給することによって現像液2aを攪拌し
現像効率とマスクの現像の均一性を高めている。
According to FIG. 4, the developer container consists of an outer tank 30 and an inner tank 31, the inner tank 31 is filled with a developer 2, and a plurality of masks are conveyed by a carrier 32 into the developer 2. 33
(on which a conductive layer and a resist layer are formed) is immersed. The carrier 32 is connected to a motor 35 via a transport mechanism 34, and is swung up and down to increase development efficiency and improve uniformity on the mask. A conducting wire is connected to one of the plurality of masks 33 so as to be connected to chrome, which is a metal film of the mask. Further, a platinum wire 4 serving as one electrode is immersed in the developer 2 in the same manner as shown in FIG. 1, and the conducting wire and the platinum wire are connected to a detection device. The developer 2a overflows from the upper part of the inner tank 31, is sucked up by the pump 36, and is again supplied into the inner tank 31 from the lower part, thereby stirring the developer 2a and improving the developing efficiency and the uniformity of the mask development. .

発明の詳細 な説明したように、本発明の方法によって電気化学的に
現像状況が検出されるので再現性のにい且つ能率的な最
適現像および自動化が可能となる。更に本発明はICマ
スク水晶発振器、弾性表面波フィルタ等周波数の制御も
可能となる。
As described in detail, the method of the present invention allows for highly reproducible and efficient optimal development and automation because the development status is detected electrochemically. Furthermore, the present invention enables frequency control of IC mask crystal oscillators, surface acoustic wave filters, etc.

すなわち目視によらず電気化学的に終点を検出するので
再現性がよく、その後に行うエツチングを精度よく行う
ことができるので発振周波数のバラツキを小さくするこ
とができる。
That is, since the end point is detected electrochemically rather than visually, the reproducibility is good, and the subsequent etching can be performed with high precision, so that variations in the oscillation frequency can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の詳細な説明するための一実施例を示す
模式図であり、第2A図及び第2B図はレジストの現像
工程を示す概略断面図であり、第3図は現像時間と現像
電圧の関係を示すグラフであり、第4図は本発明の方法
を実施するための現像容器の一実施例を示した模式図で
ある。 1・・・容器、2・・・現像液、3・・・基板、4・・
・白金線、5・・・保持具、6・・・導線、7a、7b
・・・ビニールリ−ド線、8・・・抵抗、9・・・増幅
器、10・・・ADコンバータ、11・・・演算制御機
能を備えた処理装置、12・・・現像電流記憶回路、1
3・・・追加現像フ゛アクタ記憶回路、14・・・ブザ
ーあるいはタイマー、15・・・を池、16・・・起動
スイッチ、21・・・クロム層、22・・・ネガレジス
ト、 23・・・ネガレジスト(露光部)、30・・・
外槽、 31・・・内槽、32・・・キャリヤ、33・
・・マスク、34・・・搬送機構、35・・・モータ、
36・・・ポンプ。
FIG. 1 is a schematic diagram showing an example for explaining the present invention in detail, FIGS. 2A and 2B are schematic cross-sectional views showing the resist development process, and FIG. 4 is a graph showing the relationship between developing voltages, and FIG. 4 is a schematic diagram showing an embodiment of a developing container for carrying out the method of the present invention. 1... Container, 2... Developer, 3... Substrate, 4...
・Platinum wire, 5... Holder, 6... Conductor wire, 7a, 7b
. . . Vinyl lead wire, 8 . . . Resistor, 9 .
3... Additional development factor memory circuit, 14... Buzzer or timer, 15... Pond, 16... Starting switch, 21... Chrome layer, 22... Negative resist, 23... Negative resist (exposed area), 30...
Outer tank, 31... Inner tank, 32... Carrier, 33.
...Mask, 34...Transportation mechanism, 35...Motor,
36...Pump.

Claims (1)

【特許請求の範囲】 1、基板上に形成された導体層上にレジスト層を形成し
、該レジスト層を所望のパターンに形成するために光ま
たはX線露光し、または電子線描画し、次に該露光した
基板の現像の終点検出方法において; 前記光またはX線露光し、または電子線描画した基板の
レジストを通して該導体層に第1の導電材料からなる接
続手段を接続させて一方の電極となし、第2の導電材料
からなる物体を現像液に浸漬して他の電極となし、前記
二つの電極間に電圧を印加しその間に流れる電流を監視
することを特徴とする現像の終点検出方法。 2、前記第1の導電材料が前記導体層と同一の材料から
なることを特徴とする特許請求の範囲第1項記載の方法
。 3、前記接続手段が現像液に浸漬中核現像液に接触しな
いように被覆されることを特徴とする特許請求の範囲第
1項記載の方法。 4、前記二つの電極間に流れる電流の変化を検出して主
現像の終了点とし、更に追加現像ファクタに基づいて追
加現像を行ない該追加現像終了点を現像の終了点とする
ことを特徴とする特許請求の範囲第1項記載の方法。 5、前記主現像の終了点が、上昇電圧が規定値より小さ
くなる時点とすることを特徴とする特許請求の範囲第4
項記載の方法。 6、前記主現像の終了点が電圧の上昇率の低下する時点
とすることを特徴とする特許請求の範囲第4項記載の方
法。 7、前記電流の変化がピーク値であることを特徴とする
特許請求の範囲第4項記載の方法。 8、前記電流の変化が勾配最大点であることを特徴とす
る特許請求の範囲第4項記載の方法。 9、前記電流の監視を現像状態監視手段と追加現像ファ
クタ記憶手段と演算制御手段とを具備する手段を用いて
行なうことを特徴とする特許請求の範囲第1項記載の方
法。
[Claims] 1. A resist layer is formed on a conductor layer formed on a substrate, the resist layer is exposed to light or X-rays, or exposed to electron beams to form a desired pattern, and then In the method for detecting the end point of development of the substrate exposed to light, connecting means made of a first conductive material to the conductive layer through the resist of the substrate exposed to light or X-rays or drawn with electron beams to connect one electrode. Detecting the end point of development, characterized in that an object made of a second conductive material is immersed in a developer solution to serve as another electrode, a voltage is applied between the two electrodes, and a current flowing between the two electrodes is monitored. Method. 2. The method according to claim 1, wherein the first conductive material is made of the same material as the conductor layer. 3. A method according to claim 1, characterized in that the connecting means is immersed in a developer solution and coated so as not to come into contact with the core developer solution. 4. A change in the current flowing between the two electrodes is detected and determined as the end point of the main development, and further development is performed based on an additional development factor, and the end point of the additional development is determined as the end point of the development. A method according to claim 1. 5. Claim 4, characterized in that the end point of the main development is a point in time when the rising voltage becomes smaller than a specified value.
The method described in section. 6. The method according to claim 4, wherein the end point of the main development is set at a point in time when the rate of increase in voltage decreases. 7. The method according to claim 4, wherein the change in the current is a peak value. 8. The method according to claim 4, wherein the change in current is at a maximum slope point. 9. The method according to claim 1, wherein the current is monitored using means comprising a development state monitoring means, an additional development factor storage means, and an arithmetic control means.
JP60007365A 1984-07-09 1985-01-21 Development endpoint detection method Expired - Lifetime JPH06103393B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60007365A JPH06103393B2 (en) 1985-01-21 1985-01-21 Development endpoint detection method
DE8585304867T DE3581010D1 (en) 1984-07-09 1985-07-08 DEVELOPMENT END POINT PROCEDURE.
EP85304867A EP0171195B1 (en) 1984-07-09 1985-07-08 Method for detecting endpoint of development
US06/752,714 US4621037A (en) 1984-07-09 1985-07-08 Method for detecting endpoint of development

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60007365A JPH06103393B2 (en) 1985-01-21 1985-01-21 Development endpoint detection method

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JPS61167947A true JPS61167947A (en) 1986-07-29
JPH06103393B2 JPH06103393B2 (en) 1994-12-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62135838A (en) * 1985-08-19 1987-06-18 Toshiba Corp Method and apparatus for forming pattern
JPS63193151A (en) * 1987-02-06 1988-08-10 Toshiba Corp Automatic developing device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5036765A (en) * 1973-07-06 1975-04-07
JPS584143A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Developing method for positive resist film
JPS5842042A (en) * 1981-08-28 1983-03-11 ヘキスト・アクチエンゲゼルシヤフト Development for photosensitive copying layer exposed
JPS6120043A (en) * 1984-07-09 1986-01-28 Sigma Gijutsu Kogyo Kk Detection of end point of development

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5036765A (en) * 1973-07-06 1975-04-07
JPS584143A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Developing method for positive resist film
JPS5842042A (en) * 1981-08-28 1983-03-11 ヘキスト・アクチエンゲゼルシヤフト Development for photosensitive copying layer exposed
JPS6120043A (en) * 1984-07-09 1986-01-28 Sigma Gijutsu Kogyo Kk Detection of end point of development

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62135838A (en) * 1985-08-19 1987-06-18 Toshiba Corp Method and apparatus for forming pattern
JPS63193151A (en) * 1987-02-06 1988-08-10 Toshiba Corp Automatic developing device

Also Published As

Publication number Publication date
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