JPS61166228A - Overload compensation type digital-analog converting circuit - Google Patents

Overload compensation type digital-analog converting circuit

Info

Publication number
JPS61166228A
JPS61166228A JP585785A JP585785A JPS61166228A JP S61166228 A JPS61166228 A JP S61166228A JP 585785 A JP585785 A JP 585785A JP 585785 A JP585785 A JP 585785A JP S61166228 A JPS61166228 A JP S61166228A
Authority
JP
Japan
Prior art keywords
circuit
waveform
overload
analog
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP585785A
Other languages
Japanese (ja)
Inventor
Yukihiro Okada
行弘 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP585785A priority Critical patent/JPS61166228A/en
Publication of JPS61166228A publication Critical patent/JPS61166228A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid generation of overload noise by providing a synthesis circuit synthesizing an output of an analog converting circuit and an output of a narrow band low pass filter and making the delay time of both the synthesized outputs identical so as to reproduce an analog waveform. CONSTITUTION:An output of an analog converting circuit 2 has a waveform whose positive/negative peaks are clipped. A time delay of TAB is caused to an input signal at a point A. Then a time delay of TAC is caused to a signal at a point C to the input signal at the point A. The synthesis circuit 9 synthesizes signals B, C and the delay times of TAB, TAC are made identical so that both the phases are made coincident in this case. In matching analogical ly the phases, the phases, the phase of filters 5, 8 is adjusted or an attenuator ATT of the synthesis circuit 9 is adjusted. In matching the phases digitally, a delay adjusting circuit 11 is inserted to any one of digital transmission lines branched into two from a PCM signal processing circuit 1. When the TAB and TAC are identical, the waveform whose clip state is compensated is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ディジタルオーディオ機器などのPCM変調
方式の音声信号再生装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM modulation type audio signal reproducing device for digital audio equipment and the like.

〔従来の技術〕[Conventional technology]

ディジタルオーディオ機器などでは、PCM変調方式で
音声信号の録音・再生を行なっている。
In digital audio equipment, audio signals are recorded and played back using the PCM modulation method.

PCMデータを再生する場合は、通常、そのままD/A
変換を行ないアナログ信号を得ている。
When playing PCM data, normally the D/A
The conversion is performed to obtain an analog signal.

しかし、使用者が録音できるような機器、ディジタルオ
ーディオテープなとでは、使用者が録音レベル設定をな
し、太刀信号がA/D変換器の動作レインジに入るよう
に調節する。これは一般の使用者にとっては難しく、時
々量子化レベル範囲を超えるアナログ信号を録音し、再
生時にオーバーフロー雑音(過負荷雑音)が発生する。
However, in a device that allows the user to record, such as a digital audio tape, the user sets the recording level and adjusts the signal so that it falls within the operating range of the A/D converter. This is difficult for ordinary users, as they sometimes record analog signals that exceed the quantization level range, resulting in overflow noise (overload noise) during playback.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、上記の欠点を除去し、波形の一部が過
負荷状態でA/D変換された信号をアナログ変換すると
きに、正負のピーク値で波形が台形になった部分に、波
形的修正を加えて元の波形に近ずけ、過負荷雑音を除去
することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and when a part of the waveform is overloaded and a signal that has been A/D converted is converted into analog, the waveform becomes trapezoidal at the positive and negative peak values. The purpose is to modify the waveform to make it closer to the original waveform and remove overload noise.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のD/A変換回路は、D/A変換器・低域フィル
タによりアナログ波形に変換するアナログ変換回路と、
前記ディジタル信号の過負荷を検出し、その間一定出力
パルスを発生する過負荷検出回路と、前記一定出力パル
スを入力し定遅延を与える狭帯域低域フィルタと、前記
アナログ変換回路の出力と前記狭帯域低域フィルタの出
力とを合成する合成回路とを設け、前記の合成する再出
力の遅延時間を同一にすることによりアナログ波形を再
生するようにしたものである。
The D/A conversion circuit of the present invention includes an analog conversion circuit that converts into an analog waveform using a D/A converter and a low-pass filter;
an overload detection circuit that detects an overload of the digital signal and generates a constant output pulse during that time; a narrowband low-pass filter that inputs the constant output pulse and provides a constant delay; A synthesizing circuit for synthesizing the output of the low-pass filter is provided, and the analog waveform is reproduced by making the delay time of the synthesized re-output the same.

〔作用〕[Effect]

アナログ波をA/D変換するときに、量子化レベル範囲
を正・負において一部超えると、変換されたディジタル
信号はその範囲においてすべてのビットが”H″レベル
たは″L″レベルである状態がm続する。したがって再
生されたアナログ信号はクリップ波形になり、奇数次歪
成分が増大し、聴覚上質の低い音声になる。本発明では
、このクリップ波形の部分に、過負荷の時間間隔に相当
するパルス幅のパルス入力による狭帯域低域フィルタの
応答波形を重畳して、なだらかな波形としクリップ波形
を補正することで原波形に近似し、過負荷雑音が発生し
ないようにするものである。
When A/D converting an analog wave, if some of the positive and negative quantization level ranges are exceeded, all bits of the converted digital signal will be at "H" level or "L" level within that range. The state continues for m times. Therefore, the reproduced analog signal has a clipped waveform, the odd-order distortion components increase, and the audio quality is low. In the present invention, the response waveform of a narrow-band low-pass filter caused by a pulse input with a pulse width corresponding to the overload time interval is superimposed on the clipped waveform to create a gentle waveform and correct the clipped waveform. This approximates the waveform and prevents overload noise from occurring.

〔実施例〕〔Example〕

以下、図面を参照して本発明の一実施例の説明を行なう
。第1図は実施例の回路ブロック図であり、第2図に回
路の各点の信号を図示している。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of the embodiment, and FIG. 2 illustrates signals at each point of the circuit.

PCM信号回路1からのPCM信号が、本発明の過負荷
補償型D/A変換回路の入力であり、その正または負の
入力レベルの一部で過負荷状態でA/D変換されている
ものとする。このPCM信号はアナログ変換回路2を経
て、アナログ出力となり加算回路9のB点の信号となる
。アナログ変換回路2はD/A変換器3.アパーチャ回
路4゜低域フィルタ5からなり、通常のD/A変換回路
である。アナログ変換回路2の出力は第2図(B)に示
すようにその正・負のピークがクリップされた波形にな
る。またA点の入力信号に対しTANの時間遅れになる
The PCM signal from the PCM signal circuit 1 is an input to the overload compensation type D/A conversion circuit of the present invention, and is A/D converted in an overload state at a part of its positive or negative input level. shall be. This PCM signal passes through the analog converter circuit 2, becomes an analog output, and becomes a signal at point B of the adder circuit 9. The analog conversion circuit 2 includes a D/A converter 3. It consists of an aperture circuit 4° and a low-pass filter 5, and is a normal D/A conversion circuit. The output of the analog conversion circuit 2 has a waveform with its positive and negative peaks clipped, as shown in FIG. 2(B). Also, there is a time delay of TAN with respect to the input signal at point A.

一方、前記PCM信号は過負荷検出回路6に入力する。On the other hand, the PCM signal is input to the overload detection circuit 6.

正の入力レベルで過負荷であれば、すべてのビットが1
″であることを回路61で検出し、過負荷状態であるか
ぎりその間正のパルスを発生する。また負の入力レベル
で過負荷であればすべてのビットが“θ″であることを
回B62で検出しその間食のパルスを発生する。
If overloaded with a positive input level, all bits are 1.
'' is detected by circuit 61, and as long as there is an overload condition, a positive pulse is generated during that period.If the overload is at a negative input level, circuit B62 detects that all bits are ``θ''. It detects and generates intercalating pulses.

上記パルスは過負荷継続時間に比例するパルス幅をもつ
一定振幅のパルスでP点、N点の波形は第2図(P)、
  (N)に示すようになる。上記パルスはアナログ加
算回路7を介して狭帯域低域フィルタ8に入力する。こ
の狭帯域低域フィルタ8は直線位相性をもち一定の遅延
を与えるとともに狭帯域の特性を有し、第3図に示すよ
うなパルス応答特性を与えるものであればよい。例えば
第4図に示すようなcos”ロールオフあるいはガウス
波形などの特性フィルタが用いられる。したがって狭帯
域低域フィルタ8の出力は0点で第2図(C)の波形に
なる。振幅は合成回路9内の減衰器ATTで適宜設定で
きる。そしてA点の入力信号に対し0点の信号はTAc
の時間遅れになる。
The above pulse is a constant amplitude pulse with a pulse width proportional to the overload duration, and the waveforms at points P and N are shown in Figure 2 (P).
It becomes as shown in (N). The pulses are input to a narrow band low pass filter 8 via an analog adder circuit 7. The narrowband low-pass filter 8 may be of any type as long as it has linear phase characteristics, provides a constant delay, has narrowband characteristics, and provides pulse response characteristics as shown in FIG. For example, a characteristic filter such as a cos'' roll-off or a Gaussian waveform as shown in FIG. It can be set appropriately with the attenuator ATT in the circuit 9.Then, the signal at point 0 with respect to the input signal at point A is TAc.
There will be a time delay.

合成回路9で信号B、倍信号とを合成するが、その際、
両者の位相が一致するように、TAR。
The synthesis circuit 9 synthesizes the signal B and the doubled signal, but at this time,
TAR so that both phases match.

T’Acの遅延時間を同一にする。それにはアナログ的
に位相を合わせる場合は、各フィルタ5.8の位相を調
節したり、あるいは合成回路9の減衰器ATTの部分で
行なう。ディジタル的に位相を合わせるにはPCM信号
処理回路1からの2分岐するディジタル伝送路のいずれ
か1つに遅延調節回路11を挿入することによって行な
う。
Make the delay time of T'Ac the same. If the phase is to be matched in an analog manner, the phase of each filter 5.8 is adjusted, or the attenuator ATT of the synthesis circuit 9 is used. Digitally matching the phase is achieved by inserting a delay adjustment circuit 11 into one of the two branched digital transmission lines from the PCM signal processing circuit 1.

TAll、TAcが同一であれば、第2図(B)のアナ
ログ変換回路2の出力のクリップされた部分に、第2図
(C)の波形が重畳し、同図(D)の波形となり、クリ
ップ状態が補償された波形を得ることができる。低域フ
ィルタ10は上記合成過程で少し位相ずれがあった場合
にも、波形がなだらかにするためのものである。
If TAll and TAc are the same, the waveform in FIG. 2(C) is superimposed on the clipped part of the output of the analog conversion circuit 2 in FIG. 2(B), resulting in the waveform in FIG. 2(D), A waveform whose clipping state is compensated for can be obtained. The low-pass filter 10 is used to smooth the waveform even if there is a slight phase shift during the synthesis process.

〔発明の効果〕〔Effect of the invention〕

以上、詳しく説明したように、PCM録音の際、量子化
レベルを超えるような信号に対しても、そのままD/A
変換すればクリップされた波形になるところを、その部
分にクリップされた期間の時間幅をもつパルスの低域フ
ィルタ応答波を重畳して補償することで、クリップによ
る奇数次歪成分を減少できる。したがって過負荷の場合
にも、聴感特性を著しく改善することができる。本発明
は原波形の完全な再生ではないが、過負荷はしばしば発
生するものでないため、上記のような補償回路で十分に
対応できる。
As explained in detail above, during PCM recording, even signals that exceed the quantization level can be directly D/A
If the conversion results in a clipped waveform, the odd-order distortion components due to clipping can be reduced by superimposing a low-pass filter response wave of a pulse having the time width of the clipped period on that portion to compensate. Therefore, even in the case of overload, the auditory characteristics can be significantly improved. Although the present invention does not completely reproduce the original waveform, since overload does not occur often, a compensation circuit such as the one described above can sufficiently cope with the problem.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路ブロック図、第2図は
第1図の各点の波形、第3図、第4図は狭帯域低域フィ
ルタの特性を示す図である。 1−P CM信号処理回路、2−アナログ変換回路、3
−D/A変換器、 4−アパーチャ回路、5−低域フィ
ルタ、 6−過負荷検出回路、8−狭帯域低域フィルタ
、 9−合成回路、1〇−低域フィルタ。 実用新案登録出願人 日本電気ホームエレクトロニクス株式会社代理人   
弁理士   佐藤秋比古 乞2図 L3図
FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is a waveform at each point in FIG. 1, and FIGS. 3 and 4 are diagrams showing characteristics of a narrow band low-pass filter. 1-P CM signal processing circuit, 2-analog conversion circuit, 3
-D/A converter, 4-aperture circuit, 5-low-pass filter, 6-overload detection circuit, 8-narrowband low-pass filter, 9-synthesizing circuit, 10-low-pass filter. Agent for utility model registration applicant NEC Home Electronics Co., Ltd.
Patent Attorney Akihiko Sato Figure 2 L3

Claims (1)

【特許請求の範囲】[Claims] アナログ波形の1部が過負荷状態でA/D変換されたデ
ィジタル信号について、前記ディジタル信号を入力し、
D/A変換器・低域フィルタによりアナログ波形に変換
するアナログ変換回路と、前記ディジタル信号の過負荷
を検出し、その間一定出力パルスを発生する過負荷検出
回路と、前記一定出力パルスを入力し定遅延を与える狭
帯域低域フィルタと、前記アナログ変換回路の出力と前
記狭帯域低域フィルタの出力とを合成する合成回路とを
設け、前記の合成する両出力の遅延時間を同一にするこ
とによりアナログ波形を再生することを特徴とする過負
荷補償型D/A変換回路。
Regarding a digital signal in which a part of the analog waveform is A/D converted in an overload state, inputting the digital signal,
an analog conversion circuit that converts the digital signal into an analog waveform using a D/A converter/low-pass filter; an overload detection circuit that detects an overload of the digital signal and generates a constant output pulse during that time; and an overload detection circuit that inputs the constant output pulse. A narrowband low-pass filter that provides a constant delay and a synthesis circuit that synthesizes the output of the analog conversion circuit and the output of the narrowband low-pass filter are provided, and the delay time of both outputs to be synthesized is made the same. An overload compensation type D/A conversion circuit characterized by reproducing an analog waveform.
JP585785A 1985-01-18 1985-01-18 Overload compensation type digital-analog converting circuit Pending JPS61166228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP585785A JPS61166228A (en) 1985-01-18 1985-01-18 Overload compensation type digital-analog converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP585785A JPS61166228A (en) 1985-01-18 1985-01-18 Overload compensation type digital-analog converting circuit

Publications (1)

Publication Number Publication Date
JPS61166228A true JPS61166228A (en) 1986-07-26

Family

ID=11622645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP585785A Pending JPS61166228A (en) 1985-01-18 1985-01-18 Overload compensation type digital-analog converting circuit

Country Status (1)

Country Link
JP (1) JPS61166228A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142934A (en) * 1993-11-18 1995-06-02 Japan Radio Co Ltd Waveform distortion compensation method and method and circuit for amplitude modulation using it
JP2010518324A (en) * 2007-02-01 2010-05-27 シャエフラー カーゲー Bearing structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142934A (en) * 1993-11-18 1995-06-02 Japan Radio Co Ltd Waveform distortion compensation method and method and circuit for amplitude modulation using it
JP2010518324A (en) * 2007-02-01 2010-05-27 シャエフラー カーゲー Bearing structure

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