JPS61166039A - Dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To obtain a less curved substrate by reducing the alternate lamination pitch of a silicon polycrystalline layer and a silicon oxide film (one example) at near the last silicon polycrystalline layer than the pitch of the other part. CONSTITUTION:An isolation groove 2 is formed in a lattice state. Then, a silicon oxide film 3 is formed on an upper main surface. The silicon oxide film 3 is used as a dielectric film. The alternate lamination of a silicon polycrystalline layer and the silicon oxide film is formed as a support region on the silicon oxide film 3. In this case, the silicon polycrystalline layers 4a-4h counting from the silicon oxide film 3 to the eighty layer are made thicker than the other silicon polycrystalline layers 4i-4k. One example is that the silicon polycrystalline layers 4a-4h are each approx. 50mum and the silicon polycrystalline layers 4i-4k are each approx. 10mum. Each silicon oxide film 5 is made the same thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dielectric insulating isolation substrate, and particularly to a substrate structure that does not cause curvature in the substrate itself during the manufacture of semiconductor integrated circuits using the substrate.

A dielectric insulating isolation substrate has a structure in which multiple silicon single crystal island regions are supported via a dielectric insulating film in a support region, and has high breakdown voltage and small parasitic capacitance. It has been widely used since.

Due to the difference in thermal expansion coefficients between the support region and the silicon monocrystalline island region, the manufactured substrates are often curved. If the substrate is curved, in order to manufacture semiconductor integrated circuits, photolithography technology is used to diffuse impurities into each silicon single crystal island region to form circuit elements, and each circuit element is connected with aluminum wiring. When connecting, the accuracy will be reduced and the degree of integration will be reduced. Furthermore, since it is curved, there is a problem that the substrate may break due to the pressing force applied during processing.

Generally, polycrystalline silicon is often used for the support region. Therefore, a manufacturing method was proposed in which the same applicant as the present application filed an application in which a silicon oxide film, for example, was interposed in the support region to compensate for the difference in thermal expansion coefficients (Japanese Patent Application No.
No. 625).

In this case, the final layer of the support region is preferably a silicon polycrystalline layer. The reason for this is that although the surface of this silicon polycrystalline layer has many irregularities, a horizontal surface can be obtained by polishing and processing can be easily performed by applying a vacuum chuck.

In this case, the same applicant proposed a manufacturing method for determining how thick the final polycrystalline silicon layer should be to minimize curvature of the dielectric isolation substrate and to facilitate processing. This is Japanese Patent Application No. 50-54585. That is, if the total thickness of the substrate is y and the length of the final silicon polycrystal is also the length, it is sufficient to satisfy the relationship X≦y/40. In this way, even if the final silicon polycrystalline layer is doped with oxygen during impurity diffusion,
This causes almost no curvature.

The total thickness y of the substrate is generally about 400 to 500 microns in many cases. As an example, assume that the thickness is 400μ.

The silicon polycrystalline layer and silicon oxide film are disclosed in the above-mentioned patent application filed in 1973.
According to No. 138625, it is manufactured using a vapor phase growth technique, which is based on mass production and currently has a maximum thickness accuracy of ±5% at the final level.

Further, the flatness during polishing is approximately ±10μ10μ.

Therefore, as for the polishing accuracy, ±30μ is the maximum accuracy of variation. (400μ x 5% + 10μ = 30μ) According to Japanese Patent Application No. 50-54585, the thickness is ±3
Since it is 0μ, it is impossible to obtain a substrate with little curvature.

Therefore, (1) an object of the present invention is to provide a substrate with less curvature (6) A feature of the present invention that achieves the above object is that near the final silicon polycrystalline layer, the silicon polycrystalline layer and the silicon oxide The purpose is to make the alternate lamination pitch of the film (example -) finer than other parts.

The silicon polycrystalline layer itself is grown using known vapor phase growth technology.
One layer can be formed with a thickness of about 10 μm.

Therefore, if the thickness of each silicon polycrystalline layer for making the pitch finer is, for example, 10 μm, then three such silicon polycrystalline layers are provided. In this case, at least a thickness of 30μ or more can be obtained with these three layers. As mentioned above,
If the polishing accuracy is 30μ, the polished surface will be formed by three layers with finer pitches. on the other hand,
Looking at each silicon polycrystalline layer, its thickness is 10
μ, it is smaller than the thickness X that the outermost layer obtained in the above-mentioned Japanese Patent Application No. 54585-1985 should have, that is, 15μ, and fully satisfies the invention disclosed in the Japanese Patent Application No. 50-54585. Therefore, even if impurities are diffused and oxygen enters these silicon polycrystalline layers for the purpose of forming a single circuit element, almost no curvature will occur in the substrate.

Hereinafter, the present invention will be explained based on the drawings.

In the figure, 1 is a silicon single crystal substrate, and first, separation grooves 2 are formed in a lattice shape. Next, silicon oxide film 3 is formed on the upper main surface.

The silicon oxide film 3 is used as a dielectric film. Thereon, an alternating stack of silicon polycrystalline layers 4 and silicon oxide films 5 is formed as a support region according to the technique disclosed in Japanese Patent Application No. 48-138625. The number of alternately laminated layers is in the patent application filed in 1972-14 by the same applicant as the present application.
According to the technique disclosed in No. 1555, the number of silicon polycrystal layers is preferably 3 to 12, but in this embodiment, the number of silicon polycrystal layers is 11.

The eight silicon polycrystalline layers 4a to 4h counting from the silicon oxide film 3 are the remaining silicon polycrystalline layers 41 to 4k.
It is thicker than. - As an example, the silicon polycrystalline layers 4a to 4h have a thickness of about 50μ, and the silicon polycrystalline layers 41 to
4 is 10μ.

Each silicon oxide film 5 has the same thickness.

The polishing accuracy is set to 30μ. When polishing the final silicon polycrystalline layer 4k for processing using a vacuum chuck or the like, the lower surface of the silicon single crystal substrate 1 is bonded to a polishing table. The composite shown in the figure, which was obtained according to the above-mentioned Japanese Patent Application No. 141555/1980, has almost no curvature.

When the illustrated composite is polished from the upper side, for reasons of polishing accuracy, the difference in the polished surfaces shown by the dashed-dotted line is 30 μm when measured on both sides of the composite.

Even if the difference in the polished surface is 30μ, the silicon polycrystalline layer 4
The total thickness of 1-4k exposed by polishing is 10μ. This corresponds to the thickness of each.

In other words, since each of the exposed silicon polycrystalline layers 41 to 4 has a maximum thickness of 10 μm, the above-mentioned Japanese Patent Application No. 50-5458
According to the technique shown in No. 5, the thickness of the exposed outermost silicon polycrystalline layer can satisfy the relationship X≦y/40.

After the support region is polished, the resulting polished surface is adhered to a polishing table, and the silicon single crystal substrate 1 is polished to the position shown by the two-dot chain line. By this polishing, silicon single crystal islands 1a to 1c are obtained. In addition, the composite material obtained by this polishing, that is, the dielectric isolation insulating substrate 10
It is sufficient if it satisfies the above-mentioned condition X≦y/40.

Circuit elements are formed by diffusing impurities into each silicon single crystal island region 1a-IC in an atmosphere containing oxygen, but at this time, oxygen invades silicon polycrystalline layers 41-4k. Due to the wedge action based on this intrusion.

The dielectric isolation substrate 10 is subjected to a force that causes it to bend, but since the thickness of each silicon polycrystalline layer 41 to 4 is 10μ, the force that causes the dielectric isolation substrate 10 to bend is negligible. almost no curvature occurs.

In various heat treatment processes, the dielectric isolation substrate 1o does not curve, and therefore, it is possible to bring the processing jig such as a mask into close contact with the dielectric isolation substrate 10 over the entire surface without any gaps, so the processing accuracy is high. Significantly improved.

The numerical values used in the above examples are - examples. That is, it can be freely changed depending on the thickness and diameter of the dielectric isolation substrate to be manufactured.

Claims (1)

[Claims] 1. A plurality of silicon single crystal island regions are supported by a support region via a dielectric insulating film, and the support region compensates for the difference in coefficient of thermal expansion between the silicon single crystal and the silicon polycrystal. In a dielectric insulation isolation substrate in which a compensating film and silicon polycrystalline are alternately laminated, and the final layer on the side opposite to the silicon single crystal island region is a silicon polycrystalline layer, the plurality of layers on the final silicon polycrystalline layer side are A dielectric insulation isolation substrate characterized in that a silicon polycrystalline layer is thinner than other silicon polycrystalline layers. 2. In claim 1 above, each of the plurality of thin silicon polycrystalline layers satisfies x≦y/40, where the total thickness of the dielectric insulating isolation substrate is y. Thickness x
1. A dielectric insulating isolated substrate, characterized in that the sum of the thicknesses of x is larger than the numerical value when polishing accuracy on the final silicon polycrystalline layer side is expressed in terms of length.