JPS61164482A - Digital type phase controller - Google Patents

Abstract

PURPOSE:To enhance the responding characteristic of a phase control system by correcting a reference phase by a machine error of frequency generating means to obtain a phase compared output including no machine error. CONSTITUTION:An error pattern by machine error is stored in a RAM 8, and when the RAM 8 is read out, the output DRA of the stored content of the RAM 8 inverted in the polarity is output. The delay time of phase comparing means 4 is corrected by the output DRA of the RAM 8, the delay time corresponding to frequency generating means (FG) 2 is set, and the obtained phase compared output DER is corrected for the machine error of the FG2, i.e., for the pattern. Since no FG machine error is generated at the output DER of the means 4 when the RAM 8 is read out, the frequency characteristic of a digital filter 10 is enhanced to set the loop response to a high value. thus, the responding characteristic of the phase control system can be highly set irrespective of the FG machine error to improve the performance of a phase controller.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase control device for controlling the phase of a rotating body such as a cylinder, a capstan, or a motor of a magnetic recording/reproducing device (VTR).

Conventional technology In the phase control of rotating bodies such as cylinders and capstans in home VTRs, the frequency of % of the vertical synchronization signal (30 Hz in the NTSC system) is used as the sampling frequency, as typified by VH3 and Beta system VTRs. It is used. Generally, the response of a control system is constrained by the sampling frequency, and its upper limit is at most nine times the sampling frequency.

That is, when the sampling frequency is 30 Hz, response characteristics can only be provided up to about 3 Hz.

This is practically sufficient for a stationary VTR, but
Portable type cameras and 8mm V-type cameras with built-in cameras, which need to be made smaller and lighter, are not necessarily sufficient due to their structure and usage. In other words, similar demands are placed on the motor itself that drives the rotating body in order to reduce its size and weight, making it susceptible to tape load fluctuations, vibrations, and the like. To solve this problem, for example, frequency generation means (hereinafter referred to as FG)
This can be achieved by increasing the sampling frequency and improving the response characteristics of the control system.

Problems to be Solved by the Invention However, with the above configuration, if the mechanical precision of the FG is poor, it will cause rotational phase fluctuations, so a highly accurate FG is required, which is not economical. There were problems with practical implementation.

In view of this, an object of the present invention is to provide a digital phase control device that is not affected by mechanical errors even if the FG has mechanical errors and can improve the response characteristics of a control system. It is.

Means for Solving the Problems The present invention comprises a frequency generation means, a phase comparison means, a storage means, and a digital filter, and the storage means is switched between writing and reading by a mode command signal, and in the writing state. This is a non-digital phase comparator that stores the output of the phase comparator and corrects the reference phase of the phase comparator in the read state.Furthermore, it switches the frequency characteristics of the digital filter using a mode command signal and changes the writing state of the memory. The loop response is set low in the read state, and the loop response is set high in the read state.

Operation According to the present invention, with the above-described configuration, the phase comparison means can set a reference phase corresponding to each FG, and a 1:1 relationship can be established between the FG and the reference phase.

Therefore, a phase comparison output with the FG mechanical error corrected can be obtained from the phase comparison means, and the dynamic range can be widened, and the loop response of the phase control system can be set high.

Embodiment FIG. 1 is an electrical block diagram of a digital phase control device showing an embodiment of the present invention. In the electric diagram 1, 1 is a rotating body, 2 is a FG, 3 is a PG (rotational position detection means), and 4
7 is a digital phase comparison means which inputs the FG signal SFG of FG2 and the external reference phase signal SRF from the terminal 5 and digitally compares the phases using the clock pulse ScK input from the terminal 6; a read-only memory IJ (ROM) that provides a reference value NP for phase comparison;
8 is a storage means, a writable/continued memory IJ (RAM) that stores the output DER of the phase comparison means 4; 9 is a R
A switching means selectively switches the output DRO of OM7 and the output DRA of RAMa and supplies it to the phase comparison means 4; 1Q is a digital filter that digitally processes the output DER of the phase comparison means 4; 11 is a digital filter 1;
a driving means for driving the rotating body 1 according to the output DDF of o;
12 inputs the PG signal SPG and the FG signal SFG,
Control means creates an address signal for RAMa, and 13 is an input terminal for a mode command signal SMQ.

In the above configuration, the phase comparison means 4 is composed of an M-bit binary counter, and the phase comparison output D is output from the lower N bits.
Get ER.

FIG. 2 is a waveform diagram showing an example of the operation of the phase comparison means 4.

Waveform A is a reference phase signal, waveform B is a trapezoidal wave signal that is an analog representation of the digital operation of the phase comparison means 4, and waveform C
is the FG signal S, and the waveform DG is the phase comparison output DER. Reference phase signal A is at terminal 6
It is also possible to generate and use an internal reference phase signal by decoding a predetermined count value of a binary counter constituting the phase comparing means 4 instead of the external reference phase signal SRF from the external reference phase signal SRF.

The phase comparison means 4 has the function of setting the initial value twice, 1st preset and 2nd preset, and the 1st preset pulse created by the reference phase signal SRF is used to set the initial value twice.
Perform st preset (first initial value setting), and after this preset, for example, count down and detect that the lower N bits of the binary counter become all "Q", and this all "0" detection pulse causes the first Create 2 preset pulses and perform 2nd preset (second initial value setting). Thereafter, the count down continues, and the period (a) from the 1st preset until the count value reaches NH (2N-1) is set to the high level NH (2N-1). And the period (b) from the count value NH to the count value N L (o) is 2
Take out the lower N bit output of the advance counter and set the ramp period. Further, the period (c) from the count value NL to the next 1st preset is set to a low level NL). NC of the trapezoidal wave signal B is the center value 2N-1 of the slope period (O).

Here, the preset value at the time of presetting is 1 s
t preset, the output DRA of RAM5 (or ROM
7 output DRO), and ROM in the 2nd preset.
The output DRo of y (also the output DRA of RAM8) is used. This switching of the preset value is performed by the switching means e, and the switching signal Ssw is generated by the phase comparing means 4 using the reference phase signal SRF and the all "0" detection pulse. Note that the number of bits of the output DRA of the RAM 8 is equal to the number of bits of the output DER of the phase comparison means 4, which is N.
Since the 2a counter has N bits, the upper M-N bits can be set to R in both 1st and 2nd presets without switching by the switching means 9.
The output DRO (M - N bits) of OM7 is used. Further, when writing to the RAM 5, the output DRA is fixed to a specific value NC (NC-1). ROM7 output DR
Since o is a fixed value NP, the time Ti from the 1st preset to the center value NG of the slope is not constant, and the point where the reference phase signal S and F is delayed by Ti becomes the center of phase comparison. Note that RAMa has addresses corresponding to at least the number of teeth of FG2, and stores phase comparison outputs DER1 to DERZ at addresses corresponding to each of FG2. This writing and address designation are performed by the control means 12.

Figure 3 is a waveform diagram showing the operation when writing to RAM5.
The figure is a waveform diagram showing the operation when reading from the RAM 8. Hereinafter, the operation of the digital phase control device during writing and reading of the pRAM 8 will be explained with reference to FIGS. 3 and 4. Waveforms A-D in Figures 3 and 4 are waveforms A in Figure 2.
-D is the same signal. Waveform E is the PG multiplied signal PG, waveform F is the delayed PG signal SPG', and waveform G is the control means 120 address signal SAD. The delayed signal SPG' is generated, for example, by the falling edge of the PG multiplied signal PG and the FG multiplied signal FG.

In FIG. 3, when writing to RAM 8, the trapezoidal wave signal B has the center of phase comparison at a position delayed by a fixed time Ti from the reference phase signal RF (waveform A), so it is different from the FG signal 5FG (waveform C). Phase comparison is performed using this point as a reference.Here, as mentioned above, since FG2 has a mechanical error, the timing at which the FG multiplied signal FG is generated is also modulated by the mechanical error.Therefore, phase comparison Output DE
Error patterns DER1 to DER6 as shown in the waveforms are generated in R every rotation of the rotating body 1. This error pattern is detected by the latch pulse "LA" of the phase comparison means 4.
The data is stored in each address ADM to ADe of AMa. RAM
The address signal 5AD (waveform G) for selecting address No. 8 is created by resetting the counter with the delayed PG multiplied signal PG' (waveform F) in the control means 12 and dividing the frequency of the FG multiplied signal FG (waveform C). . During this writing, the digital filter 10
Set the loop response low by lowering the frequency response. In this way, the rotating body 1 does not react to the mechanical error of the FG2, that is, the error patterns DER1 to DERe, and the error patterns can be detected with high accuracy.

Next, in FIG. 4, when reading RAM a, R
The memory contents of AM8 DE
This is performed using the doubled signal PG (waveform E), and low-chip conversion is performed in which the address signal SAD is shifted forward one address at a time with respect to the writing time. That is, ADl is AD e, AD2 is A
Dl, AD4 to AD3. AD5 to AD4. AD6 to AD
es respectively. In this way, the delay time Ti of the phase comparison means 4 can be set to the delay time Ti(1) to 'ri(e) corresponding to each output DRA of the RAM s, and the obtained phase comparison output DER has a waveform. As shown in the figure, the mechanical error of FG2, that is, the error patterns DER1 to D
It can be a corrected version of ERe. However, when reading from the RAM 8, the output DER of the phase comparison means 4
Since no FG mechanical error occurs, the frequency characteristics of the digital filter 1o are made high and the loop response is set high. As a result, the response characteristics of the phase control system can be set high regardless of the FG mechanical error, and the performance of the phase control device can be improved.

In addition, in the above explanation, the PG multiplied signal PG is used as a reference, and the FCi
Although an example has been shown in which the address signal SAD is created by frequency-dividing the signal SFG, if the rotational position detection means (PG) 3 is not required, a frequency dividing circuit that divides the frequency of the FG multiplied signal FG is provided, and this division is performed. An isometric PG multiplied signal is created by the circuit, and the PG multiplied signal P
It goes without saying that the objective can be achieved in the same way by substituting G. In addition, when the present invention is applied to a VTR or the like, a rehearsal function is added to generate the mode command signal SMo and write to the RAM 8,
In this case, it is desirable to prevent load disturbances from being applied to the rotating body 1 as much as possible.

Effects of the Invention As is clear from the above explanation, the present invention detects mechanical errors and differences in the frequency generation means (FG) and stores them in the storage means (RAM), and based on the stored contents, the reference for the phase comparison means is determined. Since the phase is corrected, it is possible to obtain a phase comparison output that does not include the FG mechanical error, so the response characteristics of the phase control system can be improved, and its practical effects are significant.

[Brief explanation of drawings]

Fig. 1 is an electrical block diagram of a digital phase control device according to an embodiment of the present invention, Fig. 2 is a waveform diagram showing an example of the operation of the digital phase comparison means in the embodiment, and Fig. 3 is an electrical block diagram of the digital phase control device according to the embodiment. FIG. 4 is a waveform diagram showing an example of the RAM write operation in the second embodiment, and FIG. 4 is a waveform diagram showing an example of the RAM read operation in the same embodiment. DESCRIPTION OF SYMBOLS 1...Rotating body, 2...Frequency generation means, 3...Rotational position detection means, 4...Digital phase comparison means, A... ...Read-only memory, 8...Writable/readable memory, 9.
...Switching means, 10...Digital filter, 12...Control means.

Claims (2)

[Claims] (1) a frequency generating means for detecting the rotational speed of a rotating body; a phase comparing means for comparing the phases of the output of the frequency generating means with a reference phase signal; and a storage means for storing the output of the phase comparing means; and a digital filter which receives the output of the phase comparison means as input, and forms a loop for controlling the phase of the rotating body by the output of the digital filter, and also controls the writing and writing of the storage means by the mode command signal.
A digital phase control device, characterized in that it performs readout switching, stores the output of the phase comparison means during writing, and corrects the reference phase of the phase comparison means during readout. (2) The digital type according to claim 1, characterized in that the frequency characteristics of the digital filter are switched by a mode command signal, the loop response is set low when writing to the storage means, and the loop response is set high when reading. Phase control device.