JPS61163722A - A/d converter - Google Patents

Abstract

PURPOSE:To curtail the number of parts, and to improve the reliability by providing an extending means for extending a low-order counter to a high rank, on the low-order counter, and providing a variable delay means on the output side of a comparator. CONSTITUTION:A low rank extending counter 30 to a low-order counter 17, and a feedback circuit 31 to which that which has combined the output of the counter 30 and a part of an output of the counter 17 is supplied are pro vided, a variable delay counter 32 is provided on the output side of a differential amplifier 11, and its delay quantity is controlled by an output of the feedback circuit 31. The feedback circuit 31 has a threshold value, and when the low-order counter 17 containing the extended part has ended A/D conversion, for instance, if it has counted more than a prescribed range, the delay quantity of the counter 32 is increased by the circuit 31, the count time of a high-order counter 16 is extended, and the count quantity of the counter 17 is decreased. In such a way, the count quantity of the low-order counter 17 is held in a prescribed range.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is an A method for converting analog signals into digital signals.
The present invention relates to A/D converters, particularly cascade integral type A/D converters.

[Conventional technology]

As such a cascade integral type A/D converter, one shown in FIG. 4 has been proposed. In the same figure, +
1) is an input terminal to which an input analog signal is supplied, and this input terminal (11 is connected to a resistor (2) and a switch (3).
) to the inverting input terminal of a differential amplifier (4) constituting an integrator, and the non-inverting input terminal of this amplifier (4) is grounded. An integrating capacitor (5) is connected between the inverting input terminal and the output terminal of the amplifier (4), and a resistor (2) and a -switch (3) are connected to the output terminal of the amplifier (4).
A resistor (6) is connected between the connection point and the connection point.

A series circuit of a switch (7) and a reference current source (8) and a series circuit of a switch (9) and a reference current # (10) are connected between the inverting input terminal of the amplifier (4) and the negative power supply terminal -■. are connected in parallel. The current In of the reference current source (8) and the current io of the reference current source (10) are, for example, [0/1o=
It is assumed that there is a relationship of 127. Also, switch (7)
is a switch for upper integration, and switch (9) is a switch for )-order integration. ' The output terminal of the amplifier (4 is the differential amplifier (1
1) and (12), and the non-inverting input terminal of the amplifier (11) is connected to the sliding terminal of a variable resistor (13) connected between the negative power terminal -V and ground. , the non-inverting input terminal of the amplifier (12) is grounded.

The amplifier (11) is a comparator for the upper counter stop, and the amplifier (12) is a comparator for the lower counter stop.

The outputs of amplifiers (11) and (12) are controlled by nIf!
l path (14). The control circuit (14) controls the opening and closing of the switches (7) and (9), and in conjunction with this, it also controls the clock and, for example, the 7-bit clock that is supplied to, for example, a 9-bit upper counter (16) through the OR circuit (15). controls the clock supplied to the lower counter (17).

Further, the control circuit (14) is supplied with a master clock from a terminal (18) and a conversion command signal from a terminal (19). Further, a carry signal (carry) of the do position counter (17) is supplied to the upper counter (16) via the OR circuit (15). An output register (20) is provided on the output side of the upper counter (16) and lower counter (17), and a sample clock is supplied to this output register (20) from a terminal (21). .

Next, the operation of the circuit shown in FIG. 4 will be explained with reference to FIG. Now, from time to to ti, only the switch (3) is closed, and the switches (7) and (9) are left open. During this period, the input voltage VIN from the input terminal (1) is sampled and
As a result, the output VOtff of the amplifier (4) becomes -VIM.The switch (3) is opened at time t1, and the switch (7) is opened at time t2 after a predetermined time.

Close (9). At the same time, the upper counter (16) starts counting. Amplifier (gradient output is reference current source (8),
(10) approaches 0■ with a constant slope, but when it reaches the reference value of amplifier (11) - Vigpk: 777"
(11) is inverted, the control circuit (14) opens the switch (η) at time t3, simultaneously stops the operation of the upper counter (16), and now the lower counter (17
) starts counting. The amplifier (4) as an integrator continues to operate only with the reference current source (lO). When the output of the amplifier (gradient) crosses Ov, the output of the amplifier (12) is inverted,
The control circuit (14) stops the operation of the lower counter (17) at time t4.

Between the reference current sources (8) and (10), (Io+1o)
Since the relationship is io "2", one count of the upper counter (16) is weighted 27 times as much as one count of the lower counter (17). Therefore, by connecting the upper counter (16) and lower counter (17) in series, 16-bit A/D converted data can be obtained. In other words, 16-bit A/D conversion data is always obtained from the output register (2o).

[Problem that the invention seeks to solve]

By the way, in the case of the conventional circuit having the configuration as shown in FIG. 4, the reference value (threshold voltage ) is adjusted using a variable resistor (13), which increases the number of parts.
Further, there is a drawback that the adjustment man-hours increase the cost as well. Furthermore, in order to prevent the system from going out of order due to changes over time, drift, etc., the lock rate is increased as necessary to provide some margin, resulting in an increase in power consumption and a decrease in reliability and yield.

This invention was made in consideration of this point, and aims to eliminate the need for adjustment by automatically adjusting the reference value (threshold voltage) for switching from the upper counter to the lower counter based on the count value of the lower counter. The present invention provides an A/D converter that can perform

[Means for solving problems]

The A/D converter according to the present invention compares the output of the integrator (4) with a reference value to change the count states of the upper counter (16) and the lower counter (17).
), the lower counter (17) is connected to the lower counter (17).
Extension means (3G) to extend 7) to the upper level, (31
) and a variable delay element Il! on the output side of the comparator (11).
(32), and controls the delay amount of the variable delay means (32) according to the value at the end of A/D conversion of the extension means, so as to keep the count range of the lower counter (17) within a predetermined range. It is configured to fit automatically.

(Function) In the cascade integration type A/D converter, a lower extension counter (30) and a feedback circuit (31) constituting the extension means are provided, and a variable delay means (31) is provided on the output side of the comparator (11).
32), the lower extension counter (30) detects how many times the lower counter (17) has sung, and the information from the lower extension counter (30) and part of the output from the lower counter (17) are The combined result is supplied to a feedback circuit (31) to determine whether it is larger or smaller than a predetermined range, and the determination result is supplied to a variable delay element m (32) to control the amount of delay, and a lower counter (17) Optimize the count range.

[Example] Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows the circuit configuration of this embodiment. In the figure, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

In this embodiment, a lower extension counter (30) is supplied with carry information from the lower counter (17) and extends the first lower counter (17) upward by several bits, and the output of this counter (30) is A feedback circuit (31) to which a part of the outputs of the lower counters (17) is supplied is provided, and a variable delay counter (32) is provided on the output side of the differential amplifier (11). The output of the variable delay counter (32) is supplied to control the amount of delay. Note that the 1-variable delay counter (32) has a terminal (1
8) The master clock is supplied from 8). In addition, a DC power supply (33) is connected to the non-inverting input terminal of the amplifier (11), and a reference value (-V
R needle). The other configurations are the same as in FIG.

The feedback circuit (31) has a threshold value TH of
This is the upper and lower limits of the J predetermined range, as shown in Figure 3.
The feedback circuit (31) determines whether the input value is larger or smaller than a predetermined range, and
The results are digitally accumulated and stored in a variable delay counter (
Return to 32).

In other words, the lower counter (17) including the extension part is the A/D
At the end of the conversion, if the count exceeds the predetermined range, the feedback circuit (31) causes the variable delay counter (32
) by increasing the delay amount of the upper counter (16) to extend the count time of the upper counter (16) and reduce the count amount of the lower counter (17).Conversely, if the count is less than the predetermined range, the variable delay counter (31) is (32) is decreased to shorten the count time of the upper counter (16) and increase the count amount of the lower counter (17). In this way, a negative feedback loop is constructed, and the lower counter (1
7) Count I is maintained within a predetermined range. Note that an increase in the amount of delay of the variable delay counter (32) means that the timing of stopping the clock supplied to the upper counter (16) from the control circuit (14) is delayed, causing the delay from the upper counter (16) to the lower counter (17). ) is delayed, and conversely, the delay amount of the variable delay counter (32) becomes smaller.
6), the timing to stop the clock supplied to
7) respectively means that the timing of switching to 7) is earlier.

FIG. 2 shows an example of the feedback circuit (31). First,
FIG. 2A shows a comparator (31a), addition i! i (31b
) and a register (31c). The adder (31b) and the register (31c) form an accumulator and act as a kind of digital integrator.

The comparator (31a) detects when the input, that is, the output of the lower counter (17) including the output of the lower extension counter (30), is within a predetermined range represented by the threshold value TH at the end of A/D conversion, as shown in FIG. Generates an output of 0 as per A, generates an output of +1 when it is larger than a predetermined range, and generates an output of -1 when it is smaller than a predetermined range. is 0.2 laps (waste count), the upper limit is 2.3 laps (therefore, the predetermined range is 2.1 laps, and this value is most preferably slightly more than 2 laps of the lower counter (17)), and the upper limit is 1 sample from the upper limit. 0 until the end of A/D conversion
．． 2 laps (margin count). In this case, when the lower counter (17) counts θ to 127, one round is completed.

Now, the counter (17) is A/D including the extension part.
If the count exceeds the predetermined range at the end of the conversion, a +1 output is generated from the comparator (31a), inputted to the adder (31b), and the contents of the adder (31b) are taken into the register (31c). It will be done. This operation is repeated, and at the end of A/D conversion, the register (31
c) is fed to the variable delay counter (32). Then, the delay amount of the variable delay counter (32) becomes large, and the timing of stopping the clock supplied to the upper counter (16) is delayed.
) increases, and the lower counter (17)
The time to count decreases.

On the other hand, if the first-place counter (17) including the extension part counts less than the predetermined range at the end of A/D conversion, the comparator (31a) generates an output of -1, and the signal is output in the same way as described above. After processing, the contents of the A/D conversion end point register (31c) are supplied to the variable delay counter (32), and in this case, conversely, the delay amount of the variable delay counter (32) becomes smaller, and the contents are sent to the upper counter (16). Since the timing of stopping the supplied clock becomes earlier, the time counted by the upper counter (16) decreases, and the time counted by the lower counter (17) increases. In this way, there is essentially only one negative feedback, and the input to the comparator (31a), that is, the number of times (count amount) of the F-place counter (17) is maintained within a predetermined range.

Further, FIG. 2B shows a case where the feedback circuit (31) is constructed of a comparator (31a) and an up/down counter (31d). The comparator (31a) is a lower extension counter (30
) If the output of the counter (17) below is within a predetermined range, a HOLD signal is generated as shown in Figure 3A, and if it is greater than the predetermined range, an up signal ([IP) is generated.
Generates a signal, and if it is smaller than a predetermined range, it goes down (DOWN
) generates a signal.

Now, if the lower counter (17) including the extension part is counting more than the predetermined range at the end of A/D conversion, an up signal is generated from the comparator (31a), and the up/down counter (31d) starts counting. and its contents are supplied to the variable delay counter (32). Since the delay amount of the variable delay counter (32) becomes thicker and the timing of stopping the clock supplied to the upper counter (16) is delayed, the counting time of the upper counter (16) increases, and the delay amount of the lower counter (17) increases. ) count time decreases.

On the other hand, if the lower counter (17) including the extension part counts less than the predetermined range at the end of A/D conversion, a down signal is generated from the comparator (31a), and the up/down counter (31d) counts down. Then, the contents are supplied to the counter (32). Then, the delay amount of the variable delay counter (32) becomes smaller, and the timing of stopping the clock supplied to the upper counter (16) becomes earlier, so the counting time of the upper counter (16) decreases, and the timing of the clock supplied to the upper counter (16) decreases. ) increases. In this way, the number of turns (count amount) of the lower counter (17), which is substantially caused by negative feedback, is maintained within a predetermined range.

In addition, in the case of Fig. 3A, the output of the comparator (31a) is 2
In the case of operation corresponding to bits, as shown in FIG. ) has the configuration shown in FIG. A variable delay means is provided on the output side of the comparator that changes the count state of the upper counter and the lower counter, and the delay of the variable delay means is provided in accordance with the value at the end of A/D conversion of the extension means. Since the count range of the lower counter is automatically kept within a predetermined range, the variable resistor that was conventionally used to create the reference value of the above comparator is no longer required, reducing the number of parts and adjustment man-hours. This reduces both costs, making it possible to lower costs.

In addition, it is no longer necessary to run the lower counter several times to allow for drift, changes over time, etc., and the minimum clock frequency is required, reducing power consumption and reducing A/D converter I/O.
The cost of C also decreases, and as a result, the reliability and yield of ICs improve. Furthermore, the drift margin increases dramatically, improving the reliability of the entire circuit without any adjustment. Furthermore, since the feedback circuit system can be constructed entirely of digital circuits, it is possible to incorporate them all into an IC, and there is also the advantage that no external parts are required.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the essential parts of the invention, and FIG. 3 is used to explain the operation of FIGS. 1 and 2. FIG. 4 is a circuit diagram showing an example of a conventional circuit, and FIG. 5 is a diagram for explaining the operation of FIG. 4. (4), (11), (12) are differential amplifiers,
(81, (10) is a reference current source, (14) is a control circuit,
(16) is the upper counter, (17) is the lower counter, (
20) is the output register, (30) is the lower extension counter,
(31) is a feedback circuit, and (32) is a variable delay counter. Fig. 2B Fig. 3 Double-barrel wing 31aλ cal Sameho 31 ridge force (lower tηtsunde karan) - t)
(Lower Karantau Raft a) Figure 5 Procedural Amendment Written March 18, 1985 1, Indication of the Case 1985 Patent Application No. 3863 3, Relationship with the person making the amendment Patent Applicant Address Tokyo 6-7-35, Kita-Shinyo, part name (2
18) Sony Corporation Representative Director Norio Ohga 4, Agent (1) The scope of claims in the specification will be corrected to the rest of the appendix. (2) Same, page 5, lines 2-3 r (Io +1o)
t. =27'' is corrected to rlo/io'''127J. (3) Same, page 6, lines 3-6, ``Higher counter...
- Correct "adjust," to "set reference value by automatically controlling the operations of the upper and lower counters based on the number of pulses input to the lower counters." (Niuma corrects "to count..." on line 12 of the same page to "to control the counting operation.") (6) On lines 14 to 19 of the same page, "the above lower counter...delays." The output signal of this comparator (11) is
The operation of the upper counter (16) and the lower counter (17) is controlled by a variable delay means (32) whose delay amount is set based on the number of pulses input to the lower counter (17). (6) Same, on page 7, lines 3-4, ``doing moxibustion...'' is corrected to ``count the carry information of the lower counter.'' (7) Add "or this information" after "information" on line 8 of the same page. (8) Same, on page 8, line 17, ``have'' is corrected to ``can be detected.'' (9) Add the following at the end of page 14, line 5 of the same. "In the above embodiment, a lower-length counter is provided separately from the lower-order counter, but it is of course possible to integrally configure the lower-order counter and the lower-order extension counter." αl Ibid., pp. 8-13. "Lower counter...controls" in the row is changed to "A variable whose delay amount is controlled based on the number of pulses input to the output signal of the comparator to the lower counter to control the operation of the upper counter and lower counter." By controlling by means of delay” is corrected. - Claims 1. an integrator that stores charge corresponding to an input signal; first and second current sources that discharge the charge at a constant rate; and a comparator that compares the output signal of the integrator with a reference value. and an upper counter and a lower counter whose operation is controlled by the output signal of the comparator, and a cascade integral type A/D converter in which a digital signal corresponding to the input signal is output from the upper counter and the lower counter. A variable delay counter is provided for delaying the output signal of the comparator, and the amount of delay by the variable delay counter is controlled according to the number of pulses input to the lower counter, so that the output signal is input to the lower counter. An A/D characterized in that the number of pulses is within a predetermined range.
converter. 2. A patent claim characterized in that a lower extension counter is provided for counting carry information of the lower counter, and the amount of delay of the variable delay counter is controlled by the count value of the lower extension counter. The A/D converter according to the range 1 above. 3. The A/D converter according to claim 1, wherein the delay amount of the variable delay counter is controlled by the carry information of the lower counter and the count value of the lower counter.

Claims (1)

[Claims] In a cascade integration type A/D converter equipped with a comparator that compares the output of an integrator with a reference value and changes the count state of an upper counter and a lower counter, the lower counter is extended to the upper one with respect to the lower counter. and a variable delay means on the output side of the comparator, the amount of delay of the variable delay means is controlled according to the value of the delay means at the end of A/D conversion, and the count of the lower counter is controlled. An A/D converter characterized in that the range is automatically kept within a predetermined range.