JPS6116029B2 - - Google Patents
Info
- Publication number
- JPS6116029B2 JPS6116029B2 JP54150490A JP15049079A JPS6116029B2 JP S6116029 B2 JPS6116029 B2 JP S6116029B2 JP 54150490 A JP54150490 A JP 54150490A JP 15049079 A JP15049079 A JP 15049079A JP S6116029 B2 JPS6116029 B2 JP S6116029B2
- Authority
- JP
- Japan
- Prior art keywords
- board
- tested
- circuit
- wiring pattern
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010998 test method Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 14
- 238000007689 inspection Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 241001422033 Thestylus Species 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
【発明の詳細な説明】
本発明は被検査基板の回路パターンの短絡状態
を検査する検査法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection method for inspecting a short-circuited state of a circuit pattern on a board to be inspected.
一般に基板の回路パターンの短絡等の検査は、
触針による検出方法がとられている。ところが、
回路基板には、メツキリードを有することが多
く、このメツキリードが存在する場合、上記触針
での検出は不可能である。従つてメツキリードを
有するものは目視で検査が行なわれている。その
ため検査に大変な手間がかかるだけでなく検査ミ
スが多数生じていた。 In general, inspection of short circuits etc. of the circuit pattern of the board is carried out by
A detection method using a stylus is used. However,
Circuit boards often have plating leads, and if these plating leads are present, detection with the stylus is impossible. Therefore, those with a blind lead are visually inspected. For this reason, not only was the inspection time-consuming, but also many inspection errors occurred.
本発明は、このような点に鑑みなされたもので
あり、メツキリードを有していても、短絡検査を
可能にする検査法を提供するのである。尚本発明
はメツキリードを有していない基板でも、検査で
きることは勿論である。 The present invention has been made in view of these points, and provides an inspection method that enables short-circuit inspection even when a wire has a blind lead. It goes without saying that the present invention can also inspect a board that does not have a plating lead.
以下図面に示す実施例に従つて本発明を説明す
る。第1図は検査部の斜視図である。図中1は被
検出基板2を保持する下部基台、3は検出用の電
極を有した検出基板4を保持する上部基台であ
る。上記下部基台1はX又はY方向に移動可能で
あつて、上部基台3はZ方向(縦方向)に移動可
能に設けられている。上記被検出基板2は、例え
ば第2図aに示す如き回路配線がパターン2―1
を有しており、図中2―2はメツキリードであ
る。 The present invention will be described below with reference to embodiments shown in the drawings. FIG. 1 is a perspective view of the inspection section. In the figure, 1 is a lower base that holds a detection target substrate 2, and 3 is an upper base that holds a detection substrate 4 having a detection electrode. The lower base 1 is movable in the X or Y direction, and the upper base 3 is movable in the Z direction (vertical direction). The detection target board 2 has a circuit wiring pattern 2-1 as shown in FIG. 2a, for example.
2-2 in the figure is Metsuki lead.
一方、検出基板4は、被検出基板2の回路配線
パターン2―1と逆パターンの電極4―1を、第
2図b如く基板上に形成している。この電極4―
1のネガ幅は、被検出基板2の配線パターン2―
1の逆パターンの幅より細く形成されている。 On the other hand, the detection substrate 4 has an electrode 4-1 formed thereon with an opposite pattern to the circuit wiring pattern 2-1 of the detection target substrate 2, as shown in FIG. 2B. This electrode 4-
The negative width of 1 is the wiring pattern 2-
It is formed narrower than the width of the reverse pattern of pattern 1.
以上の構成のものにおいて、上部基台3が下降
し、検出基板4と下部基台1上の被検出基板2と
を接触させ重ね合わせる。この場合、第2図cに
重ね合せた状態を示している。この第2図cの状
態で配線パターン2―1と電極4―1との導通状
態を検出する。そこで、導通状態が検出されれ
ば、配線パターン2―1の何等れかのネガ間が短
絡2―3されており、この短絡部2―3と電極4
―1とが接触することが導通状態が検出され、被
検査基板2の配線パターン2―1の短絡状態が簡
単に検出できる。上記導通状態が検出されなけれ
ば、次の被検出基板2を下部基台1に保持させ、
上述の検査を行なえばよい。 In the above configuration, the upper base 3 is lowered, and the detection substrate 4 and the detected substrate 2 on the lower base 1 are brought into contact with each other and overlapped. In this case, the superimposed state is shown in FIG. 2c. In this state shown in FIG. 2c, the conduction state between the wiring pattern 2-1 and the electrode 4-1 is detected. Therefore, if a conductive state is detected, a short circuit 2-3 is established between some negatives of the wiring pattern 2-1, and this short-circuit portion 2-3 and the electrode 4 are connected.
-1 is detected as a conductive state, and a short-circuited state of the wiring pattern 2-1 on the board 2 to be inspected can be easily detected. If the conduction state is not detected, the next board to be detected 2 is held on the lower base 1,
The above-mentioned test may be performed.
ここで、検出基板4の電極4―1のネガ幅が、
被検査基板2の回路配線以外の逆パターンの幅よ
り細いことから、被検査基板2の回路配線パター
ン2―1と検査基板4の電極4―1とが接触しな
い程度に、例えば被検査基板2側をX又はY方向
に移動させて検査をより確実なものにすることが
できる。即ち、下部基台1を微小ピツチずらし
て、上部基台3を重ね合わせて、その都度導通状
態を検出する。この操作は、下部基台1を上述の
如く回路配線パターン2―1と電極4―1との接
触しない程度移動させ、繰り返えし行う。そし
て、下部基台1を移動させる間に導通状態が検出
されなければ、被検出基板2のネガの短絡はな
い。この場合、1度の検査に比べより信頼性の高
に検査ができ、ネガ間の短絡だけでなく、短絡し
かかりをも検出できる。 Here, the negative width of the electrode 4-1 of the detection board 4 is
Since the width is narrower than the width of the reverse pattern other than the circuit wiring on the board to be inspected 2, the width of the circuit wiring pattern 2-1 of the board to be inspected 2 and the electrode 4-1 of the inspection board 4 is not in contact with each other. The side can be moved in the X or Y direction to make the inspection more reliable. That is, the lower base 1 is shifted by a small pitch, the upper base 3 is superimposed, and the conduction state is detected each time. This operation is repeated by moving the lower base 1 to such an extent that the circuit wiring pattern 2-1 and the electrode 4-1 do not come into contact with each other as described above. If the conduction state is not detected while the lower base 1 is being moved, there is no negative short circuit of the detected substrate 2. In this case, the test can be performed with higher reliability than a one-time test, and not only short circuits between negatives but also short circuits can be detected.
以上説明したように、本発明による短絡検査法
によれば、基板上に2次元に広がつて形成された
配線パターンに対して、同一平面上の配線パター
ンを一度に検査することができ、検査時間の短絡
化が図れると共に、検査作業を機械化することが
でき、生産性や信頼性向上等に極めて有利であ
る。 As explained above, according to the short circuit inspection method according to the present invention, it is possible to inspect the wiring patterns on the same plane at the same time for the wiring patterns that are spread two-dimensionally on the board. It is possible to shorten the time and mechanize the inspection work, which is extremely advantageous in improving productivity and reliability.
第1図は本発明にかかる検査法の一例を示す斜
視図、第2図a,b,cは本発明にかかる各基板
を示すもので、aは被検査基板の回路配線パター
ンの一例を示す平面図、bは検出基板の検出電極
を示す平面図、cはa及びbを重ね合わせた状態
を示す透視平面図である。
2;被検出基板、2―1;回路配線パターン、
4;検出基板、4―1;検出電極。
Fig. 1 is a perspective view showing an example of the inspection method according to the present invention, Fig. 2 a, b, and c show each board according to the present invention, and a shows an example of the circuit wiring pattern of the board to be inspected. A plan view, b is a plan view showing the detection electrode of the detection substrate, and c is a perspective plan view showing a state where a and b are superimposed. 2; Detected board, 2-1; Circuit wiring pattern,
4; Detection substrate, 4-1; Detection electrode.
Claims (1)
ターンとは逆パターンの関係によつて、且つ上記
回路配線パターンより細いネガ幅の電極が形成さ
れた検査基板を、上記被検査基板に重ね合わせて
面接触させ、被検査基板の回路配線パターンと検
査基板の電極との間の短絡状態を検出することに
より、上記被検査基板の回路配線パターンの短絡
を検査することを特徴とする基板の回路短絡検査
法。1. Overlaying a test board on the board to be tested, which has an opposite pattern to the two-dimensional circuit wiring pattern formed on the board to be tested, and on which electrodes with a negative width narrower than the circuit wiring pattern are formed. A circuit of a board characterized in that a short circuit in the circuit wiring pattern of the board to be tested is tested by bringing the circuit wiring pattern of the board to be tested into surface contact with an electrode of the board to be tested and detecting a short circuit state between the circuit wiring pattern of the board to be tested and an electrode of the board to be tested. Short circuit test method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15049079A JPS5672365A (en) | 1979-11-19 | 1979-11-19 | Inspection of short circuit of board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15049079A JPS5672365A (en) | 1979-11-19 | 1979-11-19 | Inspection of short circuit of board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5672365A JPS5672365A (en) | 1981-06-16 |
JPS6116029B2 true JPS6116029B2 (en) | 1986-04-26 |
Family
ID=15498002
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15049079A Granted JPS5672365A (en) | 1979-11-19 | 1979-11-19 | Inspection of short circuit of board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5672365A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH063127U (en) * | 1992-06-24 | 1994-01-18 | 祐子 佐藤 | rucksack |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4463645B2 (en) * | 2004-08-27 | 2010-05-19 | 日本メクトロン株式会社 | Printed circuit board and inspection method thereof |
-
1979
- 1979-11-19 JP JP15049079A patent/JPS5672365A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH063127U (en) * | 1992-06-24 | 1994-01-18 | 祐子 佐藤 | rucksack |
Also Published As
Publication number | Publication date |
---|---|
JPS5672365A (en) | 1981-06-16 |
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