JPS61158249A - Code system - Google Patents

Abstract

PURPOSE:To prevent an reception error due to a step-out by putting the codes reverse to the continuous logic in a period between the center of the (m-1)-th bit and the end of the m-th bit when (m) or more pieces of same bits are delivered continuously. CONSTITUTION:A counter 6 detects that the same logic of data is continuous in (m) bits and informs this to a switch control circuit 7. The circuit 7 controls a switch circuit 9 at the (m-1)-th and m-th bit output timings and switches the circuit 9 at the side of a signal generating circuit 8. The circuit 8 produces the codes of the deformation patterns corresponding to the (m-1)-th and m-th bits when the circuit 9 is switched to the side of the circuit 8. Both the counter 6 and the circuit 7 are initialized for each change of data. Thus a timing extracting circuit at the reception side is restarted within a fixed period of time. This prevents a reception error due to a step-out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a coding system for self-synchronizing baseband data transmission.
This relates to a coding system that can encode so that no more than a certain number of bits are consecutive for any of the above.

[Conventional technology]

As a method for extracting synchronization timing on the receiving side in this type of coding system, for example, a delay circuit having a certain delay time is used as a time reference, and 1 Separate discharge: By inverting the input signal that has been delayed through this delay circuit and performing a logical product with the input signal, 1” and 0” are alternately generated by interrupting the succession of #0” and #1” A method has been proposed that uses a circuit that converts the signal into a repeating signal.

FIG. 6 shows such a conventional synchronization timing extraction circuit, in which 1α and 1b are delay circuits, and 2a and 2b are delay circuits.
is an AND circuit, 3.3a and 3b are NOT circuits, and 4 is an OR circuit. Moreover, FIG. 7 shows signals of various parts in the circuit of FIG. 6, and shows V! 8 is an input signal, CK1 is an input signal of 1H"
A synchronized timing signal when the level is (b))
(b) shows the case where the input signal 1H" is relatively short, and (b) shows the case where the input signal a"H" continues for a long time.

In FIG. 6, the received input signal V is applied to one input of an AND circuit 2α, and the output of the AND circuit 2α passes through a delay circuit 1α and a negative circuit 3α.
is fed back to the other input. This causes the input signal V□
, is at the 1H" level, for example, as shown in FIG. can be obtained.

On the other hand, the received input signal VIN is inverted via the NOT circuit 3, and is then inverted by the AND circuit 2b, the delay circuit 1b, and the NOT circuit 3b.
Similarly, when the input signal V□ is at the σL'' level, the delay circuit 1
A synchronous timing signal CK2 that alternately repeats the fall delay time and rise delay time of b is obtained at the output of the AND circuit 2b.

Both synchronous timing signals are added through an OR circuit 4, and a synchronous timing signal output CX corresponding to the "H" level and the "L" level of the input signal is output.

Note that such a synchronization timing extraction method is described in Japanese Patent Application No. 57-165359 (Japanese Unexamined Patent Publication No. 59-1989) filed by the present applicant.
No. 54544).

[Problem that the invention seeks to solve]

In the synchronization timing extraction method shown in FIG. 6, when the period of 'H' and 'L' of the received input signal is relatively short, the input data and synchronization timing are extracted as shown in FIG. 7 (α). The correct bit correspondence is maintained. However, the delay circuit 1α shown in FIG.

The fall delay time and rise delay time of 1b are fixed, so if the received input signal continues for a long time, time distortion due to the delay circuit is accumulated. , the pit correspondence between the input data and the synchronization timing signal may gradually shift.

Fig. 7 (b+ indicates a case where the input signal has a long 'H' period and a synchronization error occurs; t in the figure indicates the synchronization time; P indicates an erroneous signal caused by the synchronization shift time t). ing.

As a method to prevent such synchronization errors, the transmitting side inserts a sign of the opposite logic so that the same logical state does not continue for more than a certain period of time, and the receiving side uses this signal to extract synchronization timing. A conventional method is to then delete the inserted code and output the data. However, when using such a method of inserting opposite logic codes, there is a problem in that it takes extra time to transmit the inserted codes.

The present invention aims to solve the problems of the conventional technology, and even when many bits of the same logic are consecutive in self-synchronized baseband data transmission,
The present invention is intended to provide a coding system that is free from the occurrence of synchronization errors that cause reception errors, and does not require extra transmission time unlike conventional code insertion systems.

[Means for solving problems]

The encoding method of the present invention is such that when bits of the same logic continue for more than bait on the transmitting side, the period from the center of the (m-1)th bit of the consecutive part to the end of the mth bit is 1+ bits. A code with the opposite logic of the continuous logic is inserted and transmitted, the receiving side detects the code with the opposite logic inserted into the T reception signal, generates a masking signal corresponding to that period, and uses this masking signal to control the reception. The original data on the transmitting side is restored by masking the signal.

[For production]

In the coding system of the present invention, in self-synchronous baseband data transmission, when m or more bits of the same logic are consecutive on the transmitting side, the m-th bit from the center of the (m-1)th bit of the consecutive part is A code of the opposite logic of this continuous logic is inserted and transmitted in the period up to the end of the continuous logic, and the received signal is masked by a masking signal generated by detecting the inserted code of the reverse logic on the receiving side. Since the ψ output data is modified, the transmission code is encoded so that neither gOn nor Ml'' is continuous for more than a certain number of bits, and therefore the timing extraction circuit on the receiving side is restarted within a certain period of time. In other words, reception errors due to synchronization errors are prevented.

〔Example〕

FIG. 1 shows a transmission code according to an embodiment of the present invention, and shows a transmission code when transmitting data of the same logic of consecutive poisonous bits, illustrating the case of logic #0''. In other words, the transmission code in the present invention "transforms" the Cm-1)th and the Cm-th digit of the same logical data, and uses it as a mark that m bits of the same logical data are consecutive.

FIG. 2 shows a code generation circuit according to an embodiment of the present invention. In the figure, 5 is an m-bit shift register;
6 is a counter, 7 is a switching control circuit, 8 is a signal generation circuit,
9 is a switching circuit.

In FIG. 2, m-bit data is output to a transmission line via an m-bit shift register 5 and a switching circuit 9.

At this time, the counter 6 detects that m bits of the same logic are consecutive in the data, and notifies the switching control circuit 7 of this fact. The switching control circuit 7 controls the switching circuit 9 to switch to the signal generation circuit 8 side at the output timing of the (m-1)th bit and the mth bit. The signal generation circuit 8 is configured to be able to generate a code with a "modified" pattern corresponding to the (m-1)th bit and the ordinary bit in the transmission code shown in FIG. When the code is switched to the signal generating circuit 8 side, this code is output to the transmission line. The counter 6 and the switching control circuit 7 change data (in the example of FIG. 1, the data changes from 10" to
1”).

FIG. 3 shows a timing extraction circuit on the receiving side in an embodiment of the present invention, and the same parts as in FIG. 6 are denoted by the same symbols.
18 is an AND circuit, 18 is a flip-flop with a preset function, 19 and 20 are NOT circuits, and 21 is a shift register.

In FIG. 3, the timing signal CK2 is supplied to the delay circuit 1b.
The timing signal CK2 is delayed by one bit to produce a delayed signal CK2D of the timing signal CK2. AND circuit 15 receives signal CK2
When D and the received signal V□8 are both -1'', the flip-flop 18 is set.

On the other hand, the timing signal CK1 is applied to the AND circuit 16, and is also applied to the AND circuit 1 via the NOT circuit 19.
Added to 7. Timing signals nPT- and DPT generated by a seven-lip flop 18 are applied to the other inputs of the AND circuits 16 and 17, respectively.

AND circuit 16.17 output and timing signal CK
2 is added to the OR circuit 4C, and the logical sum is taken to generate the timing signal CK.

The timing signal CK is used as a sampling clock of the receiving circuit in the method of the present invention.

The flip-flop 18 is reset by a signal V8 obtained by sampling the received signal V by the shift register 21 at the rising edge of the clock CK. In the third circuit, the delay times of the delay circuits 1α and 1b are set to be approximately equal.

FIG. 4 shows a sampling circuit according to an embodiment of the present invention, in which 22 and 23 are AND circuits, and 24 and 25 are 1-bit shift registers having the same configuration.

The timing signal CK obtained from the timing extraction circuit shown in FIG.
5 as a clock. The AND circuit 22 receives the received input signal r□ and the flip-flop 18 in FIG.
The timing signal DPT is input to the shift register 24, and its output is given as an input to the shift register 24. AND circuit 2
3 receives the output 0UTo of the shift register 14 and the timing signal DPT, and its output is input to the shift register 25.
is given as input.

FIG. 5 is a time chart showing signals of various parts in the timing extraction circuit of FIG. 3 and the sampling circuit of FIG. 4, and is for explaining the operation on the receiving side when the coding system of the present invention is used.

Assuming that data in which σ0'' is continuous m bits is to be received, the received signal VIN is encoded by the method of the present invention on the transmitting side as described above, and the (m-1)th bit and the mth bit are encoded. The bits are "transformed".

The clock CK2 rises at the falling edge of the received signal V,
While the reception signal VIN is at the 1L" level, it alternately repeats the 'H' level and the final L level. The clock CK2D passes through the delay circuit 1b and is delayed by 1 bit from the clock CK2. The AND circuit 15 receives Input signal V□8 and clock C
By ANDing with K2D, the input signal VI
'H in the latter half of the (771-1)th bit of H
” and generates an output signal DTR.

Signal DTR is a detection signal indicating the presence of "deformation" in input signal VIN. Flip 70 knob 8 is signal DTR
The (fi-1)th bit and the mth bit in the input signal VIN are generates an output DPT corresponding to the "deformed" portion of .

The AND circuit 22 generates an output of the logical product of the received input signal VIN and the timing signal DPT of the flip-flop 18, and the shift register 24 samples the output of the AND circuit 22 at the falling edge of the timing signal CX and delays it by 1 bit. to generate an output signal 0UTo. The AND circuit 23 generates an output of the logical product of the signal 0UTo and the timing signal DPT, and the shift register 25 samples the output of the AND circuit 23 at the falling edge of the timing signal CK, delays it by 1 bit, and outputs the output signal OUT. However, the output signal OUT is the (?7L-1)th in the input signal VIN.
The data that corrects the bit and the m-th bit is "repaired"
The original data on the transmitting side in which m bits of ``0'' are consecutive is reproduced.

In addition, in FIG. 5, the output 0UT of the shift register 24
The reason why the (m-1)th bit of o is 11" is because the gate delay of the AND circuit 15 causes the output signal DTR
The rise of the output signal DPT is delayed due to the delay of the flip-flop 18, and as a result, the rise of the output signal DPT in the AND circuit 22 is delayed.
The timing of masking IN is determined by the shift register 24.
This is because it is in time for the sampling timing of . In the circuit of FIG. 4, the (
m-1) “Repair” the 〆1″ that appeared in the bit-th bit to 10
”, an AND circuit 23 and a shift register 25 are additionally used.

In the embodiment described above, it is assumed that the data bit 0'' is continuous in virtual bits, but this is mainly due to parity bit addition in general data transmission methods,
10” insertion (11”) in the so-called HDLC transmission procedure
If there are 5 or more consecutive bits, 10'' is inserted into the 6th bit and transmitted, and the receiving side deletes the 6th bit, po0''. ), the outer code system is often designed in advance to prevent more than a certain number of consecutive '1's.

In the above-described embodiment, a case has been described in which data "0" is continuous in virtual bits, but it goes without saying that the method of the present invention can be similarly applied to a case in which data #1" is continuous in virtual bits.

〔Effect of the invention〕

As explained above, according to the coding system of the present invention, the transmission number in self-synchronous baseband data transmission is 10
", #1" are encoded so that they do not continue for more than a certain number of pits, so the timing extraction circuit on the receiving side will be restarted within a certain period of time, preventing reception errors due to synchronization. Prevented.

Further, according to the method of the present invention, the transmission code is dO'' or #
1", so the photoelectric conversion circuit and the signal amplifier can be capacitively coupled, especially when applied to optical transmission. This prevents saturation of the amplifier, improving response characteristics. Note that the fact that there is no degeneracy in the transmission code means that there is an advantage that disconnection abnormalities in the transmission line can be detected by adding a circuit (not shown) to detect degeneracy. .

Furthermore, according to the coding system of the present invention, there is no need to use Manchester code (RZ multiplied signal) as in conventional optical transmission systems, and an NRZ signal can be used. This has the effect of realizing twice the transmission speed.

Furthermore, in the system of the present invention, since no redundant bits are added to the transmission code, there is an advantage that data according to the HDLC transmission procedure can be transmitted as is.

[Brief explanation of the drawing]

1 to 5 show an embodiment of the coding system of the present invention, and FIG. 1 is a diagram showing an example of a transmission code,
Figure 2 shows an example of the configuration of the code generation circuit, Figure 3 shows an example of the configuration of the timing extraction circuit on the receiving side, Figure 4 shows an example of the configuration of the sampling circuit, and Figure 5 shows the example of the configuration of the receiving side. 3 is a time chart illustrating the operation of FIG. 6 is a diagram showing the configuration of a conventional timing extraction circuit, and FIG. 7 is a time chart showing timing signal extraction in the circuit of FIG. 6. 1α, 1b...Delay circuit, 2α, 2b...AND circuit, 3°3α, 5b...Negation circuit, 4...OR circuit, 4C...3 person chaor circuit, 5...Shift Register, 6... Counter, 7... Switching control circuit, 8...
Signal generation circuit, 9... Switching circuit, 15-17... AND-1 path, 18... Flip-flop, 19.20
...Negation circuit, 21...Shift register, 22.2
3...AND circuit, 24.25...Shift register. Patent Applicant Fuji Electric Co., Ltd. (1 other person) Representative Patent Attorney Gobe Tamamushi (2 others) Figure 1 Figure 2 9-t7) General circuit

Claims (1)

[Claims] In self-synchronous baseband data transmission, when m or more bits of the same logic are consecutive on the transmitting side, the period from the center of the (m-1)th bit of the consecutive part to the end of the mth bit is A code of the reverse logic of the continuous logic is inserted and transmitted, and the receiving side detects the code of the reverse logic inserted into the received signal and generates a masking signal corresponding to that period. A coding method characterized by restoring the original data on the transmitting side by masking the reverse logic code inserted into the data.