JPS61158151A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61158151A JPS61158151A JP27755884A JP27755884A JPS61158151A JP S61158151 A JPS61158151 A JP S61158151A JP 27755884 A JP27755884 A JP 27755884A JP 27755884 A JP27755884 A JP 27755884A JP S61158151 A JPS61158151 A JP S61158151A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- shape
- sealed
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000007789 sealing Methods 0.000 claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 43
- 239000011347 resin Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 18
- 230000001105 regulatory effect Effects 0.000 claims description 12
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052742 iron Inorganic materials 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract description 3
- 229920000647 polyepoxide Polymers 0.000 abstract description 3
- 239000000843 powder Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 150000008065 acid anhydrides Chemical class 0.000 abstract 1
- 239000010453 quartz Substances 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005350 fused silica glass Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000009974 thixotropic effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、半導体素子を樹脂によって封止する半導体
装置の製造方法に関し、特に素子を所望の面積、形状に
薄肉かつフラットに封止するための封止方法に関するも
のである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is encapsulated with a resin, and in particular to a method for encapsulating a semiconductor device in a thin and flat manner in a desired area and shape. This relates to a sealing method.
従来、回路基板上に搭載された、あるいはフィルムキャ
リアにリードを介して接続された半導体素子を封止する
には、封止樹脂の粘性、チクソトロピンク性２表面張力
などを利用し、第７図あるいは第８図に示したように一
定量の封止樹脂を封止部分に載せ、素子を含む封止すべ
き部分の面積。Conventionally, in order to seal a semiconductor element mounted on a circuit board or connected to a film carrier via leads, the viscosity of the sealing resin, the thixotropic 2 surface tension, etc. As shown in the figure or FIG. 8, a certain amount of sealing resin is placed on the sealing part, and the area of the part including the element to be sealed is determined.
形状及びその厚さを一樹脂の自然の広がりによって作り
、その状態で樹脂を硬化し、目的とする半導体素子の封
止を行っていた。The shape and thickness are created by the natural expansion of a resin, and the resin is cured in that state to seal the intended semiconductor element.
即ち、両図においてミ １は封止樹脂、２は半導体素子
、５，５ａ、ｓｂは接続リード、３は回路、４は回路基
板、６はフィルムキャリア、６ａはインナーフレームを
示し、第７図の場合では、基板４に半導体素子２が設置
され、これをリード５を介して基板上の回路３と接続し
たのち素子２を含む封止すべき部分を封止樹脂１でオー
バーコートし、該樹脂１を加熱硬化していた。That is, in both figures, 1 is a sealing resin, 2 is a semiconductor element, 5, 5a, and sb are connection leads, 3 is a circuit, 4 is a circuit board, 6 is a film carrier, and 6a is an inner frame. In this case, a semiconductor element 2 is installed on a substrate 4, which is connected to a circuit 3 on the substrate via a lead 5, and then the part to be sealed, including the element 2, is overcoated with a sealing resin 1. Resin 1 was cured by heating.
また、第８図の場合では、フィルムキャリア６のインナ
ーリード５ａに直接半導体素子２を接続し、該素子２を
含む封止すべき部分を封止樹脂１でオーバーコートし、
該樹脂１を加熱硬化していた。In the case of FIG. 8, the semiconductor element 2 is directly connected to the inner lead 5a of the film carrier 6, and the part to be sealed, including the element 2, is overcoated with the sealing resin 1,
The resin 1 was cured by heating.
しかるに、このように上記封止すべき部分の面積、形状
は封止樹脂の量やその粘性、チクソトロビック性及び表
面張力などの樹脂の特性によって自然に形成されるため
、どうしても円形の広がりを持ち、四角形など特定の形
状にすることが困難であった。又、封止すべき部分の断
面形状も樹脂の表面張力により山形となり、フラットな
形状にできなかった。そして、樹脂はリード部分への含
浸性を良くするために粘度を低くすると広がりすぎ、そ
れを防止するために粘度を高くすると山の高さが高くな
るなど所望の形状にコントロールすることは不可能であ
った。However, since the area and shape of the part to be sealed are naturally formed depending on the resin properties such as the amount of sealing resin, its viscosity, thixotropic property, and surface tension, it is inevitable to create a circular spread. It was difficult to hold it and make it into a specific shape such as a square. Further, the cross-sectional shape of the portion to be sealed also became mountain-shaped due to the surface tension of the resin, and could not be made into a flat shape. If the viscosity of the resin is lowered to improve impregnation into the lead part, it will spread too much, and if the viscosity is increased to prevent this, the height of the peaks will become higher, making it impossible to control the desired shape. Met.
この発明は、このような問題点を解消するためになされ
たもので、半導体素子を樹脂にて所望の面積、形状を有
するよう、かつ薄肉、フラットに封止できる半導体装置
の製造方法を得ることを目的とするものである。The present invention has been made to solve these problems, and provides a method for manufacturing a semiconductor device in which a semiconductor element can be sealed with resin to have a desired area and shape, and to be thin and flat. The purpose is to
この発明に係る半導体装置の製造方法は、回路基板等の
上の半導体素子上方に、又はフィルムキャリア等にリー
ドを介して接続された半導体素子の上下に該素子を含む
封止すべき部分の面一μ状形状規制体との間隙、又は２
つの形状規制体間の間隙に封止樹脂を充填し、該樹脂を
加熱硬化するものである。The method for manufacturing a semiconductor device according to the present invention provides a method for manufacturing a semiconductor device on a circuit board or the like, or above and below a semiconductor element connected to a film carrier or the like via a lead, on the surface of a portion to be sealed that includes the element. 1. Gap between μ-shaped regulating body, or 2.
The gap between the two shape regulating bodies is filled with a sealing resin, and the resin is cured by heating.
この発明においては、回路基板等と所望の面積。 In this invention, a circuit board etc. and a desired area.
形状の先端部を有する形状規制体との間に位置する半導
体素子を含む封止すべき部分、あるいはかかる２つの形
状規制体間に位置するフィルムキャリア等に接続された
半導体素子を含む封止すべき部分、に封止樹脂が充填さ
れ、これが加熱硬化されるから、上記封止部分の形状は
再現性良く上記面積、形状を有し、かつ薄肉、フラット
なものとなる。A part to be sealed including a semiconductor element located between a shape regulating body having a shaped tip, or a sealing part including a semiconductor element connected to a film carrier etc. located between two such shape regulating bodies. Since the sealing resin is filled in the desired portion and cured by heating, the shape of the sealing portion has the above-mentioned area and shape with good reproducibility, and is thin and flat.
、以下、この発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図は本願の第１の発明の一実施例による半導体装置
の製造方法を説明するためのものであり、これは、フラ
ットな先端部を持つ板状又は柱状の形状規制体を封止部
分に回路基板ヰと対向させて設置し、その間に封止樹脂
を充填した状態を示すものである。即ち、第７図と同一
符号は同−又は相当部分を示し、７は封止すべき面積、
形状が四角形のフラットな先端を持つ四角柱状の鉄片か
らなる形状規制体である。FIG. 1 is for explaining a method for manufacturing a semiconductor device according to an embodiment of the first invention of the present application. This figure shows a state in which the circuit board is placed facing the circuit board, and a sealing resin is filled between them. That is, the same reference numerals as in FIG. 7 indicate the same or equivalent parts, and 7 indicates the area to be sealed;
It is a shape regulating body consisting of a rectangular prism-shaped iron piece with a rectangular flat tip.
この方法では、回路基板４にリード５を介して接続され
た半導体素子２に対し、該素子２の約４倍のフラットな
先端面積を持つ離型剤処理された四角柱状の鉄片７を、
回路基板４から１．５ｎ隔てて平行に対向させ、その間
の封止部分にプリコート用酸無水物硬化溶融石英粉末充
填エポキシ樹脂１を充填し、この状態にて１５０℃で３
時間硬化させる。この充填・硬化期間では、樹脂１をそ
の粘度と表面張力によって封止部分に滞留した状態のま
ま硬化できる。従って、その期間は、樹・脂層を水平状
態に保つことが望ましい、硬化後、鉄片７を封止部より
はずし、第５図（Ｊｌ） （ｂ）に示すように回路基板
４上に約１０鶏角、厚さ１．５ｆｉの四角形の面積形状
を有し、薄肉、フラットに樹脂封止された半導体装置を
得る。In this method, a rectangular prism-shaped iron piece 7 treated with a release agent and having a flat tip area approximately four times that of the element 2 is attached to a semiconductor element 2 connected to a circuit board 4 via a lead 5.
The circuit board 4 was placed parallel to the circuit board 4 at a distance of 1.5n, and the sealing portion between them was filled with an acid anhydride-cured fused silica powder-filled epoxy resin 1 for precoating.
Allow time to cure. During this filling and curing period, the resin 1 can be cured while remaining in the sealing portion due to its viscosity and surface tension. Therefore, it is desirable to keep the resin layer horizontal during that period. After curing, remove the iron piece 7 from the sealing part and place it on the circuit board 4 approximately as shown in FIG. 5 (Jl) (b). A semiconductor device having a rectangular area shape of 10 hexagons and a thickness of 1.5 fi is obtained, which is thin and flat and resin-sealed.
このように本実施例によれば、四角形の封止面積形状の
先端部を持つ鉄片７と回路基板４との間の封止を必要と
する部分に封止樹脂を充填しこれを滞留した状態のまま
硬化したので、四角形の面積形状を有し、かつフラット
な樹脂封止ができる。As described above, according to the present embodiment, the sealing resin is filled in the portion that requires sealing between the iron piece 7 having a tip having a rectangular sealing area shape and the circuit board 4, and is retained therein. Since it is cured as it is, a flat resin seal having a rectangular area shape can be obtained.
また、封止の面積、形状については封止部上側の対向物
の形で定まるが、封止樹脂の多いときは封止部からのは
み出しを生じ、スルないときには封止の形に対し、ワン
ド状に欠肉状態となる。そして、封止樹脂の重力が表面
張力より大きいときには、対向する隙間より流れ出すの
で、厚肉の封止をすることは困難である。しかし、目的
とする薄肉、フラット封止には十分有用な方法で２ｗ厚
さ位までであれば本実施例のように従来から用いられて
いたプリコート樹脂はそのまま通用できる。In addition, the area and shape of the seal are determined by the shape of the object above the sealing part, but if there is a large amount of sealing resin, it will protrude from the sealing part, and if it does not come through, the wand will not fit the shape of the seal. It becomes a state of lack of flesh. When the gravity of the sealing resin is greater than the surface tension, it flows out from the opposing gap, making it difficult to achieve thick sealing. However, the precoat resin conventionally used as in this embodiment can be used as is, as long as the thickness is up to about 2W, which is a sufficiently useful method for the desired thin and flat sealing.
また、本実施例では封止樹脂は硬化時に対向するフラッ
ト面については自由に動けないが、側面がフリーとなっ
ているため、封止樹脂は硬化時に自由に収縮することが
可能で、硬化収縮にともなう内部応力の発生も小さくす
ることができる。In addition, in this example, the sealing resin cannot move freely on the opposing flat surfaces during curing, but since the side surfaces are free, the sealing resin can freely contract during curing, allowing for curing shrinkage. The generation of internal stress accompanying this can also be reduced.
第２図ないし第４図は本願の第２の発明の一実施例によ
る半導体装置の製造方法を説明するためのものであり、
第２図は一対の板状又は柱状の形状規制体の間でフィル
ムキャリアに接続された半導体素子を樹脂封止している
状態を示す断面図、第３図（ａ）はフィルムキャリアの
平面図、（ｂ）はその断面側面図、第４図は半導体素子
をフィルムキャリアのインナーリード部に接続した状態
を示す断面図である。第１図、第８図と同一符号は同−
又は相当部分を示す。2 to 4 are for explaining a method for manufacturing a semiconductor device according to an embodiment of the second invention of the present application,
Figure 2 is a cross-sectional view showing a state in which a semiconductor element connected to a film carrier is sealed with resin between a pair of plate-shaped or columnar shape regulating bodies, and Figure 3 (a) is a plan view of the film carrier. , (b) is a cross-sectional side view thereof, and FIG. 4 is a cross-sectional view showing a state in which a semiconductor element is connected to an inner lead portion of a film carrier. The same symbols as in Figures 1 and 8 are the same.
or a corresponding portion.
この方法では、第４図に示すようなフィルムキャリア６
に接続された半導体素子２を、第１図に用いたと同様の
鉄片７を１．５鶴の間隔をあけて平行に対向させ、その
間に該素子２を含む封止すべき部分が位置するようにセ
ントし、該部分にプリコーート用酸無水物硬化溶融石英
粉末充填エポキシ樹脂１を充填し、この状態で１５０℃
で３時間硬化させる。この充填・硬化期間は上記実施例
と同様に樹脂層を水平状態に保つことが望ましい。硬化
後、鉄片７を封止部よりはずし、第６図（ａ） （ｂｌ
に示すようにインナーリード５ａを含む厚さ１．５ Ｍ
、。In this method, a film carrier 6 as shown in FIG.
The semiconductor element 2 connected to the semiconductor element 2 is placed in parallel with iron pieces 7 similar to those used in FIG. Filled with epoxy resin 1 filled with acid anhydride-cured fused quartz powder for precoating, and heated at 150°C in this state.
Let cure for 3 hours. During this filling and curing period, it is desirable to keep the resin layer in a horizontal state as in the above embodiment. After curing, the iron piece 7 is removed from the sealing part, and the iron piece 7 is removed from the sealing part.
As shown in the figure, the thickness including the inner lead 5a is 1.5 M.
,.
約８寵角の四角形の面積形状を有し、かつ薄肉。It has a rectangular shape of about 8 angles and is thin.
フラットに樹脂封止された半導体装置を得る。A flat resin-sealed semiconductor device is obtained.
このように本実施例では、封止部の上下に四角柱状の鉄
片７を相互に対向するよう配置し、その間隙に素子２を
配置してこれに樹脂ｌを充填してこれを滞留した状態の
まま硬化するようにしたので、四角形の面積形状を有し
、かつフラットに樹脂封止できる。また、上記実施例と
同様に封止部が２鶴厚さ位までであれば本実施例のよう
に従来から用いられていたプリコート樹脂はそのまま通
用できる。さらに本実施例では、封止樹脂は上記実施例
と同様に側面がフリーとなっているため、′硬化収縮に
ともなう内部応力の発生も小さくすることができる。As described above, in this embodiment, the rectangular prism-shaped iron pieces 7 are arranged above and below the sealing part so as to face each other, and the element 2 is arranged in the gap between them, and the resin 1 is filled and retained therein. Since it is cured as it is, it has a rectangular area shape and can be flatly sealed with resin. Further, as in the above embodiment, if the sealing portion is up to about 2 mm thick, the precoat resin conventionally used as in this embodiment can be used as is. Furthermore, in this embodiment, since the side surfaces of the sealing resin are free as in the above embodiments, the generation of internal stress due to curing shrinkage can also be reduced.
なお、上記２つの実施例では封止すべき面積。In addition, in the above two embodiments, the area to be sealed.
形状の先端部をもつ形状規制体に四角柱の鉄片を用いた
が、材質的には金属、ガラス、セラミックスなど硬化時
の熱に耐えうるちのであれば特に限定されるものではな
い、さらに形状的には柱状体に限らず板状体でもよい、
又封止の面積、形状も対向する物体の先端部の形状に追
従するので円形。A rectangular prism iron piece was used as the shape regulating body with a shaped tip, but the material is not particularly limited as long as it can withstand the heat during curing, such as metal, glass, and ceramics. Specifically, it is not limited to columnar bodies, but may also be plate-shaped bodies.
Also, the area and shape of the seal follow the shape of the tip of the opposing object, so it is circular.
楕円形、長方形など任意の面積、形状にすることができ
る。It can be made into any area or shape, such as an oval or a rectangle.
また、上記２つの実施例では回路基板上でのプリコート
による半導体素子の封止及びフィルムキャリア両面での
半導体素子の封止の例を示したが、特にこれに限定され
るものではなく、リードフレーム上での封止等にも適用
できる。Furthermore, in the above two embodiments, examples of sealing the semiconductor element by precoating on the circuit board and sealing the semiconductor element on both sides of the film carrier are shown, but the present invention is not limited to this. It can also be applied to sealing etc.
以上のように、本発明によれば、回路基板等と所望の面
積形状を有するフラットな先端部を持つ形状規制体との
間に、またはかかる２つの尊影状規制体間に封止樹脂を
その表面張力を利用して充填し、これを加熱硬化するよ
うにしたので、半導体素子を特定の形状に、しかも薄肉
、フラ７）に封止ができ、高密度集積回路の構成上、非
常に有用な半導体装置の製造方法を得ることができる効
果がある。As described above, according to the present invention, a sealing resin is placed between a circuit board, etc. and a shape regulating body having a flat tip having a desired area shape, or between such two shadow-like regulating bodies. Since it is filled using surface tension and then heated and cured, it is possible to seal the semiconductor element in a specific shape with a thin wall (7), which is extremely useful in the construction of high-density integrated circuits. This has the advantage that a method for manufacturing a semiconductor device can be obtained.
第１図は本願の第１の発明の一実施例による半導体装置
の製造方法を説明するための断面側面図、第２図は本願
の第２の発明の一実施例による半導体装置の製造方法を
説明するための断面側面図、第３図（ａ）はフィルムキ
ャリアの平面図、第３図中）はその断面側面図、第４図
はフィルムキャリアに接続された半導体素子を示す断面
側面図、第５図（ａ）、 （ｂ）及び第６図（ａｌ、
（ｂ）は第１図及び第２図から樹脂の硬化後、板又は柱
状物を取除いた樹脂封止された半導体素子部分の状態を
示す斜視図及び断面側面図、第７図は従来の回路基板上
で回路に接続された半導体素子をプリコートした状態を
示す断面側面図、第８図は従来のフィルムキャリアに接
続された半導体素子部を封止した状態を示す断面側面図
である。FIG. 1 is a cross-sectional side view for explaining a method of manufacturing a semiconductor device according to an embodiment of the first invention of the present application, and FIG. 2 shows a method of manufacturing a semiconductor device according to an embodiment of the second invention of the present application. 3(a) is a plan view of the film carrier, FIG. 3(a) is a sectional side view thereof, FIG. 4 is a sectional side view showing a semiconductor element connected to the film carrier, Figure 5 (a), (b) and Figure 6 (al,
(b) is a perspective view and a sectional side view showing the state of the resin-sealed semiconductor element portion after the resin has hardened and the plate or columnar object has been removed from FIGS. 1 and 2, and FIG. 7 is a conventional FIG. 8 is a cross-sectional side view showing a precoated state of a semiconductor element connected to a circuit on a circuit board, and FIG. 8 is a cross-sectional side view showing a sealed state of a semiconductor element connected to a conventional film carrier.
Claims (2)
脂にて封止する半導体装置の製造方法において、封止す
べき面積、形状の先端部を有する形状規制体をその先端
部が上記半導体素子を含む封止すべき部分の上方に位置
するよう設置し、上記回路基板等と上記形状規制体との
間隙に封止樹脂を充填し、該封止樹脂を加熱してこれを
硬化することを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a semiconductor element mounted and connected on a circuit board, etc. is sealed with resin, a shape regulating body having a tip with an area and shape to be sealed is used, the tip of which is It is installed so as to be located above the part to be sealed including the semiconductor element, and the gap between the circuit board, etc. and the shape regulating body is filled with a sealing resin, and the sealing resin is heated to harden it. A method for manufacturing a semiconductor device, characterized in that:
半導体素子を樹脂にて封止する半導体装置の製造方法に
おいて、封止すべき面積形状の先端部を有する２つの形
状規制体をその先端部が相互に対向するよう設置し、そ
の間隙に上記半導体素子を含む封止すべき部分を位置さ
せて該間隙に封止樹脂を充填し、該封止樹脂を加熱して
これを硬化することを特徴とする半導体装置の製造方法
。(2) In a method for manufacturing a semiconductor device in which a semiconductor element connected to a film carrier or the like via a lead is sealed with a resin, two shape regulating bodies each having a tip having an area shape to be sealed are attached to the tip of the semiconductor device. are placed so as to face each other, a portion to be sealed including the semiconductor element is positioned in the gap, the gap is filled with a sealing resin, and the sealing resin is heated to cure it. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27755884A JPS61158151A (en) | 1984-12-28 | 1984-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27755884A JPS61158151A (en) | 1984-12-28 | 1984-12-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61158151A true JPS61158151A (en) | 1986-07-17 |
Family
ID=17585196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27755884A Pending JPS61158151A (en) | 1984-12-28 | 1984-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61158151A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089440A (en) * | 1990-03-14 | 1992-02-18 | International Business Machines Corporation | Solder interconnection structure and process for making |
-
1984
- 1984-12-28 JP JP27755884A patent/JPS61158151A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089440A (en) * | 1990-03-14 | 1992-02-18 | International Business Machines Corporation | Solder interconnection structure and process for making |
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