JPS61157027A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To decrease an error of an integration value of a frequency division signal even when a power failure takes place by providing the 1st frequency division circuit obtaining a frequency division output when a half of the count is counted and the 2nd frequency division circuit causing the same frequency division output state with the input of a reset signal the same as the reception of the 1st frequency division output. CONSTITUTION:When a measurement signal S is inputted, a 2/8 frequency division circuit 10 outputs one pulse every time 4 pulses of the signal S are counted and a frequency division output B1 is obtained. When the frequency division output is inputted to a 1/2 frequency division circuit 11, a frequency division output B2 is obtained. During the frequency division, when a power failure takes place at a time t1 and power is applied again at a time t2, a reset signal R is inputted at the time t2. Thus, the frequency division output state of the circuit 10 is brought forcibly to a high level, that is, the frequency division output as a time (time tc) when a half of 8 pulses of the measuring signal S is counted. Further, the frequency division state of the 1/2 frequency division circuit 11 is made identical to the frequency division output state receiving the frequency division output B1 at a time (time tc) when the circuit 10 counts 4 pulses. Thus, in the operation after power reapplication, the measuring signal S undergoes frequency division so that four pulses of the signal S are counted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a frequency dividing circuit that divides the frequency of a measurement signal to obtain an integrated amount of electricity, gas, water, etc.

[Technical background of the invention]

For example, when calculating the integrated amount of electric power, an electronic watt-hour meter is used, and this watt-hour meter is equipped with a frequency dividing circuit. FIG. 4 is a block diagram of the electronic power countermeasure. This watt-hour meter is a power-frequency conversion circuit (hereinafter referred to as "power-to-frequency conversion circuit") that receives a voltage signal ■ proportional to the load voltage and a voltage signal I proportional to the load current to determine the electric power, and then converts it into a frequency signal Fa proportional to the electric power. , W/V conversion circuit) 1 is provided, and a frequency signal Fa output from this conversion circuit 1 is sent to a frequency dividing circuit 2. The frequency signal Fb frequency-divided by the frequency dividing circuit 2 is sent to the integration display section 3, where it is integrated and displayed as the amount of power used.

Here, the power supply circuit 4 supplies power VQ to the W/V conversion circuit 1, frequency division circuit 2, and integration display section 3, respectively, and at the same time, it supplies a reset signal R to the frequency division circuit 2 when power is supplied. Has the ability to perform. FIG. 5a is a circuit diagram showing an example of a reset signal generating circuit. This circuit is composed of a series circuit of a resistor RO and a capacitor C, and the voltage across the capacitor C is used as the reset signal R. Therefore, the reset signal R exhibits a voltage change with a characteristic as shown in FIG. 5b. Therefore, when a low-level (L-level) voltage is used as the reset signal R, the reset time is determined from multiple values of the resistor RO and the capacitor C and becomes tr. Therefore, this reset signal R is output to the frequency dividing circuit 2 when the power is turned on.

[Problems with background technology]

However, in the above circuit, when a power outage occurs and the power is turned on thereafter, an uncounted frequency signal Fa is generated. That is, if the frequency dividing circuit 2 has a frequency division ratio of (1/n), a frequency signal Fb that outputs one pulse is output every time n pulses of the frequency signal Fa are input. Therefore, as shown in FIG. 6, when a power outage (power supply cutoff) occurs during the Tg bright period, the frequency dividing circuit 2 newly starts frequency division as the first pulse.

As a result, Tf light period pulses are no longer counted. Thus, there is a problem in that the error in displaying the amount of power used by an electronic watt-hour meter increases as the number of power outages increases.

[Purpose of the invention]

The present invention has been made based on the above-mentioned circumstances, and an object thereof is to provide a frequency dividing circuit that can minimize the error in the integrated value of the frequency divided signal even if a power outage occurs.

[Summary of the invention]

The present invention provides a first frequency dividing circuit that receives a measurement signal and obtains a final frequency-divided signal, obtains a frequency-divided output when counting half of the number of counts of the measurement signal, and enters an initial state upon input of a reset signal; The frequency division output state is forced by the input of the reset signal, and the first frequency division circuit obtains the final frequency division signal by counting half the number of counts of the measurement signal. This frequency dividing circuit minimizes the integrated value error by providing a second frequency dividing circuit whose output state is the same as that of the output state.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a frequency dividing circuit according to the present invention. In the figure, 10 is a 2/n frequency divider circuit, which inputs the measurement signal S of electricity, gas, water, etc. to the clock input terminal (hereinafter referred to as CK input terminal) and outputs the frequency divided signal from the Q output terminal. The reset signal R is the clear terminal (CL).
, the frequency division output state is the frequency division output state when half of the count number of the measurement signal S from which the final frequency division signal B2 is obtained is counted. Note that n is a positive even number. 11 is a 1/2 frequency divider circuit using a flip-flop, which divides the frequency divided output B1 of the 2/n frequency divider circuit 10 into G
It receives the frequency divided output B2 from the Q output terminal in response to the K input terminal, and the reset signal R is sent to the preset input terminal (PR).
When input to 2/n frequency divider circuit 10, the frequency divided output state is
The state of the frequency-divided output is the same as the state of the frequency-divided output when the frequency-divided signal is counted by half the count number of the measurement signal to obtain the final frequency-divided signal B2. 2.13 is a flip-flop, and 14 is an inverter. These flip-flops 12.13 and the inverter 14 create a frequency-divided output signal SO having a predetermined pulse width. In other words,
The flip-flop 12 inputs the final frequency-divided signal B2 to the GK input terminal to obtain a frequency-divided output signal So having a level corresponding to this input signal, and the flip-flop 13 inputs the frequency-divided output signal SO to the D input terminal. At the same time, the measurement signal SK that comes through the inverter 14 is input to the CK input terminal, output 2 corresponding to these signals is output from the 100 output terminal, and this is sent to the clear terminal (CL) of the 7-lip flop 12 to generate a pulse. Setting the width.

Next, the operation of the circuit configured as described above will be explained with reference to the operation timing diagram shown in FIG.

The frequency division ratio of this frequency divider circuit will be explained as (1/8), and in this case, the frequency division ratio of the 2/n frequency divider circuit will be <2/8).
becomes. When the measurement signal S is input, the 2/8 frequency divider circuit 10
outputs one pulse every time the measurement signal S is counted four pulses to obtain a divided output B1 that outputs two pulses every eight pulses.

When this frequency-divided output is input to the 1/2 frequency divider circuit 11, it becomes 1/2.
The frequency dividing circuit 11 divides the frequency into 1/2 to obtain a frequency divided output B2.

Then, this frequency divided signal B2 is the C of the flip 70 tube 12.
When input to the K input terminal, the frequency-divided output signal So output from the flip-flop 12 becomes high level. However, since the measurement signal SK inverted by the inverter 14 is input to the GK input terminal of the flip-flop 13 that receives this frequency-divided output signal, a low-level signal Z is sent from the flip-flop 13 to the clear terminal of the flip 70 tube 12. It will be done.

As a result, the frequency-divided output signal SO has the same pulse width as one pulse width of the measurement signal S. In this way, a frequency-divided output signal SO whose frequency is divided by 1/8 is obtained from the frequency divider circuit.

Now, during the above frequency dividing operation, a power outage occurs at time t1, and t22
Assume that the power is turned on again. Then, the t22 time reset signal R is input. Then, 2/8 frequency divider circuit 1
The divided output state of o is forced to high level, that is, when half of the 8 pulses of the measurement signal S is counted (time tc)
This is the same as the divided output state of . On the other hand, 1/2 frequency divider circuit 1
In the frequency division output state of 1, the 278 frequency division circuit 10 is forced to output 4.
The frequency division output state is the same as the frequency division output state when the frequency division output B1 is received when pulses are counted (time tc). Therefore, in the operation after the power is turned on again, the pulses of the measurement signal S are already counted by four pulses and the frequency is divided.

Now, a case where the frequency dividing circuit having the above configuration is applied to an electronic watt-hour meter will be explained with reference to FIG.

In the figure, 20 is a W/F conversion circuit, 21 is an integration display section, 22 is a pulse oscillator, and 23 is a power supply circuit.

24 and 25 are frequency dividing circuits having the same configuration as in the above embodiment. With such a configuration, each time a power outage occurs and the number of power outages increases, the total error in the amount of power used displayed by the integration display section 21 approximates rOJ and becomes an accurate value. Note that this is because the power outage does not occur only once. Along with this, the error in the pulse signal of the electric power output from the pulse oscillator 22 also approximates to "o".

In this way, in the above embodiment, the input of the reset signal R forces the frequency division output state to be the same as the frequency division output state when half of the count number of the measurement signal S is counted to obtain the final frequency division signal B1. A 2/8 frequency divider circuit 10,
The divided output state is forced to 2 by inputting the reset signal R.
The measurement signal S from which the /8 frequency divider circuit 10 obtains the final frequency-divided signal B1
Frequency division output B when counting only half of the number of counts
Since the configuration includes a 1/2 frequency divider circuit 11 that has the same frequency divided output state as when 1 is received, the frequency division operation when the power is turned on again after a power outage obtains the final frequency divided signal. The frequency-divided output state is forced to be the same as when counting 4 pulses, which is half of the 8-pulse count. Therefore, as the number of power outages increases, the integrated value error of the frequency-divided output signal SO will decrease to the minimum value r
Approximate to OJ. In other words, the timing of power outages varies, and therefore, if the number of power outages increases by always keeping half-counted, the pulses that should be counted and the pulses that should not be counted will cancel each other out. Therefore, the integrated value error decreases to "±(1/n)~0". In addition, in the above-mentioned example, it is 1/8 to 0.

Also, there is a method that does not reset the frequency divider circuit, but
For integrated circuits such as flip-flops (ICs), even if an initial state is not given, the state at power-on differs depending on each IC, so it has been difficult to approximate the pulse that causes error at each power outage to rOJ. However, In the above embodiment, the error can be approximated to rOJ.

It should be noted that the present invention is not limited to the above-mentioned embodiment, but can also be applied to the case of calculating the integrated value of measurement signals of gas, water, etc.

〔Effect of the invention〕

According to the present invention, the first frequency dividing circuit receives the measurement signal and obtains the final frequency division signal.The first frequency division circuit obtains the frequency division output when counting half of the number of counts of the measurement signal, and enters the initial state by inputting the reset signal. When the frequency division output state is forcibly changed by the input of the reset signal, the first frequency division circuit receives the frequency division output when the first frequency division circuit has counted half of the count number of the measurement signal to obtain the final frequency division signal. Since the second frequency dividing circuit is provided which has the same frequency output state as the frequency divided output state, it is possible to provide a frequency dividing circuit that can minimize the error in the integrated value of the frequency divided signal even if power supply is cut off.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the frequency dividing circuit according to the present invention, FIG. 2 is an operation timing diagram of the circuit shown in FIG. 1, and FIG. 3 is an electronic version of the frequency dividing circuit shown in FIG. A configuration diagram when applied to a watt-hour meter, Figure 4 is a configuration diagram of an electronic watt-hour meter to which a conventional frequency dividing circuit is applied, and Figure 5 (a) is a configuration diagram of a reset signal generation circuit. (,b) is a characteristic diagram of a reset signal generating circuit, and FIG. 6 is an explanatory diagram of the operation of a conventional frequency dividing circuit. 10...1/n frequency divider circuit, 11...1
/2 frequency divider circuit, 12.13...Flip 70 tube, 14...Inverter. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (1)

[Claims] In order to calculate the cumulative amount of electricity, gas, water, etc.,
In a frequency dividing circuit that divides the frequency of a measurement signal for gas and water, a final frequency division signal is obtained by receiving the measurement signal, a frequency division output is obtained when half of the count number of the measurement signal is obtained, and a reset signal is input. a first frequency divider circuit which is in an initial state, receives the divided output of the first frequency divider circuit, divides the frequency at a predetermined frequency division ratio to obtain the final frequency divided signal, and generates the reset signal. The frequency division output state is forcibly changed by the input to the frequency division output state when receiving the frequency division output when the first frequency division circuit has counted half of the count number of the measurement signal to obtain the final frequency division signal. 1. A frequency dividing circuit comprising a second frequency dividing circuit that is identical to the second frequency dividing circuit, and minimizing an integrated value error of a final frequency divided signal even if power supply is cut off.