JPS61157024A - Protection circuit of transistor - Google Patents

Abstract

PURPOSE:To form a protection circuit for a transistor (TR) with excellent power supply effect and small heat sink by bringing the TR into a nonconductive (cut-off) state when it is detected than an overcurrent flows to the TR. CONSTITUTION:When an overcurrent flows to a load 7, a drain current of an FET5 increases but since a gate voltage is constant, a drain-source voltage is increased by the constant current characteristic of the FET and a part of the overcurrent is inputted to an AND gate 15 via a resistor 9. Since a voltage at an output terminal Q is at a high level when the FET5 is turned on, the input of the AND gate 15 goes to a high level, resulting that the output of the AND gate 15 goes to a high level. Since the high level signal is inputted to a reset terminal R of a D flip-flop 3, the D flip-flip 3 is reset, the voltage at the output terminal Q goes to a low level attended therewith and the FET5 is cut off. Thus, the FET5 is cut off at overcurrent and the power consumption is a power required for the cut-off only, the power consumption is less and the heat sink is decreased.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a protection circuit for transistors.

[Technical Background of the Invention] A field effect transistor will be explained below as a switching circuit.

Conventionally, there is a circuit as shown in FIG. 6 that uses a field effect transistor (hereinafter referred to as FET) as a switching element and is equipped with a protection circuit for preventing overcurrent.

In FIG. 6, a power source 501 is connected to a pulse generator 503 and a load 505, and the other end of the load 505 has F'E
The drain OR of T 507 is connected.

A resistor 509 for voltage measurement is provided at the source S of the FET 507. Gate G of FET 507 is pulse generator 5
03, and a pulse voltage from a pulse generator 503 is applied. A transistor 5110 base B is connected between the resistor 509 and the source S of the FET 507, and the collector C of this transistor 511 is connected to the pulse generator 5.
It is connected to the output of 03. The emitter E of the transistor 511 is connected to the negative side of the power supply 501.

That is, the FET 507 is turned on and off according to the pulse voltage from the pulse generator 503, and performs the function of switching the load 505, and the transistor 511 is for overcurrent detection.

Next, the operation will be explained. When the FET 507 is on and overcurrent flows through the load 505, the potential difference between the resistor 509 and the negative side of the power supply increases, and this potential difference becomes the base voltage of the transistor 511.
becomes conductive. As a result, the current applied to the gate G of the FET 507 decreases, and the current applied to the load 505 also decreases, and the current-carrying circuit of the load 505 becomes non-conductive.

[Problems with the Background Art] The circuit shown in FIG. 6 has the following problems.

■ Even during overload, current flows through FET 507, consuming power equal to the product of drain current and drain-source voltage.
Because it generates heat, it was necessary to install a large radiator or the like to dissipate the heat.

■ Since current is always applied to the resistor 509, the load 505 is supplied with a voltage that is the power supply voltage minus the voltage applied to the resistor 509, which causes a deterioration in the efficiency of power supply. Ta.

[Object of the Invention] The present invention has been made in view of the above, and an object of the present invention is to provide a transistor protection circuit with a small heat dissipation facility and with good power supply efficiency.

[Summary of the Invention] To achieve the above object, in a circuit that forms a power supply path to a load when a transistor is conductive, the present invention provides a conduction control means for controlling supply of a conduction signal to a conduction control terminal of the transistor; The gist includes an overcurrent detection means for detecting that an overcurrent is flowing through the transistor, and a conduction signal cutoff means for cutting off the supply of the conduction signal when an overcurrent is detected during the supply of the conduction signal. do.

Embodiments of the present invention] Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 shows a first embodiment of the present invention.

In the figure, 1 is a pulse generator, and this pulse generator 1 is connected to a clock input terminal GK of a D-type flip-flop 3 (hereinafter referred to as D flip-flop).

The output terminal d of the D flip 70 tube 3 is connected to the input terminal, and the output terminal Q is connected to the gate G of the FET 5.

On the other hand, one end of a resistor 9 is connected between the load 7 and the drain DR of the FET 5, and one end of the input terminal of a two-person AND gate (hereinafter referred to as AND gate) 15 is connected to the other end of this resistor 9. It is connected.

This AND gate 15 has the other end of its input terminal connected to the D
It is connected to the output terminal Q of the flip-flop 3, and its output is connected to the reset terminal R of the D flip 70 tube 3.

Next, the operation of this embodiment will be explained using FIGS. 2 and 3. In addition, <a) in FIGS. 2 and 3,
, (b), (C), (d >, (e).

(f) is the clock input terminal GK, output terminal Q, and input terminal D (i.e., output terminal σ) during normal and overload conditions, respectively.
, drain current ID, drain-source voltage VDS,
3 is a time chart of signals of various parts of the output of the AND gate 15. FIG.

When a pulse voltage is applied to the clock input terminal GK (Fig. 2 (a)), the voltage becomes a high level at the output terminal Q and a low level at the output terminal d (Fig. 2 (b) and (C). )). At this time, a voltage is applied to the gate G of the FET 5, so the FET 5 is turned on.

When the next pulse voltage is applied to the clock input terminal GK, the voltage at the input terminal is latched, and since the voltage at the input terminal is at a low level at this time, the voltage at the output terminal Q is at a low level. Accordingly, the voltage at the output terminal σ becomes high level. At this time, no voltage is applied to the gate G of FET5, so FET5 is in an off state ((a) in Figure 2).
,(b).

(C)). That is, the D flip-flop normally functions as a 1/2 counter.

In this way, in the operation of the flip-flop 3, F
E 1” Rated current io to load 7 when 5 is on.

When the voltage is flowing, the drain-source voltage is not abnormally high (rated voltage Vo So), and the AND gate]5
The output of is at a low level (Fig. 2 ([)).

In such a state, if an overcurrent flows through the load 7,
Although the drain current of FET5 increases (Fig. 3(d)
Since the gate voltage is constant, the FET
Due to the constant current characteristic of , the voltage between the drain and the source increases to the level VDS× in FIG. F
When the ET5 is on, the voltage at the output terminal Q is also at a high level, so both the inputs of the AND gate 15 are at a high level, and as a result, the output of the AND gate 15 is also at a high level (FIG. 3 ([)). This high-level signal is input to the reset terminal R of the D flip-flop 3, so the D flip-flop 3 is reset, and accordingly, the voltage at the output terminal Q also becomes low level (Fig. 3 (b > (c) )),
FET5 is turned off. However, when an overcurrent flows, FET 5 is turned off, and load 7 and FET 5 are turned off.
5, no current is applied to both.

Therefore, in the event of an overcurrent, the FET 5 is cut off and the power consumption at this point is only the power required for cut-off, so power consumption is lower than in the past, and the heat dissipation equipment can also be made smaller.

Further, the resistor 509 (FIG. 6) for voltage measurement as in the conventional example is not required, and the power consumed by this resistor 509 is eliminated, so that the efficiency of power supply is improved.

FIG. 4 shows a second embodiment of the present invention, in which two FETs are used as switching elements to perform push-pull operation.

As shown in the figure, the upper end of the coil 301 as a load
Connected to the drain DRI of ET303, the FET30
The source S1 of 3 is grounded, and the gate G1 is
It is connected to the output terminal Q1 of the knob 305.

The lower end of the coil 301 is connected to the drain OR2 of the FET 307, the source S2 of the FET 307 is grounded, and the gate G2 is connected to the output terminal Q2 of the D flip-flop 309.

Resistors 311 and 313 are connected to the drains DR1 and DR2 of the FETs 303 and 307, respectively. Resistance 311.31
The other end of 3 is input to an OR circuit 315 indicated by a dotted line. This OR circuit 315 is a well-known one, and the diode 3
17.319 and resistor 321.323, resistor 3
The other end of 23 is connected to negative voltage level -Vcc. The output of the OR circuit 315 is the D flip-flop 305, 30
It is connected to the reset terminals R1 and R2 of 9.

The output of the push-pull signal generator 325 is connected to the input terminal D2 of the D flip-flop 309 and to the input terminal D1 of the D flip-flop 305 via an inverter 327. The pulse generator 329 is a D flip-flop 3
05, 309, each clock input terminal CK1. GK2
connected to.

Next, the operation of this embodiment will be explained. Figure 5(a)
5(e) are time charts of signals of each part of this embodiment, FIG. 5(a) shows the input signal input to the input terminal D1 of the D flip-flop 305, and FIG. 5(b) shows the input signal input to the input terminal D1 of the D flip-flop 305. The input signal input to the input terminal D2 of 309, FIG. 5(C) is the pulse signal generated from the pulse generator 329, and FIG.
5(e) is the output signal of the output terminal Q2 of the D flip-flop 309. FIG.

The push-pull signal generator 325 generates a signal as shown in FIG. It is input to D1 (FIG. 5(a)).

A pulse signal as shown in FIG. 5(C) is applied to clock input terminals CKI and GK2 of the D flip-flop 305.309, and the D flip-flop 305.309
Then, due to the rising edge of the clock signal in Fig. 5(C), D
Since the human power signal D1 and the human power signal D2 are latched, the output terminals Q1. The output signals of Q2 are as shown in FIG. 5(d) and FIG. 5(e).

Output terminal Q1. The output signal from Q2 is connected to each FET305.
, 307, but the Q11 output signal and 02
Since the output signal is inverted, when FET 305 is on, FET 307 is off, and conversely, when FET 305 is off, FET 307 is on. In this way, FET 305 and FET 307 perform push-pull operation.

Therefore, when no overcurrent flows through the load 301,
A normal current flows through FETs 303 and 307, and this current is blocked by resistors 311 and 313, so the inputs of the OR circuit 315 both become low level, so the reset terminals R1 and R2, which are the outputs of the OR circuit 315, Both input signals also become low level.

On the other hand, when an overcurrent flows through the load 301, the FET 303.
An overcurrent flows through one of the resistors 307, and the current causes the input of the OR circuit 315 to go to a high level through the resistor 311 (or resistor 313).

When an overcurrent flows in this way, one of the inputs of the OR circuit 315 becomes high level, so the input signals of the reset terminals R1 and R2, which are the outputs of the OR circuit 315, both become high level, and the D flip-flops 305 and 309 become high level. Both are reset, the outputs of output terminals Q1 and Q2 become low level, and F
ET303,307 will be turned off together to cut off the overcurrent flow.

[Effects of the Invention] As explained above, according to the present invention, in a circuit that forms a power supply path to a load when a transistor is conductive,
Since the transistor is configured to be in a non-conducting (cutoff) state when it is detected that an overcurrent is flowing through the transistor, the heat dissipation equipment is smaller than in the past, and the efficiency of power supply is improved. A protection circuit for transistors can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIGS. 2 and 3 are time charts showing the operation of the first embodiment, and FIG. 4 is a circuit diagram of a second embodiment of the present invention. FIG. 5 is a time chart showing the operation of the second embodiment, and FIG. 6 is a circuit diagram of the conventional example. 3.305.309...D flip-flop 5.30
3.307...FEI 7.301...Load 15...AND circuit 315.
...OR circuit diagram 1 cc

Claims (2)

[Claims] (1) In a circuit that forms a power supply path to a load when the transistor is conductive, a conduction control means that controls supply of a conduction signal to the conduction control terminal of the transistor, and a circuit that detects that an overcurrent is flowing through the transistor. 1. A protection circuit for a transistor, comprising overcurrent detection means and conduction signal cutoff means for cutting off supply of the conduction signal when an overcurrent is detected during supply of the conduction signal. (2) The transistor is a field effect transistor, and the overcurrent detection means detects an overcurrent when the drain voltage of the field effect transistor increases beyond a predetermined value. A protection circuit for the transistor described in .