JPS61157019A - 90× phase-shifting circuit - Google Patents

Abstract

PURPOSE:To attain accurate 90 deg. phase shift by connecting a phase delay compensating circuit comprising a level adjusting resistor and the 2nd common base transistor (TR) to the input of a phase shift circuit not at the side of a common base TR of a differential amplifier of the post-stage. CONSTITUTION:An output of a common collector TRQGC is fed to a phase shift capacitor CHS and to the common base TRQC through a level adjusting resistor RLA. In this case, the emitter potential of the common collector TRQGC and that of the common base TRQC are made equal so as not to flow a bias current to the level adjusting resistor RLA, then the emitter current of the common base TRs QC, QGB is made equal and the current from a constant current source comprising TRs Q3, Q4 is made equal, then the input to a differential amplifier DA due to temperature drift is not unbalanced.

Description

[Detailed description of the invention] Regarding sum circuits.

[Technical background of the invention]

Conventionally, as a 90 degree phase shift circuit, as shown in Fig. 3,
Capacitively coupled pace grounded transistor (amplifier)
QGB, collector grounded transistor (amplifier) Q
There are devices that manually generate signals using low output impedance circuits such as Go. This is because the capacitor CH8 causes the current flowing through the capacitor Cis to lead the input signal voltage by 90 degrees, thereby obtaining an output voltage phase-shifted by 90 degrees from the output terminal OUT. Unlike the LC phase shift circuit, this circuit has no frequency dependence in principle, so
Suitable for non-adjustment or especially for integrated circuits.

FIG. 4 shows an attempt to increase the output signal by combining the above circuit with a differential amplifier DA.

That is, the output terminal OUT shown in FIG. 3 is connected to the base of the first transistor Q of the differential amplifier DA, and the base of the second transistor Q is connected to the base of the first transistor Q1. The third and fourth transistors Q and Q4 and the resistor R are connected so that the same bias voltage is applied.
A current mirror circuit P8CV consisting of R1 and R1 is connected. Therefore, the output of the grounded base transistor QGB for phase shifting is further amplified by the differential amplifier DA, and the output terminals OUT and OU'r.

is output to.

[Problems with background technology]

However, the conventional 90 degree phase shift circuit as described above,
In fact, in order to obtain a sufficiently large output voltage, the load resistance R8 of the grounded base transistor QGB becomes large. Moreover, even if the differential amplifier DA is connected to the rear stage of the phase shift circuit as shown in FIG. 4, the load resistance R of the differential amplifier DA,
IR becomes large. As a result, the phase of the signal is delayed due to the high frequency characteristics of the transistor such as the collector output capacitance, and also due to the stray capacitance, making it impossible to perform an accurate 90 degree phase shift.

FIG. 5 shows the vectors of each part. That is, with the input voltage Vin as a reference, if the phase delay of the pace grounding transistor QaB is 01, its output voltage pegtor is ``I'', and the differential amplifier DAL:DA phase is 02, the output voltage and pressure vector v2 are θ1+02. 901i phase shift is not possible.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a 90-degree phase shift circuit that can compensate for phase delays caused by high frequency characteristics of transistors, etc.

[Summary of the invention]

That is, the 90-degree phase shift circuit according to the present invention is a differential amplifier connected to the latter stage of the phase shift circuit consisting of a phase shifting capacitor and a grounded base transistor (amplifier), which is not the grounded ground transistor (amplifier) gllI. Due to the human power of
An accurate 90 degree phase shift is made possible by connecting the output of a phase lag compensation circuit consisting of a level adjustment resistor and a second grounded transistor (amplifier).

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the circuit configuration. The base of Qoa is a collector-grounded transistor (amplifier) whose collector is grounded via the DC power supply VO, and the base of Qoa is the signal input terminal INK.
It is connected. The emitter of this transistor QGO is grounded via a resistor R0, and the base is connected to the emitter of a grounded base transistor (amplifier) QGB via a phase shifting capacitor CHEI, which is a grounded base transistor (amplifier) that is grounded via a DC power supply VB. has been done.

The collector of the grounded base transistor QGB is grounded via the resistor R1 and the DC power supply v00, and
It is connected to the base of the first transistor Q of the differential amplifier DA. And the second transistor Q of this differential amplifier DA.

The base of is grounded via the resistor R1 and the above 11i@Vaa. These first and second transistors Q
, and Q, are connected to ground via a current source IIe. Further, each collector is connected to the power supply VC via a resistor R4 or R3, and is also connected to an output terminal OUT.

Or OUT! It is connected to the.

The third and fourth transistors Q3 and Q4 are arranged so that the base of the second transistor Q2 receives the same bias voltage as the base of the first transistor Q.
, a current mirror circuit CV consisting of resistors RI and R1 is connected. That is, the base of the first transistor Q has an emitter that is grounded via a resistor R8, a base that is connected to the collector of the third transistor Q, which is common to the base of the fourth transistor Q4, and a base of the second transistor Q4. The base of the transistor Q is connected to the collector of a fourth transistor Q4, whose emitter is grounded via a resistor R, and whose base and collector are connected. However, in this case,
The first transistor Q is a grounded base transistor Q
GE is connected to the third transistor Q, and the second transistor Q is connected to the second transistor Q of the phase lag compensation circuit PLC.
Through the grounded base transistor (amplifier) Qa of
It is connected to the fourth transistor Q4.

That is, the phase lag compensation port @PLC' includes a second grounded base transistor QO and a level adjustment resistor RLA.
It consists of H2 grounded base transistor q
o has a common base with the grounded base transistor QGB, a collector connected to the base of the second transistor Q, and an emitter connected to the collector of the fourth transistor Q4. The level adjustment resistor RLA is the collector-grounded transistor Q.
It is interposed between the emitter of GG and the emitter of the second grounded base transistor Qc.

In the 901i phase shift circuit having such a circuit configuration, the output of the grounded collector transistor Qoa is supplied to the second grounded base transistor through the level adjustment resistor RLA in the same way as it is supplied to the phase shifting capacitor CH8. transistor qa
is also entered.

At this time, ideally, the collector grounded transistor QG
By making the emitter potential of C and the emitter itm of the second pace grounding transistor Qa equal to each other and preventing the bias voltage from flowing to the level adjustment resistor RLA, the emitter potential of the pace grounding transistors QO and QGB becomes equal.
the currents are equal, and the third and fourth transistors Q,
Since the currents of the constant current sources Q4 and Q4 can be made equal, the input balance of the differential amplifier DA will not be disrupted due to temperature drift.

The output of the second grounded transistor Qc is connected to the base of the second transistor Q of the differential amplifier DA while remaining in phase with the input 'Nozoda', and is added to the base of the first transistor Q. After being vector-combined and amplified with the phase-shifted output, the output terminals 0UT1 and 0UT2
is output to.

FIG. 2 shows a vector diagram of this phase shift circuit, and the vector V in the diagram is the output voltage phase when the phase is not compensated as in FIG. 5 above. Here, in the above phase shift circuit, if we consider the case where a signal is not input manually to the base of the first transistor Q1, in this case, it is transmitted to the second pace grounding transistor Qc via the level adjustment resistor RLA. Only the signal is input manually, and its collector output is shown as a vector V in the figure. The voltage represented by this vector V is inverted and amplified by the differential amplifier DA, and the output voltage becomes the vector v4. (However, in this case, the phase delay in each transistor amplifier is the same as in the case of FIG. 5.) That is, the voltage vectors v4 and V.

The composite vector is the output voltage vector of the entire phase shift circuit, and is indicated by V in the figure. However, the absolute value of the vector in ■4 must be adjusted so that the phase of ■ is 90 degrees with respect to the input voltage Via, which means that the absolute value of the vector in ■4 is IV41=, This is achieved by setting the value of the level adjustment resistor RLA so that /'i' vote Roroπ.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a 90-degree phase shift circuit that can compensate for phase delays due to high frequency characteristics or stray capacitance of transistors.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of a 901i phase shift circuit according to an embodiment of the present invention, FIG. 2 is a vector diagram of the phase shift circuit of FIG. 1, and FIGS. 3 and 4 are conventional 90 degree A diagram showing the circuit configuration of the phase shift circuit, FIG. 5 is a vector diagram of the phase shift circuit of FIG. 4. DA...differential amplifier, CM...current mirror circuit, PLO...phase lag compensation circuit, CH8...phase shift capacitor, QGBIQO...grounded base transistor (amplifier), QGO... Collector grounded transistor (amplifier), RLA...level adjustment resistor. Applicant's Representative Patent Attorney Takehiko Suzue First Cause Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] a low input impedance circuit into which an input signal is input; a phase shifting capacitor having one end connected to the output terminal of the low input impedance circuit; and a first reference having an emitter connected to the other end of the phase shifting capacitor. a first transistor whose base is connected to a potential point; and a differential amplifier whose one input terminal is connected to the collector of the first transistor and whose other input terminal is connected to a second reference potential point. become 90
The second transistor has a collector connected to the second reference potential point and a base connected to the first reference potential point, and one end of the second transistor is connected to the emitter of the second transistor. 9. A phase lag compensation circuit comprising a level adjustment resistor connected to the output end of the low input impedance circuit and the other end connected to the output end of the low input impedance circuit.
0 degree phase shift circuit.