JPS61156957A - Sine wave frequency detecting circuit - Google Patents

Sine wave frequency detecting circuit

Info

Publication number
JPS61156957A
JPS61156957A JP27738384A JP27738384A JPS61156957A JP S61156957 A JPS61156957 A JP S61156957A JP 27738384 A JP27738384 A JP 27738384A JP 27738384 A JP27738384 A JP 27738384A JP S61156957 A JPS61156957 A JP S61156957A
Authority
JP
Japan
Prior art keywords
output
input
sine wave
multiplier
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27738384A
Other languages
Japanese (ja)
Inventor
Tsutomu Hosokawa
勉 細川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27738384A priority Critical patent/JPS61156957A/en
Publication of JPS61156957A publication Critical patent/JPS61156957A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To attain the estimation of the frequency of the input sine wave by forming the circuit with a multiplier to which the output of a subtractor and that of the primary delay circuit are inputted and a signal processing part which consecutively renews its output and by making the output of the said processing part to be the secondary input to the said multiplier. CONSTITUTION:Delay circuits 10 and 11 that delay by a fixed time T are connected in series, whose respective outputs S1(t) and S3(t) are added by an adder 20 to obtain the output S4. Meanwhile, the output S2(t) from the delay circuit 10 and that 20 from a signal processing part 40 are multiplied by a multiplier 30, of which product that is S7(t) is subtracted by a subtractor 21 from the output S4(t) of the adder 20 to obtain an output S5(t). In the signal processing part 40, the output S5(t) of the subtractor 21 and that S2(t) of the delay circuit 10 are signal-processed so that the output S5(t) becomes smaller, for which the part 40 consecutively renews the output S6(t) of itself. From the value when this output signal S6(t) reaches the fixed value, the frequency of the input sine wave can be discriminated. In the result the input frequency can be discriminated regardless of the amplitude of the received input sine wave itself.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は単一周波数信号方式を使用するデータ伝送装置
の受信部における単一周波入力の正弦波周波数検出回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a sinusoidal frequency detection circuit for a single frequency input in a receiving section of a data transmission device using a single frequency signaling system.

〔従来技術〕[Prior art]

データ伝送装置の一つの方式として、単一周波数を使用
する方式があり、その代表例としてファクシミ’)の伝
送手順がある。CCITT(国際電信電話諮問委員会)
勧告のT、30において規定されているフェーズB、D
で使用する信号として、 G2ファクシミI7の場合に
は、単一周波数による信号方式が用いられる。
One type of data transmission apparatus is a system that uses a single frequency, and a typical example thereof is a facsimile transmission procedure. CCITT (International Telegraph and Telephone Consultative Committee)
Phases B and D as specified in Recommendation T.30
In the case of the G2 facsimile I7, a single frequency signal system is used as the signal used in the G2 facsimile I7.

従来、このような単−周波入力の周波数検出回路として
は、各周波数ごとにフィルタを内厳して検出するものや
、遅延検波によるものがある。後者の遅延検波による本
のを第1図に示す。第1図に示すものは、一定時間Tだ
け遅延させる遅延回路10と、乗算器30と、低域通過
フィルタ41とから構成されている。遅延回路1oの入
力5l(t)を単一周波数の正弦波とする。すなわち、
5t(tl=A−sinωt  (A :振幅、ω:角
周波数)その遅延回路の出力は次式で衣わされる。
Conventionally, such single-frequency input frequency detection circuits include those that detect each frequency by using a filter internally, and those that use delay detection. The latter method using delayed detection is shown in Figure 1. The circuit shown in FIG. 1 is comprised of a delay circuit 10 that delays by a fixed time T, a multiplier 30, and a low-pass filter 41. The input 5l(t) of the delay circuit 1o is a sine wave with a single frequency. That is,
5t (tl=A-sinωt (A: amplitude, ω: angular frequency) The output of the delay circuit is given by the following equation.

8(t−T)=A−sin[ω(t  T)]従って、
乗算器30の出力は となる。上式の第1項目は直流成分であシ、第2項は角
周波数2ωの交流成分である。従って、低域通過フィル
タ41により第2項の成分をカットすることによって、
第1項の成分のみ出力させることができる。すなわち、
低域通過フィルタ41ざは入力の振幅人と角周波数ωの
みに依存する。
8(t-T)=A-sin[ω(tT)] Therefore,
The output of the multiplier 30 is. The first term in the above equation is a DC component, and the second term is an AC component with an angular frequency of 2ω. Therefore, by cutting the second term component with the low-pass filter 41,
Only the first term component can be output. That is,
The low-pass filter 41 depends only on the input amplitude and angular frequency ω.

従って、低域通過フィルタ41の出力の大きさより、単
一周波数入力の周波数を検出することができる。
Therefore, the frequency of a single frequency input can be detected from the magnitude of the output of the low-pass filter 41.

しかし、第1図のような遅延検波によるものでは、前述
し几ように、低域通過フィルタの出力の大きさは入力の
振幅Aにも依存している為、この検出器の入力の前に精
度のよいAGO回路を必要となるという欠点がある。ま
た、各周波数ごとにフィルタを設けるものでは、入力の
振幅レベルにはそれほど影響でれないが、単一周波数入
力の周波数の種類が多くなると、その種類の数だけフィ
ルタを用意する必要があシ、回路規模が大きくなるとい
う欠点があった。
However, in the case of delay detection as shown in Fig. 1, as mentioned above, the magnitude of the output of the low-pass filter also depends on the input amplitude A, so The disadvantage is that a highly accurate AGO circuit is required. Also, if a filter is provided for each frequency, it will not be affected much by the amplitude level of the input, but as the number of types of frequencies for a single frequency input increases, it becomes necessary to prepare as many filters as there are types. However, the disadvantage is that the circuit size becomes large.

〔発明の構成〕[Structure of the invention]

本発明の正弦波検出回路は、遅延時間の等しい第1及び
第2の遅延回路を縦続に接続し、前記第1の遅延回路の
入力と第2の遅延回路の出力との和を求める加算器と、
前記第1の遅延回路の出力を第1の入力とする乗算器と
、前記加算器の出力よシ該乗算器の出力を減算する減算
器と、該減算器の出力と前記第1の遅延回路の出力とを
入力とし、逐次その出力を更新する信号処理部より構成
てれ、該信号処理部の出力を前記乗算器の第2の入力と
し、該信号処理部の出力値より、入力の正弦波の周波数
を推定することができることを特徴とする。
The sine wave detection circuit of the present invention is an adder that connects first and second delay circuits with equal delay times in cascade and calculates the sum of the input of the first delay circuit and the output of the second delay circuit. and,
a multiplier whose first input is the output of the first delay circuit; a subtracter that subtracts the output of the multiplier from the output of the adder; and the output of the subtracter and the first delay circuit. The output of the signal processing section is input to the multiplier, and the output of the signal processing section is used as the second input of the multiplier, and from the output value of the signal processing section, the sine of the input is It is characterized by being able to estimate the frequency of waves.

〔実施例〕〔Example〕

次に、本発明を図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第2図は本発明の一実施例を示すブロック図であり、一
定時間′rだけ遅延させる遅延回路10および11を縦
続に接続し、遅延回路lOの入力5t(tlと遅延回路
11の出力5s(tlを加算器20により加算し出力8
4(tlを得る。一方、遅延回路10の出力S 2(t
)と信号処理部40の出力5s(tlとを乗算器30で
乗算し、その出力5r(tlを減算器21を使用して加
算器20の出力5dt)から引き算し、出力5s(tl
を得る。信号処理部40では減算器21の出力S 5(
t)と遅延回路10の出力52(t)を信号処理するこ
とにより、信号5S(t)が小さくなるように、その出
力8s(tlを逐次更新していく。この出力信号85(
t)が定常値に達した時の値から、入力の正弦波の周波
数を判定することができる。
FIG. 2 is a block diagram showing an embodiment of the present invention, in which delay circuits 10 and 11 for delaying by a certain time 'r are connected in cascade, and the input 5t (tl) of the delay circuit IO and the output 5s of the delay circuit 11 are connected in series. (Add tl by adder 20 and output 8
4(tl is obtained. On the other hand, the output S2(t
) and the output 5s (tl) of the signal processing unit 40 are multiplied by the multiplier 30, and the output 5r (tl is subtracted from the output 5dt of the adder 20 using the subtracter 21) to obtain the output 5s (tl
get. In the signal processing unit 40, the output S5(
t) and the output 52(t) of the delay circuit 10, the output 8s(tl) is sequentially updated so that the signal 5S(t) becomes smaller.This output signal 85(
The frequency of the input sine wave can be determined from the value when t) reaches a steady value.

すなわち、入力信号5x(tlが単一周波数の正弦波の
場合、入力信号S 1(tlは 81(t)= A −sin (ωt )と表わすこと
ができる。この時、加算器20の出力5s(tlは 8 <(tl = 8 tftl+ 83(t)=Sよ
(t)+5l(t  2T) =A−sin(ωt)+A−sin(ω(t−2T)’
)= 2A −sin (ω(t −’]’ ) ] 
COs (G/r )となる。一方、乗算器30の出力
87(tlは87(t)= S a(tl・8(t−T
)= 5a(tl −A−5in(ω(t −T ))
となる。従りて、信号5s(tlが定常値に達した時に
は、減算器の出力S 5(t)が理想的にゼロすなわち
S 4(t) = 87(t)となるとすると、信号処
理部40の出力8 a(tlは 8g(t)=2・cos (ωT) となシ、入力51(tlの振幅人には移存せず、角周波
数ωのみに依存する信号となる。従って、信号処理部4
0の出力信号5s(tlの大きさよシ入力ax(tlの
周波数を、その振幅とは無関係に判定することができる
That is, when the input signal 5x (tl is a sinusoidal wave with a single frequency), the input signal S1 (tl can be expressed as 81(t) = A - sin (ωt). At this time, the output 5s of the adder 20 (tl is 8 <(tl = 8 tftl+ 83(t)=Syo(t)+5l(t2T) =A-sin(ωt)+A-sin(ω(t-2T)'
)=2A −sin (ω(t −′]′ ) ]
COs (G/r). On the other hand, the output 87(tl) of the multiplier 30 is 87(t)=S a(tl・8(t−T
)=5a(tl-A-5in(ω(t-T))
becomes. Therefore, when the signal 5s(tl reaches a steady value, the output S5(t) of the subtracter ideally becomes zero, that is, S4(t) = 87(t), the signal processing section 40 Output 8 a (tl is 8g(t) = 2・cos (ωT)), input 51 (the amplitude of tl is not transferred to the human body, and becomes a signal that depends only on the angular frequency ω. Therefore, the signal processing Part 4
The frequency of the input ax(tl) can be determined independently of its amplitude by the magnitude of the output signal 5s(tl) of zero.

信号処理部40の動作の一実施例として、最急傾斜アル
ゴリズムを採用する。すなわち、信号処理部40の0回
更新後の出力を特徴とする特許S 5(tl / n+
、=85(tl八へα・5s(tl・82ft+(αは
定数) に従って86(jl/nを更新することにより、減算器
21の出力5s(tlを小さくすることができる。
As an example of the operation of the signal processing unit 40, a steepest slope algorithm is adopted. That is, Patent S5(tl/n+
,=85(tl8 to α·5s(tl·82ft+(α is a constant)) By updating 86(jl/n, the output 5s(tl) of the subtractor 21 can be made smaller.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、受信入力の正弦
波の振幅とは無関係に、その入力の周波数を判定するこ
とができ、ま几、入力正弦波の周波数の種類が多い時に
でも、従来のようにフィルタの数を増やす必要はなく、
簡単な構成で提供することができる。
As explained above, according to the present invention, the frequency of the input sine wave can be determined regardless of the amplitude of the received input sine wave, and even when there are many types of input sine waves, There is no need to increase the number of filters as in the past,
It can be provided with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例を示すブロック図、第2図は本発明の実
施例を示すブロック図である。 10.11・・・・・・遅延回路、20・・川・加算器
、 21・・・・・・減算器、3o・・・・・・乗算器
、40・・・・・・信号処理部、41・・・・・・低域
通過フィルタ。 O 猶・1頂 争2剖
FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 10.11...delay circuit, 20...adder, 21...subtractor, 3o...multiplier, 40...signal processing section , 41...Low pass filter. O Yu・1 top conflict 2 autopsy

Claims (1)

【特許請求の範囲】[Claims] 遅延時間の等しい第1、第2の遅延回路の直列回路と、
前記第1の遅延回路の正弦波入力と第2の遅延回路の出
力との和を求める加算器と、前記第1の遅延回路の出力
を第1入力とする乗算器と、前記加算器の出力から該乗
算器の出力を減算する減算器と、該減算器の出力と前記
第1の遅延回路の出力とを入力とし、逐次その出力を更
新して前記乗算器の第2入力とし前記減算器の2つの入
力がほぼ等しくなるようにする信号処理部とを有し、前
記信号処理部の出力値から前記正弦波の周波数を検出す
るようにしたことを特徴とする正弦波周波数検出回路。
a series circuit of first and second delay circuits having equal delay times;
an adder that calculates the sum of the sine wave input of the first delay circuit and the output of the second delay circuit; a multiplier whose first input is the output of the first delay circuit; and an output of the adder. a subtracter that subtracts the output of the multiplier from the subtracter; the output of the subtracter and the output of the first delay circuit are input, and the output is sequentially updated to be used as a second input of the multiplier; A sine wave frequency detection circuit comprising: a signal processing section that makes two inputs substantially equal, and detecting the frequency of the sine wave from an output value of the signal processing section.
JP27738384A 1984-12-27 1984-12-27 Sine wave frequency detecting circuit Pending JPS61156957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27738384A JPS61156957A (en) 1984-12-27 1984-12-27 Sine wave frequency detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27738384A JPS61156957A (en) 1984-12-27 1984-12-27 Sine wave frequency detecting circuit

Publications (1)

Publication Number Publication Date
JPS61156957A true JPS61156957A (en) 1986-07-16

Family

ID=17582759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27738384A Pending JPS61156957A (en) 1984-12-27 1984-12-27 Sine wave frequency detecting circuit

Country Status (1)

Country Link
JP (1) JPS61156957A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06553U (en) * 1992-06-18 1994-01-11 品川白煉瓦株式会社 Refractory block for continuous casting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06553U (en) * 1992-06-18 1994-01-11 品川白煉瓦株式会社 Refractory block for continuous casting

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