JPS61156786A - Manufacture of semiconductor luminescent device - Google Patents

Manufacture of semiconductor luminescent device

Info

Publication number
JPS61156786A
JPS61156786A JP59280728A JP28072884A JPS61156786A JP S61156786 A JPS61156786 A JP S61156786A JP 59280728 A JP59280728 A JP 59280728A JP 28072884 A JP28072884 A JP 28072884A JP S61156786 A JPS61156786 A JP S61156786A
Authority
JP
Japan
Prior art keywords
film
semiconductor
layer
semiconductor substrate
amorphous state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59280728A
Other languages
Japanese (ja)
Inventor
Tomoji Nakamura
友二 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59280728A priority Critical patent/JPS61156786A/en
Publication of JPS61156786A publication Critical patent/JPS61156786A/en
Pending legal-status Critical Current

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  • Led Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To prevent the Au film from penetrating the semiconductor layer and to prevent the bad effect of the Au film by a method wherein a Ti film and a Pt film are adhered on the upper surface of the semiconductor substrate in such a way that at least one side of the Ti film and the Pt film is brought into an amorphous state. CONSTITUTION:The semiconductor substrate formed with a P-type InGaAsP contact layer 5 on its uppermost surface is placed in the chamber of the electron beam evaporating device and the substrate is cooled by liquid nitrogen and is made to drop to an absolute temperature of 77 deg.K. The interior of the evaporating chamber is made vacuous, and a Ti film 11 and a Pt film 12 are continuously evaporated on the upper surface of the semiconductor substrate by an electron beam evaporation method. So that the films 11 and 12 in an amorphous state are formed. Then, an Au film 13 is evaporated thereon. According to such a forming method, the film 11 and the film 12, which are adhered in an amorphous state, are hard to crystallize, and even though the films 11 and 12 are crystallized, pinholes are hard to generate. Accordingly, the Au film is prevented from penetrating the semiconductor layer and is prevented from being diffused in the semiconductor layer. As a result, the characteristics of the semiconductor laser can be made to improve.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体発光装置の製造方法に係り、特に半導体
レーザや発光ダイオードの電極形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor light emitting device, and particularly to a method of forming electrodes of a semiconductor laser or a light emitting diode.

最近、光伝送が脚光を浴びており、その光源として発光
ダイオードや半導体レーザが利用されているが、これら
の光源はm−v属化合物半導体のへテロ接合構造からな
り、特に、コヒーレントな光をだす半導体レーザは光伝
送用光源の本命とみ  −なされている。例えば、波長
0.7〜0.9μm帯の^lGaAs / GaAs 
(活性M/基板)や波長1〜1.5μm帯のInGaA
s P / In Pは良く知られている発光光源であ
る。
Recently, optical transmission has been in the spotlight, and light-emitting diodes and semiconductor lasers are used as light sources.These light sources are made of a heterojunction structure of m-v compound semiconductors, and are particularly difficult to transmit coherent light. Semiconductor lasers that emit light are considered to be the most promising light sources for optical transmission. For example, ^lGaAs/GaAs in the wavelength band of 0.7 to 0.9 μm
(active M/substrate) and InGaA in the wavelength band of 1 to 1.5 μm
sP/InP is a well-known luminescent light source.

このような半導体レーザ、あるいは発光ダイオードにお
いて、発光効率を高めて、出来るだけ長寿命化すること
、換言すれば、高性能化して信頼性を高めることが要望
されている。
In such semiconductor lasers or light emitting diodes, it is desired to increase the luminous efficiency and extend the life span as much as possible, in other words, to improve the performance and reliability.

[従来の技術] 図はこのような発光装置の一例として、埋め込み型In
GaAs P / In P半導体レーザの一形式の概
要断面図を示しており、本例は1,3μmの発光波長を
もったVSB形(V −5haped 5ubstra
te Buri −ed tleterostruct
ure形)埋め込み型レーザである。
[Prior Art] The figure shows an example of such a light-emitting device.
This figure shows a schematic cross-sectional view of one type of GaAs P/In P semiconductor laser.
te Buri-ed tleterostruct
(ure type) embedded type laser.

図中、1はn−InP基板、2はn−InPnツバ1フ
フ ッド層.5はp − 111GaAs Pコンタクト層
,6はp−InP層(電流阻止層)で、そのコンタクト
層5の上面にn電極(+電極)10が設けられ、それは
チタン(Ti)膜(膜厚1000人程度定押1,白金(
Ptン膜(膜厚1000人程度定押2,金(Au)膜1
3(膜厚3μm)の三層を積層した構造となっている。
In the figure, 1 is an n-InP substrate, 2 is an n-InPn flange 1 hood layer. 5 is a p-111GaAs P contact layer, 6 is a p-InP layer (current blocking layer), and an n electrode (+ electrode) 10 is provided on the upper surface of the contact layer 5, which is a titanium (Ti) film (film thickness 1000 mm). Fixed number of people 1, platinum (
Pt film (film thickness: approximately 1000) 2, gold (Au) film 1
It has a structure in which three layers (thickness: 3 μm) are laminated.

又、n電極(−電極)20はInP基板1の裏面に形成
され、それは金−ゲルマニウムーニソケルからなる電極
である。
Further, an n-electrode (-electrode) 20 is formed on the back surface of the InP substrate 1, and is an electrode made of gold-germanium nitride.

このような埋め込み型レーザは、レーザ発光が両側の電
流阻止層で閉じ込められて、中央部のn− 1nGaA
s P活性層3で行なわれ、特に低しきい値電流が得ら
れる特徴がある。
In such a buried laser, the laser emission is confined by the current blocking layers on both sides, and the n-1nGaA
This is carried out in the sP active layer 3, and has the characteristic that a particularly low threshold current can be obtained.

[発明が解決しようとする問題点] ところで、上記に例示した半導体レーザ、あるいはその
他の発光装置において、n電極20は膜厚の厚い基板裏
面に形成されるから問題はないが、p電極lOの方は薄
くエビタキンヤル成長した屓(活性層に近い層)の上に
形成されるから、それは信頼性上に大きな影響を与える
[Problems to be Solved by the Invention] Incidentally, in the semiconductor laser or other light emitting device exemplified above, there is no problem since the n-electrode 20 is formed on the back surface of the thick substrate, but the p-electrode lO Since the layer is formed on a thin layer (layer close to the active layer) of the epidermis, it has a big impact on reliability.

即ち、Ti篩膜1とPt膜12とは電子ビーム蒸着法で
連続形成され、次いで、電解鍍金法でAu膜が形成され
るが、そのオーミックコンタクトを良くするための熱処
理を行なうと、鍍金したAu膜がこれらの膜を透過拡散
して、半導体層と反応し、素子特性を悪くすることが判
ってきた。更に、動作中にもAuが浸透して発光特性を
悪化させることがある。
That is, the Ti sieve film 1 and the Pt film 12 are successively formed by electron beam evaporation, and then the Au film is formed by electroplating. It has been found that the Au film diffuses through these films, reacts with the semiconductor layer, and deteriorates device characteristics. Furthermore, Au may penetrate during operation and deteriorate the light emitting characteristics.

これらの問題はオージェ電子分光法の分析で検出され、
明らかとなってきた。
These problems were detected by Auger electron spectroscopy analysis and
It has become clear.

その原因は、Ti膜とPt膜とが非常に薄く、且つ、蒸
着したTi膜やPt膜はアモルファスと多結晶との混合
状態にあり、その結晶構造特有の間隙から^Uが突き抜
けていると思われる。
The reason for this is that the Ti film and Pt film are very thin, and the deposited Ti film and Pt film are in a mixed state of amorphous and polycrystalline, and the ^U penetrates through the gaps unique to the crystal structure. Seem.

更に、これらのTi膜,Pt膜を被着した後のピンホー
ルを観察すると、ピンホール密度は10′F/cni以
上であり、これもAuが透過する原因と考えられる。
Furthermore, when observing the pinholes after these Ti films and Pt films were deposited, the pinhole density was 10'F/cni or more, which is also considered to be the cause of Au permeation.

一方、このように、p電極lOをTi −Pt−Au三
層構造にしている理由は、Ptと篩とが半導体層と反応
し易いために、半導体層との間にTiを介在させており
、且つ、TiとAuとも反応し易いために、その間にP
tを介在させているものである。
On the other hand, the reason why the p-electrode IO has a Ti-Pt-Au three-layer structure is because Pt and the sieve easily react with the semiconductor layer, so Ti is interposed between the semiconductor layer and the sieve. , and because it easily reacts with Ti and Au, P
t is interposed therebetween.

また、Ti膜とPt膜とを膜厚1000人程度定押く形
成しているのは、これらを余り厚く被着すると、熱膨張
が半導体層と大きく相異するため、応力が生じて半導体
層に歪を与え、発光特性に影響する問題があるからであ
る。
Furthermore, the reason why the Ti film and Pt film are formed at a constant thickness of about 1000 is that if they are deposited too thickly, their thermal expansion will be significantly different from that of the semiconductor layer, which will cause stress to occur in the semiconductor layer. This is because there is a problem in that it causes distortion and affects the light emission characteristics.

本発明は、このような問題点を取り除いて、高性能化・
高信頼化される電極の形成方法を提案するものである。
The present invention eliminates these problems and improves performance.
This paper proposes a method for forming highly reliable electrodes.

[問題点を解決するための手段] その問題は、半導体基板の上面に、少なくとも一方がア
モルファス状態になるように、Ti膜とPt膜とを連続
形成し、次いで、該Pt膜上にAu膜を形成する三層積
層構造の電極形成工程が含まれる半導体発光装置の製造
方法によって解決される。
[Means for solving the problem] The problem is to form a Ti film and a Pt film in succession on the upper surface of a semiconductor substrate so that at least one of them is in an amorphous state, and then to form an Au film on the Pt film. The problem is solved by a method of manufacturing a semiconductor light emitting device, which includes a step of forming an electrode with a three-layer stacked structure.

例えば、この半導体基板を100°K以下の温度で冷却
して、該半導体基板の上面にTi膜とPt膜とを連続形
成する。また、このような三層電極をp− InGaA
s Pからなるコンタクト層に接続する。
For example, this semiconductor substrate is cooled to a temperature of 100°K or less, and a Ti film and a Pt film are successively formed on the upper surface of the semiconductor substrate. Moreover, such a three-layer electrode is made of p-InGaA
Connect to the contact layer made of sP.

[作用]    ・ 即ち、本発明は、半導体基板を100″に以下の温度、
即ち、液体窒素温度(77°K)程度に冷却して、Ti
膜とPt膜の少なくとも一方をアモルファス状態で被着
するようにする。勿論、両膜ともアモルファス状態で被
着する方が望ましい。
[Function] - That is, in the present invention, the semiconductor substrate is heated to a temperature of 100" or less,
That is, the Ti is cooled to about liquid nitrogen temperature (77°K).
At least one of the film and the Pt film is deposited in an amorphous state. Of course, it is preferable that both films be deposited in an amorphous state.

そうすると、緻密な膜質となって、また、熱処理しても
結晶化しに<<、従フて、6膜の突き抜けが阻止され、
その悪影響が防止される。
As a result, the film becomes dense and does not crystallize even after heat treatment, thus preventing the film from penetrating.
Its negative effects are prevented.

[実施例] 以下,実施例によって形成工程を詳細に説明する。[Example] Hereinafter, the formation process will be explained in detail using examples.

p −In Ga AsP (0<x<1.0<y<1
)からなるコンタクト層5を最上面に形成した半導体基
板を、電子ビーム蒸着装置のチャンバ内に載置し、それ
を液体窒素で冷却して77°Kにする。そして、蒸着チ
ャンバ内の真空度を1O−6Torr以下にして、その
上面に電子ビーム蒸着法で膜厚1000人のTi膜11
.膜厚1000人のPt1l臭12を連続して茎着する
。そうすると、アモルファス状態(非晶質状態)の膜が
形成される。
p-In Ga AsP (0<x<1.0<y<1
) is placed in a chamber of an electron beam evaporator and cooled to 77°K with liquid nitrogen. Then, the degree of vacuum in the evaporation chamber was set to 1O-6 Torr or less, and a Ti film 11 with a thickness of 1000 nm was deposited on the top surface using the electron beam evaporation method.
.. Pt1l odor 12 with a film thickness of 1000 was applied continuously. In this way, a film in an amorphous state (non-crystalline state) is formed.

次いで、これを水素雰囲気中で、430℃、30分間の
熱処理を行なう。これはコンタクト層とのオーミックコ
ンタクトを十分にするための処理である。次いで、その
上に、通常の電解鍍金法で膜厚3μmのへU膜を被着す
る。
Next, this is heat-treated at 430° C. for 30 minutes in a hydrogen atmosphere. This is a process to ensure sufficient ohmic contact with the contact layer. Next, a U film having a thickness of 3 μm is deposited thereon by a normal electrolytic plating method.

次いで、膜厚2000人のn電極20を蒸着し、更に、
380℃、1分間の熱処理を行ない、最後に、襞間して
半導体レーザに仕上げる。
Next, an n-electrode 20 with a thickness of 2000 was deposited, and further,
Heat treatment is performed at 380° C. for 1 minute, and finally, the semiconductor laser is finished by folding.

このような形成方法によれば、アモルファス状態で被着
したTi膜、 Pt膜が結晶化し難<、又、結晶化して
もピンホールができに(い。そのピンホールの密度は1
03 /clIl以下であることが確認されている。且
つ、本形成方法によれば、コンタクト層のAu濃度はオ
ージェ電子分光法の検出限界以下になった。ラザフォー
ト後方lt&乱法による分析でも、同様に検出限界外と
なった。
According to such a formation method, the Ti film and Pt film deposited in an amorphous state are difficult to crystallize, and even if crystallized, pinholes are not formed (the density of the pinholes is 1).
It has been confirmed that it is less than 0.03 /clIl. Moreover, according to this formation method, the Au concentration of the contact layer was below the detection limit of Auger electron spectroscopy. Analysis using the Rutherfort backward lt&random method was also outside the detection limit.

上記の実施例は、VSB形埋め込み型半導体レーザであ
るが、その他のBH形やPBH形の半導体レーザ、ある
いは発光ダイオードにも適用できることは云うまでもな
い。
Although the above embodiment is a VSB type buried semiconductor laser, it goes without saying that it can also be applied to other BH type or PBH type semiconductor lasers or light emitting diodes.

[発明の効果] 以上の説明から明らかなように、本発明によれば、半導
体層へのAuの透過拡散がなくなって、半導体レーザの
特性・信頼性の向上に大きな効果が得られる。
[Effects of the Invention] As is clear from the above description, according to the present invention, transmission and diffusion of Au into the semiconductor layer is eliminated, and a great effect is obtained in improving the characteristics and reliability of the semiconductor laser.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明を適用する一実施例の半導体レーザの概要断
面図である。 図において、 1はn −1nP基板、 2はn−1nPバッファ層、 3はn −1nGaAs P活性層、 4はp−1nPクラッド層、 5はp −1nGaAs Pコンタクト層、6はp −
1nP電流阻止層、 20は一電極、 10は十電極、      11はTi膜、12はPt
膜、       13は^U膜を示している。
The figure is a schematic cross-sectional view of a semiconductor laser according to an embodiment of the present invention. In the figure, 1 is an n-1nP substrate, 2 is an n-1nP buffer layer, 3 is an n-1nGaAs P active layer, 4 is a p-1nP cladding layer, 5 is a p-1nGaAs P contact layer, and 6 is a p-1nP layer.
1nP current blocking layer, 20 is one electrode, 10 is ten electrodes, 11 is Ti film, 12 is Pt
Membrane 13 indicates the ^U membrane.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の上面に、少なくとも一方がアモルフ
ァス状態になるように、Ti膜とPt膜とを連続形成し
、次いで、該Pt膜上にAu膜を形成する三層積層構造
の電極形成工程が含まれてなることを特徴とする半導体
発光装置の製造方法。
(1) Step of forming an electrode with a three-layer stacked structure in which a Ti film and a Pt film are successively formed on the upper surface of a semiconductor substrate so that at least one of them is in an amorphous state, and then an Au film is formed on the Pt film. 1. A method of manufacturing a semiconductor light emitting device, comprising:
(2)半導体基板を100°K以下の温度で冷却して、
該半導体基板の上面にTi膜とPt膜とを連続形成し、
次いで、該Pt膜上にAu膜を形成する三層積層構造の
電極形成工程が含まれてなることを特徴とする特許請求
の範囲第1項記載の半導体発光装置の製造方法。
(2) Cooling the semiconductor substrate at a temperature of 100°K or less,
Continuously forming a Ti film and a Pt film on the upper surface of the semiconductor substrate,
2. The method of manufacturing a semiconductor light emitting device according to claim 1, further comprising the step of forming an electrode having a three-layer laminated structure of forming an Au film on the Pt film.
(3)上記電極が接続される半導体基板の上面が、p−
InGaAsP(0<x<1、0<y<1)層からなる
ことを特徴とする特許請求の範囲第1項記載の半導体発
光装置の製造方法。
(3) The upper surface of the semiconductor substrate to which the above electrode is connected is p-
2. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is made of an InGaAsP (0<x<1, 0<y<1) layer.
JP59280728A 1984-12-27 1984-12-27 Manufacture of semiconductor luminescent device Pending JPS61156786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59280728A JPS61156786A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor luminescent device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59280728A JPS61156786A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor luminescent device

Publications (1)

Publication Number Publication Date
JPS61156786A true JPS61156786A (en) 1986-07-16

Family

ID=17629112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59280728A Pending JPS61156786A (en) 1984-12-27 1984-12-27 Manufacture of semiconductor luminescent device

Country Status (1)

Country Link
JP (1) JPS61156786A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396229A (en) * 1989-08-16 1991-04-22 American Teleph & Telegr Co <Att> Semiconductor device and method of manufacturing the same
US5266526A (en) * 1991-03-19 1993-11-30 Kabushiki Kaisha Toshiba Method of forming trench buried wiring for semiconductor device
JP2008244344A (en) * 2007-03-28 2008-10-09 Mitsubishi Materials Corp Thin film thermistor element and manufacturing method of thin film thermistor element
US9018736B2 (en) 2013-04-24 2015-04-28 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396229A (en) * 1989-08-16 1991-04-22 American Teleph & Telegr Co <Att> Semiconductor device and method of manufacturing the same
US5266526A (en) * 1991-03-19 1993-11-30 Kabushiki Kaisha Toshiba Method of forming trench buried wiring for semiconductor device
JP2008244344A (en) * 2007-03-28 2008-10-09 Mitsubishi Materials Corp Thin film thermistor element and manufacturing method of thin film thermistor element
US9018736B2 (en) 2013-04-24 2015-04-28 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing semiconductor device

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