JPS61156328A - Tablet input device - Google Patents

Tablet input device

Info

Publication number
JPS61156328A
JPS61156328A JP59281213A JP28121384A JPS61156328A JP S61156328 A JPS61156328 A JP S61156328A JP 59281213 A JP59281213 A JP 59281213A JP 28121384 A JP28121384 A JP 28121384A JP S61156328 A JPS61156328 A JP S61156328A
Authority
JP
Japan
Prior art keywords
bit
tablet
wires
wire
error detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59281213A
Other languages
Japanese (ja)
Inventor
Minoru Saito
実 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pentel Co Ltd
Original Assignee
Pentel Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pentel Co Ltd filed Critical Pentel Co Ltd
Priority to JP59281213A priority Critical patent/JPS61156328A/en
Publication of JPS61156328A publication Critical patent/JPS61156328A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid the wrong inputs by distributing an error detecting lead wire as if it enclosed a signal transmission lead wire and also scanning this lead wire in the same way as the electrode wires in the (x) and (y) directions. CONSTITUTION:The x-direction bit electrode wires 21 and digit electrode wires 22 are provided alternately with the prescribed spaces on the surface side of an insulated substrate 11. While the y-direction bit electrode wires 31 and digit electrode wires 32 are provided alternately with prescribed spaces on the rear surface side of the substrate 11. Thus an electrostatic coupled tablet 1 is obtained. Furthermore an error detection wire 71 for y-bit lead wire surrounds the part where y-bit lead wires 61-1-61-8 pass through and is connected to a terminal 81-39 via through holes 41i and 41j. While an error detection wire 72 for x-bit lead wire surrounds the part where x-bit lead wires 51-1-51-8 pass through. An end of the wire 72 is connected to a terminal 81-13 with the other end 72a connected to a terminal 72b respectively in the form of a loop.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はタブレット入力装置に関し、特にそのタブレッ
トの信号伝送用導線に係る誤入力の防止に関する。  
  ゛ (従来の技術) タブレット入力装置では、タブレットに形成されている
X方向及びy方向の各電極線とこのタブレットに当接さ
れる入力ペン等の座標指示手段との電気的結合(静電結
合や電磁結合)を利用して、そのとき指示されている座
標の特定を行なう。ところでとのタブレットには前記各
方向の電極線に加え、これと駆動回路等を接続するため
の信号伝送用導線を設けなければならないが、従来この
導線の配置には細心の注意を要求されている。これは、
この信号伝送用導線にも当然のことながら各電極線と同
じよ5)Cパルス信号が流れており、この信号伝送用導
線の配置によっては、入力領域外であう【もそこに不用
意に当接された座標指示手段とこれら電極線、信号伝送
用導線とが結合し、恰かも入力領域内に正しく座標指示
手段が当接されたかのような座標データ出力が為されて
しまうことがあるからである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a tablet input device, and more particularly to prevention of erroneous inputs related to signal transmission conductors of the tablet.
(Prior Art) In a tablet input device, electrical coupling (electrostatic coupling) is required between each electrode wire in the X direction and the y direction formed on the tablet and a coordinate indicating means such as an input pen that is in contact with the tablet. (or electromagnetic coupling) to identify the coordinates specified at that time. By the way, in addition to the electrode wires in each direction mentioned above, the tablet must be provided with signal transmission wires to connect these to the drive circuit, etc., but conventionally, careful attention has been required to the placement of these wires. There is. this is,
Naturally, the same 5) C pulse signal is flowing through this signal transmission conductor as in each electrode wire, and depending on the arrangement of this signal transmission conductor, it may be outside the input area and may be accidentally touched. This is because there is a possibility that the coordinate indicating means which has been inputted is coupled with these electrode wires and the signal transmission conductive wire, and the coordinate data may be output as if the coordinate indicating means was correctly brought into contact within the input area. .

このため従来は1例えば金属材料からなる額縁状の筐体
によってタブレットの周辺部等の信号伝送用導線配置部
を覆ったり、タブレットの周辺部等を十分広くして各電
極線と信号伝送用導線を隔離し、これらが同時に座標指
示手段と結合することがないよ5Kしていた。
For this reason, conventional methods have been to cover the area where signal transmission conductors such as the periphery of the tablet are arranged with a frame-shaped casing made of a metal material, or to make the periphery of the tablet sufficiently wide so that each electrode wire and signal transmission conductor can be arranged. 5K to prevent them from being combined with the coordinate indicating means at the same time.

(発明が解決しよ5としている問題点)このため従来の
タブレット入力装置では、jA観上あるいはコスト上樹
脂製筐体を用いようとしても2代りのシールド手段を設
けなければならないとか、入力領域の周辺を広くして信
号伝送用導線と電極線とを遠ざけなければならないとか
の制約があった。
(Problem that the invention aims to solve) For this reason, in conventional tablet input devices, even if a resin casing is used due to aesthetic or cost reasons, it is necessary to provide two alternative shielding means, and the input area There were restrictions such as the need to widen the area around the signal transmission conductor and the electrode wire to distance them.

(問題点を解決するための手段) そこで本発明では、信号伝送用導線をとり囲むように誤
り検出用導線を配置し、この導線もx、y各方向電極線
と同様に走査することとする。
(Means for solving the problem) Therefore, in the present invention, error detection conductors are arranged so as to surround the signal transmission conductors, and these conductors are also scanned in the same manner as the electrode lines in each of the x and y directions. .

(作用) 即ちこのようにすると、信号伝送用導線と座標指示手段
が結さした状態にあるときは誤り検出用導線もこの座標
指示手段と結合し、この誤り検出用4!IK係る信号が
検出されるので、これによりそのときの座標指示が誤り
であると判別できる。
(Function) That is, by doing this, when the signal transmission conductor and the coordinate indicating means are connected, the error detection conductor is also connected to the coordinate indicating means, and the error detection 4! Since a signal related to IK is detected, it can be determined from this that the coordinate instruction at that time is incorrect.

!(実施例) 以下本発明の詳細ItgJ示実施例に基いて説明する。! (Example) The details of the present invention will be explained below based on illustrative examples.

なおこの実施例は静電結合型タブレット入力装置に本発
明を適用したものである。第1WICおいて1はタブレ
ットで、ガラスエポキシ樹脂等の絶縁基板110表側(
同図(A) )にはX方向のビット電極線21及び桁電
極線22がヌ互に所定の間隔で、また裏a(同図(B)
)にはy方向のビット電極線51及び桁電極線32が交
互に所定の間隔で、夫々形成されている。X方向ビット
電極線21はX方向に46本(21−1〜2l−46)
形成されており、夫々7本おきにスルーホール41を介
して裏面のX方向ビット電極線信号伝送用導線51−1
〜5l−13(以下「Xビット導線」と称す。)K接続
されている。また、X方向桁電極線も46本(22−1
〜22−46)形成されており、こちらは7本づつ並列
接続されX方向桁電極線信号伝送用導線52−1〜52
−7に接続されている。
In this embodiment, the present invention is applied to a capacitively coupled tablet input device. In the first WIC, 1 is a tablet, and the front side of an insulating substrate 110 made of glass epoxy resin, etc.
The bit electrode lines 21 and the digit electrode lines 22 in the
), bit electrode lines 51 and digit electrode lines 32 in the y direction are alternately formed at predetermined intervals. There are 46 X-direction bit electrode lines 21 (21-1 to 2l-46) in the X direction.
X-direction bit electrode line signal transmission conducting wires 51-1 on the back surface are formed through through holes 41 every seven wires.
~5l-13 (hereinafter referred to as "X bit conductor") K connection. In addition, there are 46 X-direction digit electrode wires (22-1
~22-46) are formed, and here seven wires are connected in parallel and X direction digit electrode wire signal transmission conductors 52-1 to 52 are formed.
-7 is connected.

これら電極線の接続はy方向に関しても同様で、y方向
ビット電極線51−1〜451−58は7本おきにスル
ーホール41を介してy方向ビット電極線信号伝送用導
線61−1〜6l−8(以下「yビット導線」と称す)
に、またy方向桁電極線32−1〜52−38は7本づ
つ並列接続されy方向桁電極線信号伝送用導線62−1
〜62−6)Cll続されている。
The connection of these electrode wires is the same in the y direction, and the y direction bit electrode lines 51-1 to 451-58 are connected every seven through holes 41 to the y direction bit electrode line signal transmission conducting wires 61-1 to 6l. -8 (hereinafter referred to as "y bit conductor")
In addition, seven y-direction digit electrode wires 32-1 to 52-38 are connected in parallel to form a y-direction digit electrode wire signal transmission conductor 62-1.
~62-6) Cll is connected.

また71はyビット導線用談り検出導線で。Also, 71 is the tamper detection lead for the y bit lead.

yピッ)導線61−1〜61−8が通っている部分(第
1図囚図面左側)を周回する形で形成されており、スル
ーホール41i、41jを介して端子8l−5917C
接続されている。更に72はXビ。
It is formed to go around the part where the conductors 61-1 to 61-8 pass (left side in Figure 1), and connects to the terminal 8l-5917C through the through holes 41i and 41j.
It is connected. Furthermore, 72 is X-Bi.

ト導線用誤り検出導線で#Xビット導線51−1〜51
−8が通っている部分(第1図(Bl v!J面下側)
を周回する形で形成されており、一端は端子81−13
に、また他端72mは不図示接続線によりて端子72b
k接続され、ループにされているO なお前述の各信号伝送用導線51.52.61゜62も
端子81−1〜81−40のいずれかに接続されている
が、詳細説明は略す。
#X bit conductors 51-1 to 51 with error detection conductors for bit conductors
- The part where 8 passes (Figure 1 (Bl v! J side bottom side)
The terminal 81-13 is formed around the terminal 81-13 at one end.
, and the other end 72m is connected to a terminal 72b by a connection wire (not shown).
The signal transmission conductive wires 51, 52, 61 and 62 described above are also connected to any of the terminals 81-1 to 81-40, but detailed explanation will be omitted.

第2図にブロック構成例を示す。図において1は第1t
ZI忙示したタブレ、)、81−1〜81−40はその
端子群である。101はデコーダで。
FIG. 2 shows an example of the block configuration. In the figure, 1 is the first t
81-1 to 81-40 are the terminal groups. 101 is a decoder.

供給されるアドレス信号ADをデコードし、各端子81
−1〜81−40に走査パルスSPを印加する。102
は入力ペンであり、その検出先端102Aがタブレット
1に当接されると動作するペンスイッチ102Bを内蔵
している。105は増幅器で検出光fa102Ai’c
生ずる誘起パルスPPを増幅する。104はアナログデ
ジタル変換器で誘起パルスPPのパルス高をデジタル値
DDに変換する。105は入出力ポート(以下「IO」
と称す)であり、処理装置106(以下rCPUJと称
す)と各プロ、りとの間のデータの授受に供される。C
PU106は所謂マイクロコンビ、−タで構成され、リ
ードオンリーメそす107(以下「ROMJと称す)K
格納されているプログラムに従い、ランダムアクセスメ
モリ108(以下「RAMJと称す)を使用しながら、
指示座標の特定等、所定の6埋を実行する。
The supplied address signal AD is decoded and each terminal 81 is
A scanning pulse SP is applied to -1 to 81-40. 102
is an input pen, and has a built-in pen switch 102B that operates when its detection tip 102A comes into contact with the tablet 1. 105 is an amplifier for detecting light fa102Ai'c
The resulting induced pulse PP is amplified. 104 is an analog-to-digital converter that converts the pulse height of the induced pulse PP into a digital value DD. 105 is an input/output port (hereinafter referred to as “IO”)
It is used for exchanging data between the processing device 106 (hereinafter referred to as rCPUJ) and each processor. C
The PU 106 is composed of a so-called micro combination, and is a read-only system 107 (hereinafter referred to as "ROMJ").
While using the random access memory 108 (hereinafter referred to as "RAMJ") according to the stored program,
Executes predetermined 6-filling, such as specifying designated coordinates.

次に本実施例の動作を説明する。まずオペレータが入力
ペン102の先端102Aをタブレット1上の所望の座
標に当接すると、ペンスイッチ102Bが閉じペンスイ
ッチ信号psがl0105を介してCPU106i(供
給される。CPo 106はこの信号PSK応動してま
ずX方向招電極線22−1〜22−46に走査パルスS
Pを印加すぺ(所定のアドレス信号ADを順次供給する
。本実施例ではこの桁電極線22−1〜22−46が7
本づつ並列に接続され7つのグループとされており。
Next, the operation of this embodiment will be explained. First, when the operator touches the tip 102A of the input pen 102 to desired coordinates on the tablet 1, the pen switch 102B closes and the pen switch signal ps is supplied to the CPU 106i (via l0105. The CPo 106 responds to this signal PSK. First, a scanning pulse S is applied to the X-direction invitation wires 22-1 to 22-46.
P is applied (predetermined address signals AD are sequentially supplied. In this embodiment, these digit electrode lines 22-1 to 22-46 are
Each book is connected in parallel to form seven groups.

ここでは各グループに順にヘキサ表示「01」°〜「0
7」のアドレスが割当てられているとしたら、CPU1
06は「01」から「07Jまでのアドレス信号ADを
順にデーーダ101に供給する。そしてCPU106は
このときの各アドレス値「01」〜「07」の印加時化
生ずる誘起パルスppのデジタル値DDt’RAM10
8の所定エリアに格納する。以下同様にしてCPU10
6はX方向のピット電極線21−1〜21−46.7方
向の桁電極線31−1〜31−38.7方向のビット電
極線52−1〜52−38の各グループに対して順次走
査パルスSPを印加すべく、所定のアドレス信号ADを
順次供給し、そのとき誘起するパ[ ルスSPのデジタル値DDをRAM108の所定番地に
格納する。
Here, each group is displayed in hex in order from "01" to "0".
7" is assigned, CPU1
06 sequentially supplies the address signals AD from "01" to "07J" to the datar 101.The CPU 106 then calculates the digital value DDt' of the induced pulse pp generated when each of the address values "01" to "07" is applied. RAM10
8 in a predetermined area. Similarly, CPU10
6 sequentially for each group of pit electrode lines 21-1 in the X direction to digit electrode lines 31-1 in the 21-46.7 direction to bit electrode lines 52-1 to 52-38 in the 31-38.7 direction. In order to apply the scanning pulse SP, a predetermined address signal AD is sequentially supplied, and the digital value DD of the pulse SP induced at that time is stored in a predetermined location in the RAM 108.

そして更1ccPυ106は所定のアドレス信号ADを
デコーダ101に供給し、yビット導線用具り検出導線
71及びXビット導線用誤り検出導線72に順次走査パ
ルスSPを印加し、そのとき入力ペン先端102Aに発
生する誘起パルスppのデジタル値DD′4tRAM1
08の所定番地に格納する。
Further, the 1ccPυ 106 supplies a predetermined address signal AD to the decoder 101, and sequentially applies scanning pulses SP to the Y bit conductor error detection conductor 71 and the The digital value DD'4tRAM1 of the induced pulse pp
08 at the specified location.

次いで(pUto6はこのRAM 108に格納されて
いる各デジタル値DDの中からyビット導線用具り検出
導線72及びXビット導線用誤り検出導971に係る各
誘起パルスPPのデクタル値DDを読入出し、その値が
所定値より大きくないか否かを判断する。
Next, (pUto6 reads out the digital value DD of each induced pulse PP related to the Y-bit conductor error detection conductor 72 and the X-bit conductor error detection conductor 971 from among the digital values DD stored in this RAM 108. , it is determined whether the value is greater than a predetermined value.

即ち例えば第1図P1のよ5に正規の入カニリア内に入
力ペン102が当接されていれば上記6誤り検出導線7
2.71に係る誘起パルスPPのデジタル値DDは所定
値より十分に小さい筈である。その一方、不用意k例え
ば第1図P2に入力ベン102が当接されていたとする
と、上記6誤り検出導線72,71に係る誘起パルスP
Pのデジタル値DDは所定値より大きくなる筈である。
That is, for example, if the input pen 102 is in contact with the normal input canister 5 as shown in P1 of FIG.
The digital value DD of the induced pulse PP according to 2.71 should be sufficiently smaller than the predetermined value. On the other hand, if the input ben 102 is inadvertently brought into contact with, for example, P2 in FIG.
The digital value DD of P should be larger than the predetermined value.

そしてこの判断ステップにおいて上記6誤り検出導線7
2.71に係る誘起パルスPPのデクタル値DDが所定
値より大きかったとき、CPU106は他のデジタル値
DDを見ることなくエラー信号EDを不図示コンビ、−
夕零体に送出し。
In this judgment step, the above six error detection conductors 7
When the digital value DD of the induced pulse PP related to 2.71 is larger than a predetermined value, the CPU 106 outputs the error signal ED to a combination (not shown) without looking at the other digital values DD.
Send it to the Yurei body.

該コンビ、−夕本体はオペレータに対し、警告音、警告
表示等をなす。
The combination body makes a warning sound, a warning display, etc. to the operator.

一方上記判断ステ、プにおいて上記誤り検出用導$72
.71)C係る誘起パルスPPのデジタル値DDが所定
値より小さければ、CPU104は前述の各電極線走査
に係る誘起パルスPPの゛デジタル値のそ九ぞれのグル
ープの中からそれぞれの最大値を選び出し、その最大値
に係るX方向のビット電極線21−1〜21−46.同
じ(桁電極@22−1〜22−46.1方向のビット電
極線51−1〜31−38.同じく桁電極線32−1〜
52−38の各グループに付されているアドレス番号を
算出し、これをタブレッドアドレスデータTDとして不
図示コンビ、−夕本体等へ送出する。
On the other hand, in the above judgment step, the error detection guide $72
.. 71) If the digital value DD of the induced pulse PP related to C is smaller than the predetermined value, the CPU 104 calculates the maximum value of each of the nine groups of digital values of the induced pulse PP related to each electrode line scan. Bit electrode lines 21-1 to 21-46 in the X direction related to the maximum value are selected. Same (digit electrode @22-1~22-46.1 direction bit electrode line 51-1~31-38.Same digit electrode line 32-1~
The address number assigned to each group 52-38 is calculated and sent as tablet address data TD to a combination unit (not shown), a main unit, etc.

なお本実施例は静電結合型タブレット入力装置に本発明
を適用したものであるが、電磁結合盟等、他の方式のタ
ブレット入力装置にも適用し得ること勿論である。
In this embodiment, the present invention is applied to a capacitive coupling type tablet input device, but it goes without saying that the present invention can also be applied to other types of tablet input devices such as an electromagnetic coupling type tablet input device.

(効果) 以上説明したように本発明によれば信号伝送用導線と各
電極線の位置関係とかシールドに神経を遣う必要はなく
、タブレット周辺のデアトスペースがなくなると共に樹
脂筐体をも自由に使用することができる。
(Effects) As explained above, according to the present invention, there is no need to worry about the positional relationship between the signal transmission conductor and each electrode wire, or the shielding, and the space around the tablet is eliminated, and the resin casing can also be used freely. can be used.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明タブレット入力装置の一実施例を示し、第t
v!j(4)はタブレットの平面図、第1図(Blはタ
ブレットの裏面図、第2図はブロック図である。 1・・・・−・・−・・タブレット、  51.52.
61.62.・・・・・−信号伝送用導線、  71.
72・−・・−・・誤り検出用導線。 102−−−・・−・−、座標指示手段、  1(11
07,108−・−・・・・・座標特定手段
The figure shows an embodiment of the tablet input device of the present invention.
v! j(4) is a plan view of the tablet, FIG. 1 (Bl is a back view of the tablet, and FIG. 2 is a block diagram. 1... Tablet, 51.52.
61.62. ...-Conductor for signal transmission, 71.
72・-・・・・Conductor for error detection. 102---...-, coordinate indicating means, 1 (11
07,108-- Coordinate identification means

Claims (1)

【特許請求の範囲】[Claims] タブレットと、該タブレットに当接して所望の座標を指
示する座標指示手段と、該手段で指示された座標を特定
する座標特定手段を備え、前記タブレットはその信号伝
送用導線配置部分に誤り検出用導線を有し、前記座標特
定手段は座標特定にあたって前記誤り検出用導線に係る
信号が検出された場合当該座標指示を無効とすることを
特徴とするタブレット入力装置。
A tablet, a coordinate specifying means for instructing desired coordinates by contacting the tablet, and a coordinate specifying means for specifying the coordinates specified by the means, and the tablet has an error detection device in a portion where conductive wires for signal transmission are arranged. A tablet input device comprising a conducting wire, wherein the coordinate specifying means invalidates the coordinate instruction when a signal related to the error detection conducting wire is detected during coordinate specifying.
JP59281213A 1984-12-27 1984-12-27 Tablet input device Pending JPS61156328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59281213A JPS61156328A (en) 1984-12-27 1984-12-27 Tablet input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59281213A JPS61156328A (en) 1984-12-27 1984-12-27 Tablet input device

Publications (1)

Publication Number Publication Date
JPS61156328A true JPS61156328A (en) 1986-07-16

Family

ID=17635931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59281213A Pending JPS61156328A (en) 1984-12-27 1984-12-27 Tablet input device

Country Status (1)

Country Link
JP (1) JPS61156328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010020674A (en) * 2008-07-14 2010-01-28 Tokai Rika Co Ltd Touch sensor device

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Publication number Priority date Publication date Assignee Title
JPS5983281A (en) * 1982-11-05 1984-05-14 Pentel Kk Tablet input device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983281A (en) * 1982-11-05 1984-05-14 Pentel Kk Tablet input device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010020674A (en) * 2008-07-14 2010-01-28 Tokai Rika Co Ltd Touch sensor device

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