JPS61154126A - Wafer alignment mark - Google Patents

Abstract

PURPOSE:To facilitate the mask alignment by overlaying, on the edge of a dark film portion of a mask alignment mark, film layers consisting of first and second sections having different total thicknesses, with the difference being such that their reflectivity cycles are deviated from each other when they are irradiated with monochromatic light for mask alignment. CONSTITUTION:Background regions 11l and 11R have an oxide layer of a silicon wafer 13, that is a material layer for first gate oxide layer 14. Both mark regions 12L and 12R have a material layer for field oxide layer 15 instead of the material layer for first gate oxide layer 14, and the thickness of the layer 15 is different from that of the layer 14. The right-hand alignment mark has thicknesses different from those of the left-hand alignment mark, both in the background and mark regions, by 100Angstrom corresponding to the difference in thickness in a gate electrode material layer 16 plus 800Angstrom corresponding to the thickness of a material layer for second gate oxide layer 17. When the total difference in thickness between the first background region 11L and the second background region 11R is thus approximately 900Angstrom , their phases of reflectivity on a G line of mercurgty is deviated from each other by about a half wavelength.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to alignment marks, and more specifically to wafer alignment marks for photolithography that are attached to semiconductor devices and used during the manufacturing process. .

(Prior Art) In manufacturing a semiconductor device, photolithography steps are performed multiple times to form a diffusion selection mask, a contact hole, a wiring layer, and the like. In this photolithography process, in order to accurately form the noturns at desired positions, positioning, that is, mask alignment, is performed using alignment marks attached to the mask and alignment marks attached to the wafer.

In order to perform such mask alignment with good relative position, conventional techniques have been used to improve the shape of alignment marks attached to the quadrature or mask, as shown in Japanese Patent Publication No. 56-13379 or Japanese Patent Publication No. 56-12012. We are making improvements.

(Problems to be Solved by the Invention) However, these techniques do not only ensure that the edge of the mask alignment mark is clear with respect to the wafer during mask alignment work, but also that the boundary between the mark part of the wafer alignment mark and the background part is also clear. It is effective if it is clear, but if any of these are unclear,
It becomes useless because the relative position of the mask and wafer cannot be detected.

Such problems have arisen as automatic alignment devices that have come into use in recent years use monochromatic light. The reason for this will be explained below.

The k-wafer alignment mark is made of many layers that are transparent and have different refractive indexes, such as a 5R02 polysilicon layer,
It is constructed by laminating PSG layers and the like with arbitrary thicknesses, and a Renost layer is further laminated thereon during mask alignment. This is because the light reflected from each layer may interfere with each other, causing almost no reflection and causing the wafer alignment mark to become dark.

As you can see, the wafer alignment mark becomes dark,
A state in which the boundary between the edge of the mask alignment mark or the mark portion of the wafer alignment mark and the background portion becomes unclear will be described with reference to FIGS. 2 and 3.

FIG. 2(,) is a plan view of a wafer alignment mark, in which a mark portion 22 consisting of a white portion or a concave portion is formed in a background portion 21. The presence of the wafer alignment mark can be recognized by observing the light reflected from it, so when the wafer alignment mark can be observed as shown in Figure 2 (,), the background portion 21 and This is the time when reflected light from both mark portions 22 can be observed. At this time, the background part 21 and the mark part 2
Since the boundary 23 with the mark 2 reflects light in a direction different from that of the background portion 21 and the mark portion 22, it appears as a dark line.

FIG. 2(b) is a plan view of the alignment marks on the mask. The dark film portion 24 is formed by forming a light blocking layer such as chromium on a quartz glass plate or the like. The window portion 25 has the light blocking layer removed and is made only of a transparent material such as a quartz glass plate. The dark film portion does not allow light reflected from the wafer to pass through during the mask alignment process, so it is always observed as dark.

When alignment is performed by aligning the wafer 7 alignment mark with the mask alignment mark, there are four ways in which the alignment mark can be seen. First, there is a case where both the background portion 21 and the mark portion 22 are bright. In this case, the mark portion 22 can be detected by the dark line of the boundary 23, and the dark film portion 24 of the mask also has a large contrast difference with the background portion 21, making it easy to detect its edge 26. The second case is when the background portion 2I is bright and the mark portion 22 is dark. In this case, since the bright background portion 21 is sandwiched between the dark mark portion 22 and the dark dark film portion 24, the boundary 23, that is, the mark portion 22
The edges of the dark film portion 24 and the edges 26 of the dark film portion 24 can be easily detected. In this way, mask alignment is easy in the first case and the second case.

The third and fourth cases are cases where mask alignment is impossible or rather difficult, and will be explained using FIGS. 3(,) and (b).

Note that in the following plan views, hatched areas indicate dark areas. As for the hatched area, the denser area (left slanted line) indicates the dark part of the 7 alignment mark on the mask, and the less dense area (right slanted line a) indicates the dark area of the alignment mark on the mask. .

(,) indicates the third case. This is the case when the background portion 2I is dark and the mark portion 22 is bright. In this case, the two horns 23 of the mark portion 22 can be easily detected due to the contrast difference between the background portion 2Z and the mark portion 22. However, since both the background portion 21 and the dark film portion 24 are dark, the edge 26 of the dark film portion 24 cannot be detected.
Alignment is not possible.

(b) shows the fourth case. This is a case where both the background portion 21 and the mark portion 22 are dark. In this case, since the entire image is dark, both the boundary 23 and the edge 26 of the dark film portion 24 cannot be detected, and alignment cannot be performed.

As mentioned above, the reason why the wafer alignment mark becomes dark is because reflections from each layer that make up the wafer alignment mark interfere with each other. will be explained assuming that the wavelength of the d11 layer light is λ.

When light is irradiated onto a transparent layer, reflection occurs on its top and bottom surfaces. The light reflected on the bottom surface travels a longer distance than the light reflected on the top surface as it travels back and forth through the multilayer, and the light reflected on the top surface and the light reflected on the bottom surface are 2nd (n is the refractive index). A phase difference occurs.

This phase difference causes light interference and changes the brightness of the layer. This is defined as reflectance, and if the relationship between wavelength and reflectance is plotted on a graph, it becomes a periodic curve as shown in FIG. According to the graph, the reflectance is minimum at a phase difference of 1/2λ. Therefore, the layer thickness d
When becomes λ/4n, the reflectance is at its minimum and the wafer alignment mark is in a dark state where mask alignment cannot be performed.

Wafer alignment marks formed on actual semiconductor devices are made up of multiple layers, and each layer is made of a different material and has a different refractive index. Further, even on one wafer, the thickness of each layer varies from place to place, and often defects occur in the third or fourth case, making mask alignment impossible. In particular, in the case of an interlayer insulating layer made of a P2O layer or the like, such a problem is likely to occur because it is difficult to control the layer thickness of the P2O layer and the layer thickness is large.

(Means for solving the problem) The present invention has a background part and a mark part on a wafer,
This background part and mark part are the field oxide layer r-)
It is configured so that it can be identified by the difference in thickness with the oxide layer, and has a transparent layer on these oxide layers, and the dark side of the 7 alignment marks of the mask is present only in one of these background areas or mark areas. At least the background portion or the mark portion of a wafer alignment mark in which the film portions are overlapped, irradiated with monochromatic light, and the edge of the dark film portion is detected and mask aligned based on the contrast difference with the dark film portion. A portion overlapping with the edge of the dark film portion is composed of a first portion and a second portion of a transparent layer on the oxide layer having different thicknesses,
The two parts are configured so that the period of the phase of the reflectance in the monochromatic light is different, so that the reflectance of both parts does not become small at the same time. Similarly, the part of the background part or mark part of the wafer alignment mark that overlaps with the edge of the dark film part of the alignment mark of the mask is composed of a first part and a second part having different reflectances. Therefore, when the reflectance of one side decreases and becomes dark, the reflectance of the other side increases and becomes brighter, so the contrast difference between this bright area and the dark dark film area is large, and the edges of the dark film area are can be detected.

Further, the boundary between the background portion and the mark portion can be easily detected because at least one of the first portion and the second portion is bright. In this way, both the edge of the dark film portion of the mask alignment mark and the boundary between the background portion and the mark portion can be easily detected, so that mask alignment can be easily performed.

(Embodiment) FIG. 1 is a diagram for explaining the first embodiment of the present invention, in which (&) is a plan view of a wafer alignment mark;
(b) is the 11-A2 cross-sectional view. In the embodiments of the present invention, the monochromatic light used for mask alignment is H, G.
The description will be made assuming that a line (4358X) is used.

In (,), the wafer alignment mark has a first background portion 11L as a left alignment mark and a first mark portion 12L formed so as to be surrounded by the first background portion 11L, and a second background portion 11 as a right alignment mark.
R and the second mark portion 1 formed so as to be surrounded by this.
2R, and is composed of a set of adjacent left and right alignment marks.

If we explain the cross-sectional structure in (b), background part 1
1L and ZIR have a 1f-) oxide layer material layer 14 consisting of an oxide layer of the silicon wafer 13, ie a SiO2 layer. Mark portions 12L and 22R are both 1r
-) In place of the oxide material layer 14, there is a field oxide material layer 15 having a different thickness. In the wafer alignment mark of the present invention, as in the conventional case, due to the difference in thickness between the first gate oxide layer material layer 14 and the field oxide layer material layer z5, the background portion ZIL and 1
1R and mark part 12L and Z,? Make a distinction between R.

The left alignment mark has a layer of dirt electrode material 16 consisting of a polysilicon layer on the first layer of gate oxide material 14 and layer of field oxide material 15, and a second layer of dirt oxide material 17 thereon. have The thickness of each layer in this example is such that the first r-) oxide layer material layer I4 is 30
0X, the field oxide material layer 15 is 5oooX, the dirt electrode material layer 16 is 2600X, and the second dirt oxide material layer Z2 is 800X.

The right alignment mark is removed by removing the second dirt oxide material layer 17 from the left alignment mark and
- Etch the electric sign material layer 16 by 100X to a thickness of 2
500X. That is, the right alignment mark and the left alignment mark are the sum of the difference in thickness of the dirt electrode material layer 16 of 100X and the difference in the presence or absence of the second dirt oxide layer material layer 17 of 800X, that is, the thickness of each stacked layer by 900X. However, both the background part and the mark part are different.

Below, using Figures 5 and 6, the total difference in layer thickness is 9.
00^ Explain the reason for the difference.

When the wafer alignment marks shown in FIGS. 1(a) and 1(b) are used in the manufacturing process of a semiconductor device, for example, a glabella insulating layer and a resist layer are then laminated. Here, let's take the PSG layer as an example of the insulating layer between the eyebrows, and the horizontal axis is the PSG layer.
FIG. 5 shows a graph showing the relationship between the PSG layer thickness and the reflectance of the background portions ZZL and IIR, where the G layer thickness and the reflectance are plotted on the vertical axis. This is a graph of a computer simulation when the Lenost layer thickness is 9500X and the wavelength is the mercury G line (4358X). This graph:77 is 2nd = mλ (dark)...
(1) 2nd = (21+1)λ/2 (bright)
- In equation (2), n is the refractive index of each layer, d is the layer thickness in each layer, m and l are positive integers, λ = 4358X, and PSG is calculated while taking into account multiple reflections in each layer. The reflectance was calculated by changing the layer thickness.

In the figure, due to the difference in the thickness of the gate electrode material layer I6 in the background portions 11L and IIR and the difference in the presence or absence of the second dirt oxide layer material layer I7, the reflectance as a periodic function curve changes regardless of the thickness of the PSG layer. They are half out of phase.

As described above, if the total layer thickness difference between the first background portion 11L and the second background portion 11R is approximately 900X, the phase of the reflectance at the mercury G line shifts by about half a wavelength, but this can be specified from the following.

Since the first background portion 11L and the second background portion 11R are close to each other, the thickness of the PSG layer on both background portions is equal. Considering this, in order to make it easier to explain, we set the refractive index of each layer in the background part of the composite layer consisting of many layers to the same value n.
If considered as a single layer with That is,
If the total thickness d in each equation differs by Δd, then 2nd = mλ...(3
)2n(d+Δd) = (21+1)λ/2
・(4) Tonashi, Δd=(13-m)λ/2n+λ/4n (1≧m
) ・(5) becomes.

In the case of this example, 1=m, and the difference in layer thickness mainly consists of the second dirt oxide layer material layer 17, so if this refractive index of 1.4 is used for n, Δd becomes approximately 780X. Become. In reality, the values do not match the values in the example because there are multiple layers and the refractive index of the multiple layers, multiple reflections, etc. must be taken into consideration.

Incidentally, in FIG. 6, the same holds true for the mark portions 12L and 12H shown for the background portions ZIL and IIR.

As explained above, it is optimal for the phase shift of the reflectance to be half a phase shift. In actual 7-line devices, the detection sensitivity of reflected light varies between models, so it cannot be determined unambiguously, but if the reflectance is around 10 or so, it will be bright enough to match the mask. Therefore, if the phase of the reflectance is shifted to such an extent that when the reflectance of the - alignment mark becomes less than that, the reflectance of the other 7 alignment marks becomes greater than that, then mask alignment will always be possible. I will be able to do it. Further, even if it is not possible to bring the range of the phase shift of reflectance within the above range due to reasons such as the process of forming the element, the rate of failure in mask alignment can be reduced. In the currently used alignment apparatus, it is preferable to set this phase shift so that it is within a range of 174 phases before and after, with the half phase being the optimum value.

When mask alignment is performed using such wafer alignment marks, the appearance of the alignment marks will be as shown in Figure 6(a) if the thickness of the 280 layers is within the range of Figure 5A or B. , (b) or when these left and right sides are reversed.

In the wafer alignment mark of this embodiment, the left alignment mark has the same layer structure as the conventional example, so it is different from the conventional example shown in FIGS.
The case corresponds to the fourth case. Note that the cases where the right alignment mark is the third and fourth cases correspond to cases where the left and right sides of FIGS. 6(a) and 1(b) are reversed.

In Figure 6 (,), the left alignment mark is
Since the first background portion IZL is dark and the first mark portion 12L is bright, this corresponds to the third case, and mask alignment cannot be performed. However, since the reflectance of the second background portion 11R of the right alignment mark is shifted by a half phase with respect to the first background portion 11L, the second mark portion 12R is bright, while the second background portion 12R is dark. Therefore, when the left alignment mark is in the third case, the right alignment mark is in the second case, so mask alignment can be performed by scanning the scanning line on this right alignment mark. It becomes like that.

In FIG. 6(b), since both the first background portion FIL and the first mark portion I2L of the left alignment mark are dark, this corresponds to the fourth case, and mask alignment cannot be performed. In this case as well, the reflectance of the second background portion 11R and second mark portion 12R of the right alignment mark is shifted by a half phase with respect to that of the left alignment mark. Therefore, unlike the first case, the right alignment mark can be scanned with a scanning line to perform mask alignment.

Here, when the thickness of 280 layers is in the region C in Fig. 5, the alignment mark becomes somewhat dark, but since both the left and right sides have almost the same brightness to the extent that mask alignment is possible, both Positioning can also be achieved by scanning a scanning line over the 7 alignment marks.

In this embodiment, the portion removed by 900X is provided as the second background portion ZZR and the second mark portion 12RIIC of the right alignment mark, but the left and right seven alignment marks may be reversed. Further, the layer thickness difference does not need to be provided in both the background portion and the mark portion as in this embodiment, but may be provided only in the portion overlapping with the 7 alignment mark of the mask. The reason for this is that if only one of the background portions FIL or IIH becomes bright, the alignment mark can be used for mask alignment corresponding to the first or second case described above.

FIG. 7 is a diagram for explaining the second embodiment of the present invention,
The Ueno-7 alignment mark and the 72 alignment mark on the mask are overlapped to show the state of alignment.

In FIGS. 7(,) to (d), the first background portion 71 of the wafer alignment mark has the same structure as the first background portion ZIL of the first embodiment, that is, the first r-
) Oxide layer material layer, 2600X dirt electrode material layer formed on this, 800X second f-
) having an oxide layer material layer.

The second background portion 72 is the second background portion ZIR of the first embodiment.
A similar configuration, i.e., the dart electrode material layer was
Toshi no 2? -) A structure in which the oxide layer material layer is removed. The mark portion 73 may be located at the center of the background portion including the first background portion and the second background portion, in other words, at the center of the alignment mark of the mask, which may be offset from the mark portion 12L or Z2RC of the first embodiment. The mask is formed at a position where the mask can be aligned. The first background portion 71 and the second background portion 72 are placed in a positional relationship such that scanning lines 74 and 75 during mask alignment pass through the same background portion. That is, as shown in FIG. 7(,), the scanning line 7
4 and 75 pass through the edge of the mark portion 73, as for the background portion, only the first background portion 71 passes through, and as shown in FIG.
As shown in C), when passing through the center of the mark portion 73, it is configured to pass only through the second background portion 72.

In the case of this embodiment, regardless of whether the mark portion 73 is bright or dark, by selecting and scanning the first or second background portion, mask alignment is performed without using shear alignment marks as a set. Therefore, it is possible to save time compared to the first embodiment. Hereinafter, wafer alignment and one-way mask alignment in this embodiment will be explained.

As shown in the figure, the number of 7 alignment marks visible during mask alignment is 4 j5. (a) and (b) show the case where the first background portion 7z is bright and the second background portion 72 is dark.

In this case, mask alignment can be performed while scanning lines 74 and 75 pass through the bright first background portion 7z. This is because for the scanning line passing through the first background portion 71, (&) corresponds to the first case described above, and (b) corresponds to the second case. (c) and (d) show the case where the second background portion 72 is bright and the first background portion 71 is dark. In this case, mask alignment can be performed by scanning so that the scanning lines 74 and 75 pass through the bright second background portion 72. For scan lines 74 and 75 passing through the second background portion 72, (,) is in the first case (
This is because b) corresponds to the second case.

FIG. 8 is a diagram for explaining the third embodiment of the present invention, and shows the alignment between the wafer alignment mark and the mask.
The marks are overlapped to show the alignment status.

In FIGS. 8(,) to (d), the wafer alignment mark is located in the first background portion 8, which is the same as the layer structure of the second embodiment.
1 and a second background portion 82. Further, a mark portion 83 having the same layer structure as the second embodiment is provided at the center of the background portion including both of these background portions. This wafer alignment mark is a tree 7 obtained by rotating the conventional wafer alignment mark shown in FIG. 2(a) by 45 degrees, except that the background part is divided into 8z and 82. In accordance with this, the 7 alignment mark of the mask indicated by the left inclined line has also been rotated by 45 degrees.

While the second embodiment required scanning lines in two directions, vertical and horizontal, as shown in FIG. 7(λ) to (d), this embodiment required four scanning lines.
Since it is rotated by 5 degrees, it has the characteristic that it can be aligned with the scanning line 84 in one direction. That is, the scanning lines 84 on both sides separated by the mark portion 83I/c
By making the length on the background part open on both sides, horizontal mask alignment is performed, and by making the length of the scanning line a predetermined length, vertical mask alignment is performed. It is possible to align the positions. For this reason, as shown in FIG. 8, the first
The background portion 81 and the second background portion 82 are arranged vertically.

In the case of this example as well, the appearance of the alignment mark is (
By selecting the scanning lines in four ways as shown in , ) to (d), (, ) and (c) can be obtained in the first case described above.
b) and (d) allow mask alignment under the second case.

Note that vertical scanning lines cannot be used in the third embodiment of the present invention. This is because, in a vertical scanning line, the background parts through which this scanning line passes are not the same, and one of the background parts is dark, so in this dark part, the fourth case described above does not occur.
Mask matching is not possible. Therefore, when using vertical scanning lines, the first and second background portions are formed so as to be lined up in the left-right direction.

As a modified example of the wafer alignment mark of the present invention, as shown in FIG. It may be configured to have a mark portion including a second mark portion 92 having the same layer structure and a background portion 93 surrounding the mark portion.

In this case, it is preferable to perform mask alignment using a 7-alignment mark of a mask having a dark film portion 94 smaller than the mark portion, as shown in FIG.

In this mask alignment, scanning lines 95 and 96 scan the first mark portion 91 and the second mark portion 9
Make sure to pass through the brighter of the two.

In each of the embodiments of the present invention, the background part has a dirt oxide layer material layer and the mark part has a field oxide layer material layer, but due to manufacturing process reasons, etc. Needless to say, the present invention can also be applied to a case where the background portion has a field oxide layer material layer and the mark portion has a dirt oxide layer material layer.

Hereinafter, the state in which the wafer alignment mark of the present invention is formed during the manufacturing process of a semiconductor device and used for mask alignment will be explained using a semiconductor device having a MOS transistor as an element as an example, and FIGS. I will explain using

10(&) and (b) show the process of forming wafer alignment marks in the first embodiment. In the diagrams, 101 is a wafer alignment mark formation area, and 102 is an element formation area. shows.

As shown in (=), first, in a step of forming a field oxide layer 103 used for element isolation, a field oxide layer material layer 15 is formed in regions where mark portions 12L and 12R are to be formed. Next, in the step of forming the dirt oxide layer 104 of the element, an r-) oxide layer material layer z4 is formed in the region where the background portion 11L and IIR are to be formed.

After this, in the step of forming the electrode layer 105 with a thickness of 2,600 mm (1 layer) as shown in (b) K, the polysilicon layer constituting this layer has the same thickness on the area 101 where the wafer alignment mark is to be formed. A dart electric material layer 106 is formed. Next, the 1 gate electrode material layer zos is oxidized to a layer thickness of 8
In the step of forming the second dirt oxide layer 106 of 00X, the dirt electrode material layer Z6 is oxidized to form the second dirt oxide layer material layer 17 having the same thickness.

After this, in an etching process to form a contact hole in the first dirt oxide layer 104, the second dirt oxide layer material layer 17 on one side of the wafer alignment mark formation area is etched.
etching. After this, the second f-) oxide layer material layer I7 is completely removed and r-) the electrode material layer I6.
The polysilicon layer is over-etched by about 100X, resulting in 2500 layers. As a result, a wafer alignment mark having the cross-sectional structure shown in FIG. 1(b) is formed. Incidentally, impurities are diffused into the wafer 13 in any of the steps before this, and an impurity diffusion region is formed, but this will not be explained in detail.

FIGS. 10(c) to 10(,) show steps of forming a semiconductor device using the wafer alignment marks formed in the above steps.

(c) is a mask alignment process between the wafer and the mask.

After the above process, PS of about 750OX is applied as an insulating layer between the eyebrows.
Form GMlol. As mentioned above, this PSG layer 1
It is difficult to control the layer thickness of 07, and the layer thickness varies by about 100OX around 7s OOX. next,
A resist layer 10B is formed on this, and mask alignment with the mask 109 is performed. After mask alignment, 7#)'
) process is carried out.

(d) G! A state in which x-tching has been performed is shown. In the photoreno process, the aforementioned mask alignment is performed and etching is performed. After etching, resist layer 101
1 is removed. After this, stain polar pattern on A1 etc.!
10 is formed to obtain a semiconductor device having MO8IC elements as shown in (,).

By the way, as explained in the first embodiment, the present invention provides a method in which the difference in the total layer thickness of each layer stacked on the first background portion 11L and the second background portion 11R is 900X, that is, expressed by equation (5). It is preferable that the layer thickness difference Δd takes into consideration multiple reflections and the like. In the first embodiment, the thickness of the second dirt oxide layer material layer 17 is 800X under the conditions of the element formation process, and the above-mentioned layer thickness difference r is also small. A 100X overetch of the balanced material layer 16 was required. However, the second dirt oxide layer material layer 17
If the thickness of the oxide material layer 17 is larger than the above-mentioned layer thickness difference, the oxide layer material layer 17 is only removed by the above-mentioned layer thickness difference. For example, if the thickness of the oxide material layer 12 is 100X, only 900X is etched, leaving 100X.

(Effects of the Invention) As explained above, the present invention provides that the portion of at least the mark portion or the background portion of the wafer alignment mark that overlaps with the edge of the dark film portion of the alignment mark of the mask has a thickness equal to the total thickness of each layer. It is composed of a first part and a second part with different thicknesses, and the difference in layer thickness is such that the period of reflectance shifts when irradiated with monochromatic light used for mask alignment. Even if the reflectance of one of the second parts decreases, the reflectance of the other part increases, so it is easy to detect the edge of the dark film part of the mask alignment mark. This allows you to select parts and perform mask matching.

Therefore, even when laminating layers whose thickness is difficult to control and performing mask alignment, two layers with different reflectances must be stacked beforehand.
Since two portions are formed, mask alignment can be facilitated. Therefore, the wafer, which conventionally required changing the resist thickness and redoing the exposure process, can be processed for just one step, and the process can be simplified. In addition, since there is no need to consider special processes such as re-shaping, process automation becomes easy. In particular, the effect is remarkable in highly integrated semiconductor devices that require 7 to 7 cycles of processing.

Note that the unique effects of each embodiment of the present invention are summarized as follows.

The second embodiment requires only one comparison alignment mark in addition to the first embodiment, and space can be saved.

In the third embodiment, just one alignment mark is required as in the second embodiment, and furthermore, it is possible to perform alignment in both vertical and horizontal directions using only one scanning line.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams for explaining the first embodiment of the present invention, in which (a) is a plan view of a wafer alignment mark, (b) is an Al-A2 cross-sectional view thereof, Figure 2 (,
) is a top view of a conventional wafer alignment mark, (
b) is a plan view of the alignment mark on the mask, FIGS.
The figure is a graph showing the relationship between wavelength and reflectance when one layer is irradiated with monochromatic light. Figure 5 is the PSG layer thickness and reflectance in the wafer alignment mask of the first embodiment of the present invention. Graphs showing the relationship between, Figure 6 (,) and (b)
7 is a plan view of a state in which mask alignment is performed using the wafer alignment mark of the first embodiment of the present invention, and FIGS. 7(a) to (d) are wafer alignments of the second embodiment of the present invention.・The plan view of the state in which mask alignment is performed using marks, FIGS. Plan view of the state shown in Fig. 9 (,)
(b) is a plan view of the mask alignment marks used for this, and (C) is a plan view of the mask using these alignment marks. FIGS. 10(a) to 10(e), which are plan views of the alignment state, show the state in which the wafer alignment marks of the first embodiment of the present invention are formed during the process of forming elements and are used for mask alignment. Cross-sectional views in each process showing 0 11L, 71, Ell... first background part, IIR,
72°82...Second background part, 21.93...Background part, 12L. 9Z...second mark part, 12R, 92...second mark part, 22.73.83...mark part, 13.
... Quahar, 14... 1st) r'''-t oxide layer material layer, z5... Field oxide layer material layer, 16... Dirt electrode material layer, 17... Second dirt oxide layer material layer,
24.94...Dark film part. Patent applicant Oki Electric Industry Co., Ltd. Miyazaki Oki Electric Co., Ltd. Figure 1 Figure 5 Figure 6 Figure 7 Figure 8

Claims (3)

[Claims] (1) A first thickness of SiO on the background part on the wafer
2 layers, a SiO_2 layer having a second thickness different from the first thickness on a mark part provided in the background part, and a polysilicon layer having an oxidized upper part on these SiO_2 layers.・A wafer alignment mark in which a dark film portion of an alignment mark of a mask is superimposed on one of the background portion or the mark portion, and mask alignment is performed by irradiating monochromatic light; At least a portion of the portion that overlaps with the edge of the dark film portion has a total thickness of the laminated layers, the first portion having the third thickness, and the fourth portion by removing a predetermined thickness from above. The wafer alignment mark has a second portion formed to have a thickness of 1000 nm, and the difference in thickness is configured such that the phase of the period of reflectance due to interference of the monochromatic light is shifted. (2) The wafer alignment mark according to claim 1, wherein a periodic phase shift due to interference of the monochromatic light is about half a wavelength. (3) The wafer alignment mark according to claim 1, wherein the first portion and the second portion are arranged so that scanning lines during mask alignment pass through portions having the same thickness.