JPS61154127A - Wafer alignment mark - Google Patents

Abstract

PURPOSE:To facilitate the mask alignment, by constructing alignment marks such that a portion in a mark region or background region provided with a polysilicon layer is composed of first and second sections having different total thicknesses, with the difference being such that their reflectivity cycles are deviated from each other when monochromatic light is applied thereto. CONSTITUTION:A PSG layer is took as an example to be etched. The graph shows the relation between a thickness of the PSG layer and a reflectivity of mark portions 12R and 12L, taking the thicknesses on the axis of abscissa and the reflectivities on the axis of ordinate. The graph is made by computer simulation on the assumption that the thickness of a resist layer is 9500Angstrom and the wavelength is of G line of mercury (4358Angstrom ). If the difference in total thickness between the layers in the first mark section 12R and the layers in the second mark section 12L is approximately 900Angstrom , the phases of reflectivity on the G line of mercury are deviated from each other by a half wave-length.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to alignment marks, and more specifically to wafer alignment marks for photolithography applied to semiconductor devices and used during manufacturing processes. .

(Prior Art) In manufacturing a semiconductor device, multiple IJ steps are performed to form a diffusion selection mask, contact holes, wiring layers, etc. In this photolithography process, alignment marks are placed on the mask and alignment marks on the wafer to form the pattern exactly in the desired position.

In other words, mask alignment is performed.

In order to perform such mask alignment with good relative position, conventional techniques have been used to improve the shape of alignment marks attached to wafers or masks, as shown in, for example, Japanese Patent Publication No. 56-13379 or Japanese Patent Publication No. 56-12012. We are making improvements.

(Problems to be Solved by the Invention) However, these techniques do not only ensure that the edge of the mask alignment mark is clear with respect to the wafer during mask alignment work, but also that the boundary between the mark part of the wafer alignment mark and the background part is also clear. It is effective if it is clear, but if any of these are unclear,
It becomes useless because the relative position of the mask and wafer cannot be detected.

Such problems have arisen as automatic alignment devices that have come into use in recent years use monochromatic light. The reason for this will be explained below.

The wafer alignment mark is made up of a number of layers that are transparent and have different refractive indexes, such as a SiO□ layer, a polysilicon layer, a PSG layer, etc., each laminated to a desired thickness. A renost layer is laminated on the top. This is because the light reflected from each layer may interfere with each other, causing almost no reflection and causing the wafer alignment mark to become dark.

As you can see, the wafer alignment mark becomes dark,
A state in which the boundary between the edge of the mask alignment mark or the mark portion of the wafer alignment mark and the background portion becomes unclear will be described with reference to FIGS. 2 and 3.

FIG. 2(,) is a plan view of a wafer alignment mark, in which a mark portion 22 consisting of a white portion or a concave portion is formed in a background portion 21. The presence of the wafer alignment mark is recognized by observing the light reflected from it, so when the wafer alignment mark can be observed as shown in Figure 2 (,), the background portion 21 and mark portion 220 This is when the reflected light from both can be observed. At this time, since the boundary 23 between the background portion 21 and the mark portion 22 is a slope, light is reflected in a direction different from that of the background portion 2 and the mark portion 22, and a dark line appears.

FIG. 2(b) is a plan view of the alignment marks on the mask. The dark film portion 24 is formed by forming a light blocking layer such as chromium on a quartz glass plate or the like. The dark film portion 24 does not allow light reflected from the wafer to pass through during the mask alignment operation, so it always appears dark.

When alignment is performed by aligning such a wafer alignment mark and a mask alignment mark, there are four ways in which the alignment mark can be seen. First, there is a case where both the background portion 21 and the mark portion 22 are bright. In this case, the mark portion 22 can be detected by the dark line of the boundary 23, and the dark film portion 24 of the mask also has a large contrast difference with the background portion 21, making it easy to detect its edge 25. The second case is when the background portion 2 is dark and the mark portion 22 is bright. In this case, since the bright mark portion 22 is sandwiched between the dark background portion 21 and the dark dark film portion 24, the boundary 23, that is, the mark portion 22
Both the edge 25 of the dark film portion 24 and the edge 25 of the dark film portion 24 can be easily detected. In this way, mask alignment is easy in the first case and the second case.

The third and fourth cases are cases where mask alignment is impossible or extremely difficult, and will be explained using FIGS. 3(,) and (b).

Note that in the following plan views, hatched areas indicate dark areas. As for the hatched areas, the one with higher density (left slanted line) indicates the dark film part of the alignment mark of the mask, and the one with lower density (right slanted line) indicates the dark part of the alignment mark of the mask.

(,) indicates the third case. This is the case when the background portion 21 is bright and the mark portion 22 is dark. In this case, due to the contrast difference between the background part 21 and the mark part 22,
Detection of the edge 23 of the mark portion 22 is easy. However, since both the mark portion 22 and the dark film portion 24 are dark, the edge 25 of the dark film portion 24 cannot be detected and alignment cannot be performed.

(b) shows the fourth case. This is a case where both the background portion 21 and the mark portion 22 are dark. In this case, it becomes impossible to detect both the boundary 23 and the edge 25 of the dark film portion 24, which is entirely dark, and alignment cannot be performed.

As mentioned above, the reason why the wafer alignment mark becomes dark is because reflections from each layer that make up the wafer alignment mark interfere with each other. will be explained assuming that the wavelength of the d11 layer light is λ.

When light is irradiated onto a transparent layer, reflection occurs on its top and bottom surfaces. The light reflected on the bottom surface travels a longer distance than the light reflected on the top surface due to the round trip through the layer, and the light reflected on the top surface and the light reflected on the bottom surface are approximately 2nd (n is the refractive index). A phase difference occurs.

This phase difference causes light interference and changes the brightness of the layer. This is defined as reflectance, and if the relationship between wavelength and reflectance is plotted on a graph, it becomes a periodic curve as shown in FIG. According to the graph, the reflectance is minimum at the phase difference λ. Therefore, the layer thickness d is λ
/4n, the reflectance is at its minimum and the wafer alignment mark is in a dark state where mask alignment cannot be performed.

Wafer alignment marks formed on actual semiconductor devices are made up of multiple layers, and each layer is made of a different material and has a different refractive index. Further, even on one wafer, the thickness of each layer varies from place to place, often falling into the third or fourth case, making mask alignment impossible. In particular, in the photolithography process of forming a glabellar insulating layer using a PSG layer or the like, such problems tend to occur because it is difficult to control the layer thickness of the PSG layer and the layer thickness is thick.

(Means for Solving the Problems) The present invention is configured to identify a mark portion and a background portion depending on the presence or absence of a polysilicon layer, and a mask is placed on a portion of these mark portions and background portions having a polysilicon layer. In the wafer alignment mark in which the dark film portions of the alignment marks are overlapped and mask alignment is performed by irradiating monochromatic light, the portion having the polysilicon layer is replaced with an oxide layer formed on the polysilicon layer or The first portion and the second portion have a difference in thickness such that the period of reflectance due to monochromatic light during mask alignment is shifted by about a half phase due to the presence or absence of this oxide layer and the difference in thickness of the polysilicon layer. It is constructed such that the reflectance of this image area does not decrease at the same time.

(Function) As described above, in the present invention, the phase of the period of reflectance of the background part or mark part of the alignment mark, which has the polysilicon layer overlapping with the dark film part of the alignment mark of the mask, is Since it is composed of a first part and a second part that have different values, even if the reflectance of one part becomes low and it becomes dark, the reflectance of the other part increases and becomes bright, so this bright The difference in contrast between this area and the dark film part becomes large, and the edges of the dark film part can be detected.

Furthermore, since at least one of the first portion and the second portion is bright, the boundary between the background portion and the mark portion can be easily detected due to the contrast difference or the dark line at the boundary.

In this way, both the edge of the dark film portion of the mask alignment mark and the boundary between the background portion and the mark portion are easy to detect, making mask alignment easier.

(Embodiment) FIG. 1 is a diagram for explaining a first embodiment of the present invention, in which (a) is a plan view of a wafer alignment mark;
(b) is its Al-A2 cross-sectional view. In the embodiments of the present invention, the monochromatic light used for mask alignment is Hg G.
The description will be made assuming that a line (4358X) is used.

In (a), the wafer alignment mark has a first background portion 11R and a first mark portion 12R formed inside it on the right side, and a second background portion 11L and a second mark formed inside it on the left side. 12L, and is composed of a set of these two alignment marks.

To explain the cross-sectional structure in (b), the background portions 11R and IIL and the mark portions 12R and 12L are formed on the first dirt oxide layer material layer 14 of the oxide layer of the silicon wafer 13, that is, the Sio2 layer. It is identified by the presence or absence of a dirt electrode material layer 15 made of a polysilicon layer.

The alignment marks on the right indicate a 300X first dirt oxide layer material layer 14 formed on the wafer 13, a 2600X dirt electrode material layer 15 formed thereon,
A second layer formed by 800X oxidation of this r-upper electrode material layer 15
A first mark portion 12R consisting of an oxide layer material 16, and a wafer 1 surrounding this first mark portion.
The first background portion 11R is composed of a first dirt oxide layer 14 of 300X formed on the top of the third background portion 11R.

The alignment mark on the left is formed by removing the first date oxide material layer 14 and the second date oxide material layer 16 from the right alignment mark, and removing the dirt electrode material layer 15.
was etched by 100X to a thickness of 2500X. That is, the difference in thickness of the gate electrode material layer 15 between the first mark portion 12R and the second mark portion 12L is 10.
0X and the difference between the presence and absence of the second dirt oxide layer material layer 16: 800X
The total thickness of each layer differs by a total of 900X.

Below, using Figures 5 and 6, the total difference in layer thickness is 9.
The reason for making the 00X difference will be explained.

When this wafer alignment mark is used in the manufacturing process of semiconductor devices, a layer to be etched and a resist layer are laminated thereon. Here, taking the PSG layer as an example of the layer to be etched, the graph 5 shows the relationship between the PSG layer thickness and the reflectance of the mark portions 12R and 12L, where the horizontal axis is the PSG layer thickness and the vertical axis is the reflectance. As shown in the figure. This is a graph of a computer simulation when the resist layer thickness is 9500X and the wavelength is the mercury G line (4358X). This graph is 2nd=mλ (dark)...(1)2
nd=(2t+1)λ/2 (bright) −・−(
In the formula 2), n is the refractive index of each layer, d is the layer thickness of each layer, m and t are positive integers, λ = 43
58X, and P while considering multiple reflections in each layer.
The reflectance was calculated by changing the thickness of the SG layer.

In the figure, the difference in the thickness of the dirt electrode material layer 15 between mark portions 12R and 12L and the second date oxide layer material layer 16 are shown.
Due to the difference in the presence or absence of PSG, the reflectance, which is a periodic function curve, has a half phase shift regardless of the thickness of the PSG layer.

In this way, the first mark portion 12R and the second mark portion 12L
If the total layer thickness difference is approximately 900X, the phase of the reflectance will shift by about half a wavelength at the G line of mercury, but this can be determined from the following.

The first mark portion 12R (!: Since the second mark portion 12L is close to each other, the thickness of the PSG layer on both mark portions is equal. Considering this, for the sake of clarity, we will explain the above-mentioned numerous When considering a single layer in which the refractive index of each layer in the mark portion of a composite layer consisting of layers is the same value n, the above equations (1) and (2) correspond to the case where the reflectances are half out of phase. That is, if the total thickness d differs by Δd in each equation, then 2nd=mλ ・Song (3) 2n(d+Δd)=(2t+1)λ/2 −
(4) Tonashi, Δd=(L-m)λ/2 n+λ/4 n (12m
) −・−・(5).

In this example, t = m, and the difference in layer thickness is mainly due to the second dirt oxide layer material layer 16, so if this refractive index of about 1.4 is used for n, Δd becomes approximately 780X. Become. In reality, the values do not match those of the example because the structure is multi-layered and the refractive index, multiple reflection, etc. of each layer must be taken into consideration.

As explained above, it is optimal for the phase shift of the reflectance to be half a phase shift. In actual alignment equipment, the detection sensitivity of reflected light varies depending on the model, so it cannot be determined unambiguously, but if the reflectance is about 10 or more, the brightness will be sufficient for mask alignment. Therefore, as long as the phase of the reflectance is shifted to such an extent that when the reflectance of the - alignment mark becomes less than that, the reflectance of the other alignment marks becomes greater than that, mask alignment is always possible. It will be like that. Furthermore, even if it is not possible to bring the range of the phase shift of reflectance within the above range due to reasons related to the element formation process, etc., it is possible to reduce the proportion of masks that cannot be aligned. In currently used alignment devices, it is preferable to set this phase shift to be within a range of 1/4 phase shift, with half phase being the optimum value.

When mask alignment is performed using such wafer alignment marks, the appearance of the alignment marks will be as shown in Figure 6 (a) if the thickness of the P2O layer is within the range of Figure 5 A or B. , (b) or when these left and right sides are reversed.

In the wafer alignment mark of this embodiment, the left alignment mark has the same layer structure as the conventional one, so it corresponds to the conventional example in FIGS. 3, (a) and (b), that is, the third case and the fourth case. It is. Note that the cases where the right alignment mark is the third and fourth cases correspond to the case where the right and left sides of FIGS. 6(a) and 6(b) are reversed.

In Figure 6 (,), the right alignment mark is
Since the first background portion 11R is bright and the first mark portion 12R is dark, this corresponds to the third case, and mask alignment cannot be performed. However, the second mark portion 12L of the right alignment mark becomes brighter because its reflectance is shifted by a half phase with respect to the first background portion 12H. Therefore, when the right alignment mark is in the third case, the left alignment mark is in the first case, so mask alignment can be performed by scanning the scanning line on this left alignment mark. It becomes like that.

In FIG. 6(b), since both the first background portion 11B and the first mark portion 12B of the right alignment mark are dark, this corresponds to the fourth case, and mask alignment cannot be performed. In this case as well, the second mark portion 12L of the left alignment mark becomes bright because the reflectance is out of phase by half. Therefore, when the right alignment mark is in the fourth case, the left alignment mark is in the second case, so that mask alignment can be performed by scanning the scanning line on this left alignment mark. It will become.

Note that the first dirt oxide layer material layer 14 of the second background portion 11L
Since the thickness is only 300X, the phase difference in the period of the reflectance is not significant, so the reflectance is shown as not changing. As can be seen from this, the first dirt oxide layer material layer 14 of the second background portion 11L may or may not be removed.

Furthermore, when the P2O layer thickness is in the region C in Fig. 6, the alignment mark becomes somewhat dark, but the brightness on the right and left sides is the same, and alignment can be performed on either of them. can.

FIG. 7 is a diagram for explaining the second embodiment of the present invention,
The wafer alignment mark and the mask alignment mark are overlapped to show the state of alignment.

In FIGS. 7(,) to (b), the first mark portion 71 of the wafer alignment mark has the same configuration as the first mark portion 11R of the first embodiment, that is, the first mark portion 71 of the wafer alignment mark
a dirt oxide layer material layer, a 2600X dirt electrode material layer formed thereon, a second 800X dirt layer formed thereon;
It has a dirt oxide layer material layer. The second mark portion 72 has the same structure as the second mark portion 11L of the first embodiment, that is, the dirt electrode material layer is 2500X and the second dirt oxide layer material layer is removed. The background portion 73 is the first
The background portion 11R or IIL of the embodiment described above may be formed to surround the mark portion including the first mark portion and the second mark portion. The first background portion 7 and the second background portion 72 are placed in a positional relationship such that scanning lines 74 and 75 during mask alignment pass through the same mark portion. That is, when the scanning lines 74 and 75 pass through the center of the dark film portion 76 of the alignment mark of the mask as shown in FIG. As shown in FIG. 7(b), when passing through the end of the dark film portion 76, it is configured to pass only through the first mark portion 71.

In the case of this embodiment, regardless of whether the background portion 73 is bright or dark, mask alignment is performed by selecting and scanning the first or second mark portion without using shear alignment marks as a set. Therefore, space can be saved compared to the first embodiment. Mask alignment of wafer alignment marks in this embodiment will be explained below.

(,) indicates the case where the first mark portion 21 is dark.

In this case, mask alignment can be performed by scanning the second mark portion 72 with the scanning lines 74 and 75, where the second mark portion 72 is bright. With respect to the scanning line passing through the second mark portion 72, the background portion 7
3 is dark, this corresponds to the second case described above, and although it is not shown in the figure, when the background portion 73 is bright, it corresponds to the first case described above.

(b) shows a case where the second mark portion 72 is dark.

In this case, the first mark portion 7 becomes bright, and mask alignment can be performed by scanning the first mark portion 7 with the scanning lines 74 and 75. Similarly, when the background portion 73 is dark with respect to the scanning line passing through the first mark portion 2, it corresponds to the second case, and when it is bright, it corresponds to the first case. FIG. 8 is a diagram for explaining the third embodiment of the present invention, and shows a state in which the wafer alignment mark and the mask alignment mark are overlapped and aligned.

In FIGS. 8(a) to 8(b), the wafer alignment mark has a first mark portion 81 and a second mark portion 82, which are the same as the layer structure of the second embodiment. Further, a mark portion 83 having the same layer structure as the second embodiment is provided so as to surround the mark portion including both of these mark portions. This wafer alignment mark has a pattern obtained by rotating the conventional wafer alignment mark shown in FIG. 2(,) by 45°, except that the mark portion is divided into 81 and 82. In line with this, the alignment marks on the mask are also 4.
It has been rotated 5 degrees.

While the second embodiment required scanning lines in two directions, vertical and horizontal, as shown in FIGS.
Since it is rotated by 5 degrees, it has the feature that mask alignment can be performed using the scanning line 84 in one direction. That is, horizontal mask alignment is performed by making the lengths of the scanning lines 84 on both sides separated by the dark film portion 85 of the mask alignment mark open on both sides,
By setting the length of the scanning line to a predetermined length, vertical alignment can be performed. For this reason, as shown in FIG. 8, the first mark portion 81 and the second mark portion 82 are arranged vertically in correspondence with the horizontal scanning line.

In the case of this example as well, the appearance of the alignment mark is (
, ) to (b), mask alignment can be performed by selecting the scanning line that scans the brighter mark portion.

Note that vertical scanning lines cannot be used in the third embodiment of the present invention. This is because, in the vertical scanning line, the parts that the scanning line passes through are not the same, and one of the marked parts is dark, so mask alignment cannot be performed in this dark part, unlike in the fourth case mentioned above. . Therefore, when using vertical scanning lines, the first and second mark portions are formed so as to be aligned in the left-right direction.

The wafer alignment mark of the present invention is the same as the first background part 91 and second mark part 12L having the same layer structure as the first mark part 12R of the first embodiment, as shown in FIG. 9(a) as a modified row. It may be configured to have a background portion consisting of a second background portion 92 of a layered structure and a mark portion 93 at the center thereof. In this case, mark part 9 as shown in (b)
It is preferred to align the mask using mask alignment marks comprising dark film portions 94 with windows larger than 3. In this mask alignment, the scanning lines 95 and 96 are scanned so as to pass through the brighter of the first background portion 91 or the second background portion 92, as shown in (C).

Hereinafter, the state in which the wafer alignment mark of the present invention is formed during the manufacturing process of a semiconductor device and used for mask alignment will be described using FIGS. I will explain.

FIGS. 10(a) and 10(b) show the steps in which the wafer alignment marks of the first embodiment are formed.

In the figure, IQl indicates a region where wafer alignment marks are to be formed, and 102 indicates a region where elements are to be formed.

As shown in (,), first, a field oxide layer 103 used for device isolation is formed, and then a first dirt oxide layer material layer 14 is simultaneously formed in the step of forming a first dirt oxide layer 104 of the device. Next, in the step of forming the dirt electrode layer 105 of the element with a layer thickness of 2600X, the dirt electrode material layer 15 with the same thickness is formed in the regions where the mark portions 12L and 12R are to be formed.

After that, as shown in (b), the dirt electrode material layer 15 is oxidized in the step of oxidizing the y-to electrode layer 105 of the element to form a second dirt oxide layer 106 with a layer thickness of 800X, and a second dirt electrode layer 106 with the same thickness is oxidized. A two-dirt oxide layer material layer 16 is formed. Next, the first dirt oxide layer 104 is etched to remove the first dirt oxide layer material layer 14 in the second background portion 11L in a step of forming a contact hole.

At the same time, the second dirt oxide layer material layer 16 is completely removed and the silicon layer above the date electrode material layer 15 is overetched by 100X to 2500X. As a result, a wafer alignment mark having the cross-sectional shape shown in FIG. 1(b) is formed.

Incidentally, impurities are diffused into the wafer 13 in any of the steps before this, and an impurity diffusion region is formed, but this will not be explained in detail.

FIGS. 10(c) to 10(,) show steps of forming a semiconductor device using the wafer alignment marks formed in the above steps.

(c) is a mask alignment process between the wafer and the mask.

After the above process, PS of about 750OX is used as an interlayer insulating layer.
A G layer 107 is formed. As mentioned above, this PSG layer 1
07 is difficult to control the layer thickness, mainly 7500X,
The layer thickness varies by about 1OOOX. Next, a resist layer 108 is formed on this, and mask alignment with a mask 109 is performed. After mask alignment, a photolithography process is performed.

(d) shows the state where etching has been performed. In the 7th etching process, the aforementioned mask alignment is performed and etching is performed. After etching, resist layer 10B is removed. Thereafter, an electrode pattern 110 is formed using U or the like to obtain a semiconductor device having a MO8IC element as shown in (,).

By the way, in the present invention, as explained in the first embodiment, the difference in the total layer thickness of each layer laminated on the first mark portion 12B and the second mark portion 12L is 900X, that is, expressed by equation (5). It is preferable that the layer thickness difference Δd takes into consideration multiple reflections and the like. In the first embodiment, the thickness of the second dirt oxide layer material layer 16 is 800X, which is smaller than the above-mentioned layer thickness difference under the conditions of the element formation process. It was necessary to over-etch by 100X. However, if the thickness of the second dirt oxide layer material layer 16 is greater than the above-mentioned layer thickness difference, this oxide layer material layer 16 is only removed by the above-mentioned layer thickness difference. For example, if the thickness of the oxide material layer 16 is 100X, only 900X is etched, leaving 100X.

(Effects of the Invention) As explained above, the present invention provides that at least the mark portion or background portion of a wafer alignment mark has a portion where a polysilicon layer is formed, and the total thickness of each layer constituting the portion is different. Consisting of a first part and a second part,
The difference in layer thickness is such that the period of reflectance shifts when monochromatic light used for mask alignment is irradiated, so the reflectance of one of these first or second portions decreases. However, since the reflectance of the other side is high, it becomes easy to detect the edge of the dark film portion of the mask alignment mark, and it becomes possible to select this high reflectance portion for mask alignment.

Therefore, even if layers whose thicknesses are difficult to control are laminated and mask alignment is performed, since two portions with different reflectances have been formed beforehand, mask alignment can be facilitated. Therefore, wafers that conventionally required changing the lenost thickness and redoing the exposure process can be processed as they are, simplifying the process. Furthermore, since there is no need to consider special processes such as redoing, process automation becomes easy. Especially 10 times~
This effect is remarkable in highly integrated semiconductor devices that require several times of reconstitution.

Note that the unique effects of each embodiment of the present invention are summarized as follows.

The second embodiment requires only one comparison alignment mark in addition to the first embodiment, and space can be saved.

In the third embodiment, just one alignment mark is required as in the second embodiment, and furthermore, it is possible to perform alignment in both vertical and horizontal directions using only one scanning line.

[Brief explanation of the drawing]

1(a) and (b) are diagrams for explaining the first embodiment of the present invention, in which (a) is a plan view of a wafer alignment mark, (b) is an Al-A2 cross-sectional view thereof, Figure 2 (,
) is a top view of a conventional wafer alignment mark, (
b) is a plan view of the mask alignment mark; Figs. 3(a) and (b) are plan views of a state in which mask alignment cannot be performed using conventional wafer alignment marks; Fig. 4 is a plan view of a single layer mask alignment mark. A graph showing the relationship between wavelength and reflectance when a layer is irradiated with monochromatic light. FIG. 5 is a graph showing the relationship between PSG layer thickness and reflectance in the wafer alignment mark of the first embodiment of the present invention. , Figure 6(,) and (b
) is a plan view of a state in which mask alignment is performed using wafer alignment marks according to the first embodiment of the present invention, and FIGS. FIGS. 8(a) to 8(b), which are plan views showing mask alignment performed using alignment marks, show mask alignment using wafer alignment marks according to the third embodiment of the present invention. Plan view of the state in which the
) is a plan view in which the mark portion is used instead of the background portion to form a portion with a different phase of reflectance, (b) is a plan view of the alignment marks of the mask used for it, and (C) is the plan view of the mask using these alignment marks. FIGS. 10 (,) to (,), which are plan views of the state in which alignment is being performed, show the state in which the wafer alignment marks of the first embodiment of the present invention are formed during the process of forming elements and are used for mask alignment. Cross-sectional views showing each process. 11R, 91...first background part, 11L, 92...
Second background part, 21.73.83...Background part, 12
R, 71, 81...first mark portion, 12L. 72.82... Second mark portion, 22.93... Mark portion, 13... Wafer, 14... First dirt oxide layer material layer, 15... Dirt electrode material layer, 16...
・Second dirt oxide layer material layer, 24.76.85.94・
...Dark film part. Figure 1 Figure 2 Figure 5 psG, 4 fiJ CA) Figure 6 Figure 9

Claims (3)

[Claims] (1) having a background portion and a mark portion in the background portion on the wafer, one of the portions being formed of a polysilicon layer, and having an oxide layer on the polysilicon layer;
A wafer alignment mark that identifies the background portion and the mark portion depending on the presence or absence of the polysilicon layer, wherein the alignment mark of the mask is placed on a portion of the background portion or the mark portion where the polysilicon layer is formed. In a wafer alignment mark in which dark film portions are overlapped and mask alignment is performed by irradiating monochromatic light, in the portion where the polysilicon layer is formed, the total thickness of each layer is a first thickness. and a second portion formed to have a second thickness by removing a predetermined thickness from above, and the difference in thickness causes a phase shift in the period of reflectance due to interference of the monochromatic light. A wafer alignment mark composed of various types. (2) The wafer alignment mark according to claim 1, wherein a periodic phase shift due to interference of the monochromatic light is about half a wavelength. (3) In claim 1, the first portion and the second portion are wafer alignment marks arranged so that scanning lines during mask alignment pass through portions having the same thickness.