JPS6115249A - Tlb control system - Google Patents

Abstract

PURPOSE:To increase the processing speed by changing the bit of a TLB (translation look-aside buffer) entry of a page immediately preceding the page of a TLB entry to be replaced. CONSTITUTION:A virtual address is loaded to an MAR32 in order to give memory access to a main memory 10. Then the intra-page offset contained in the loaded virtual address of the MAR32 is led to a boundary checking circuit 36. The circuit 36 checks whether or not an access covers a page boundary as long as the memory access given to the memory 10 is equal to full-word access. In this example, a page equal to 2KB and therefore the Offset contains 11 bits. In such a case, it is just required for the circuit 36 to check whether the Offset is shown or not as ''7FE'' in the hexadecimal expression as long as the memory access is equal to full-word access of a half-word boundary. The result of this check is delivered to a control circuit 37 in the form of a signal PAGEBD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a TLBIII11 system in a virtual storage control system computer equipped with T and LB.

[Technical Background of the Invention] Generally, in a computer using a virtual memory control method, in order to perform address conversion from a virtual address to a real address at high speed, T l 3 (Lranslatton LOOka
A hardware mechanism called a near address translation buffer is provided.

Each entry of this TLB has a field of address translation information including a real page number and a valid bit indicating whether the corresponding entry is valid (valid) or not (invalid).

The TLB is indexed using a predetermined field of the virtual address during memory access. Then, the validity of the memory access is checked based on the predetermined field of the virtual address and the contents of the corresponding entry in the TLB. If the validity is guaranteed by this check, memory access is performed using the real address (q) by the real page number in the corresponding entry and (the offset of) the virtual address.On the other hand, if the validity is guaranteed, If it is not guaranteed, the corresponding entry in the TLB is replaced, and then memory access is performed.

[Problems in the Background Art] However, in computers using the conventional virtual memory control method using the TLB described above, for example, halfword boundaries (Half
word Boundary)'7/L,
'7-Fullword Accesses
s) and a page boundary (Paoe Boun
dary ) Omata < When accessing memory, etc.
There was a drawback that the processing speed decreased. This is because when one memory access spans two pages, it is necessary to check each TLB entry corresponding to both pages and ensure the validity of the same memory access before performing the memory access. .

[Objective of the Invention 1] This invention has been made in view of the above circumstances, and its purpose is to provide a structure in which control information for the next page is set in each entry of the TLB, thereby reducing memory access across page boundaries. Even in the case of , the TL corresponding to the first page
A TLB that can guarantee the validity of this type of memory access just by checking the B entry, thereby improving processing speed.
The objective is to provide a control method.

Another object of the present invention is that the state of a modify bit, which is prepared in page tables 1 to 1 and indicates whether or not the corresponding page has been rewritten, can be easily grasped even in the case of memory access spanning two pages. The purpose is to do so.

Still another object of the present invention is to use the TLB
The purpose is to reduce the number of times entries are replaced.

[Summary of the Invention 1 In the present invention, in a computer using a virtual memory control method, each TLB entry has a bit V' indicating the validity/invalidity of the entry, and a bit V' of the TLB entry corresponding to the page next to the page indicated by the entry. Bit VN indicating valid/invalid
i (i-1, -n, n is an integer greater than or equal to 1), and a TLB including a field of address translation information. The first detection means stores correct address translation information in the target virtual address, the bits V' and VNi of the TLB entry corresponding to the target virtual address, and a predetermined field of address translation information when accessing the memory. and whether correct address translation information is stored in the TLB entry corresponding to the page next to the page indicated by the same entry. Further, the second detection means detects whether one memory access spans two pages. The replacement means replaces the corresponding entries in the TLB according to the detection results of the first and second detection means.

When replacing TLB entries using this replacement method,
The bit V' of the TLB entry to be replaced is unconditionally set, and the bit VN1 is unconditionally reset.

Also, the bit VN of the TLB entry that corresponds to the page immediately before the page indicated by the TLB entry to be replaced.
I is changed.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

The drawing shows the configuration of the main parts of a virtual storage control type computer to which the present invention is applied, and 10 is a main memory. Main memory 10 includes a segment table 11 indicating segment information of a virtual address space and a page table 12 indicating page information in each segment. Each entry in the segment table 11 has a field of a valid bit V indicating whether the entry is valid or invalid, main memory protection information P of the segment, LEVEL, and a page table starting address PTO which is the starting address of the corresponding page table 12. has. Each entry in the page table 12 also has a valid hit V indicating whether the entry is valid or invalid, and a valid hit V indicating that the corresponding page has been rewritten (that is, the contents of the corresponding page in the virtual space are It has a field for a modify bit M (indicating that it is necessary to match the contents of the page) and a real page number (address) RPA for converting a virtual address to a real address.

20 is a data bus, and 30 is a performance W device. The arithmetic control unit 30 connects the main memory 1 to the main memory 1 via the data bus 20.
Connected to 0.

In the arithmetic and control unit 30, 31 is a PSW (program status word). Mode information MODE indicating the program running mode (protection priority level) is stored in a predetermined field of the PSW 31. 32 is a memory address register (MAR) that holds virtual addresses.
It is. The virtual address is logically segment number S.
N, page number PN, and intra-page offset Qff
It is divided into sets. 33 is a protection register that temporarily holds the main memory protection information P and LEVEL stored in the entry (segment table entry) of the segment table 11, and 34 is stored in the page table 12 (page table entry). There is an RPA register that temporarily holds the real page number RPA.

35 is a TIB for quickly converting an address from a virtual address to a real address. TLB35 is TL
It consists of two sets, B35A and 35B, and is information on concatenation of a part of the segment number SN of the virtual address held in the MAR32, for example, the lower bits, and a part of the page number PN, for example, the lower bits (a part of the SN is (lower)
indexed by TLB35 (TL835A,
Each entry (TLB entry) of 35B> has address translation information consisting of control sections C3, SN-, PN', and RPA, and fields of P and LEVEL. Control section C8 has bit v-
, hit M', bit VNA, bit I-VNB, bit MNA, and bit MNB. The bit V' is
Indicates whether the corresponding TLB entry is valid 7 or invalid, and the pin 1
-VNA and VNB are TLB entries (TLB55A) corresponding to the page next to the page indicated by the same entry.
, 35B entry) is valid/invalid. Also,
Bit M' indicates the state of modify bit M of the entry in page table 12 of the corresponding page, and bit MNA.

MNB indicates the state of the modify bit M of the J entry in the page table 12 of the page next to the corresponding page. SN- corresponds to the remaining bits (higher bits) of the segment number SN, and PN- corresponds to the remaining bits of the page number PN. Also, for example, each entry in TLB 35B has a reference pitch hR. Bit R is
It shows which of the corresponding entries in TLB 55A and 35B (that is, which one of the corresponding entry on the A side of TLB 35 and the corresponding entry in B11) was referenced the earliest.

36 is a boundary check circuit that checks whether the target memory access straddles a page boundary based on the intra-page offset 0ffset of the virtual address held in the M A R 32, and outputs a signal PAGEBD indicating this;
37 is a control circuit for controlling the TLB 35, etc., and 38 is a register that holds real addresses. The control circuit 37 includes an index result for the TLB 35 (specifically, a control section C
8, SN′, PN=, and P, LEVEL), MAR
SN of the virtual address held in 32, signal PAGE8D from the upper pick 1-1 boundary check circuit 36 of PN,
Various memory control signals are guided from a microprogram control section (not shown). These memory control signals include a signal MREQ indicating a memory access request, a signal RD indicating a memory read, a signal WR indicating a memory write, a signal IF indicating an instruction fetch, and a signal FW indicating a full word access. be.

Next, the operation of one embodiment of the present invention will be explained.

Now, for memory access to main memory 10, M
Assume that a virtual address has been loaded into the AR32. M
The intra-page offset Qffset in the virtual address loaded into the AR 32 is directed to the boundary check circuit 36. Thereby, the boundary check circuit 36 checks whether or not the memory access to the main memory 10 described above is a full word access, and whether or not the access straddles a page boundary. In this example, one page is 2 KB, so Qffset consists of 11 bits. In this case, assuming fullword access on a halfword boundary, the boundary check circuit 36
All you have to do is check whether Qffset is °' 7 F E '' in hexadecimal representation. Boundary check circuit 3
6 is a control circuit 3 which uses the check result based on QffSet from the MAR 32 as a signal PAGEBD.
Output to 7.

On the other hand, the linkage information between the lower bits of segment No. 1 SN in the virtual address loaded into the MAR 32 and the lower bits of the page M@PN is guided to the TLB 35. Accordingly, the TLB 35 is indexed using the above connection information.

As a result, T L B35 (T L B55A, 35
From B), the stored information for the corresponding en] is read out. T
Among the read information from LB35, v'.

M-, VNA, VNB, MNA, MNB, S\'.

PM, P, LEVEL, R (T for R 835B
) is led to the control circuit 37. Also,
The control circuit 37 includes the upper bits of SN of the virtual address loaded into the MAR 32 (SN1. the upper bits of PN (PN-), and the MOD from the PSW 31).
E is also guided. Based on this input information, the FUIN 1 to roll circuits 37 output the signals MISS, PRT, MOD, and NEX.
T: MISS.

NEXT: Generate MOD. Signal MISS is TLB
This indicates that the corresponding entry of No. 35 does not have new address translation information (for address translation from a virtual address to a real address), that is, a miss (TLB miss pit).

Signal PRT indicates that the operating mode indicated by PSW31 does not have memory access rights to that segment;
In other words, this indicates a main memory protection violation. The signal MOD is
This indicates that the modify bit M of the corresponding entry in the page table 12 is not set (this is called a modify). Message @NEXT: MISS is the TLB corresponding to the page next to the page you are currently trying to access.
Indicates that the entry was not created correctly, that is, a next page miss. The signal NEXT:MOD indicates that the modify bit M of the page table entry corresponding to the page next to the page to be accessed is not set, that is, the next page is modified. The generation logic of these signals is as follows.

■ Miss MISS=HIT HIT=HITA+HITB HIT+ =Vl ・ (SN-=TLB: (SN-))・
(PN-=TLB: (PNi) Note that SN-, P
N' is SN from MAR32.

Indicates the upper bit of PN, V: , TLB+(SN-)
, TLB+ (PN-) is TLB35° (i=A,
B) (7) Applicable Int 1l) V, SN-.

PN' is shown. Therefore, H1+(i=A.

B) indicates that correct address translation information exists in the corresponding J-1-li of the TLB 35i. From this, it will be understood that HIT indicates that there is correct address translation information on either the A side or the B side of the corresponding entry in TLB 35, that is, HIT (TLB hit).

■ PRT PRT = HITA ・(MODE≧P, LEVELA)+H
ITa・(MODE≧P, LEVELe) In addition, P,
LEVEL+ (i=A, B) indicates P and LEVEL of the corresponding entry in TLB 35i.

■ MOD MOD=HI TA-tVI day+HITa・-&“-
Note that M+ (i=A, B) indicates M of the corresponding entry of 71335i.

■ NEXT:Miss NEXT:MISS =HITA・(VNAA+VNBA) +HITa・(VNAs +VNBs) Note that VN
A+, VNB+ (i = A, B) Lt, T L
B 35 i (7) 15 To I nt! J (7)
VNA and VNB are shown.

■ NEXT:~jOD NEXT:MOD =HITA・(MNAA +MNBA) 10HITa・
(MNAB +MNBB) In addition, MNA+, tvl
NB+ (i-A, B)l indicates MNA and MNB of the corresponding entry in TLB 35i.

The signals shown in ■ to ■ above are supplied from the control circuit 37 to a microprogram control section (not shown), and are used to check the validity of the memory access (by the microprogram) before performing memory access. .

Further, in this embodiment, the control circuit 37 is also configured to check the validity of memory access. This is because, in the case of an instruction that accesses memory only once, such as a load instruction, if the validity of the memory access was checked using the microb 0 setter, the processing speed would drop significantly. This is because it is possible to store it away. That is, the control circuit 37 checks the validity of the memory access in a hardware manner using the signals ① to ① described above, as well as various memory control signals from the microprogram 111111 section. If the correctness of memory access cannot be guaranteed, the control circuit 37 generates an interrupt at the firmware level before executing the instruction. In this case, the mishit interrupt signal Miss:lNT1, the main memory protection violation interrupt signal PRT:INT, and the modify interrupt signal MOD:
INT, next page miss interrupt signal @NEXT :M
ISS: INT and further the next page modify interrupt signal NEXT: MOD: INT are generated according to the logic shown below.

■ MISS:INT MISS : INT =MISS-MREQ ■ PRT:INT PRT:INT -~+188-PRT-MREQ ■ MOD:INT MOD+INT ■ NEXT :~ll5S:INT NEXT:MISS: INT -MI SS -P RT・( MOD-WR)・NEX
T:Miss-NEXT:MREQNEXT:MR
EQ = MREQ-PAGEBD-FW ■ NEXT :MOD : INTNEXT :M
OD+INT/NEXT:MREQ-WR As is clear from the logic described above, the interrupts (signal@) of the above ■ to [phases] have a priority order of interrupt generation. In the above example, ■ (miss hint interrupt) has the highest priority, followed by ■, then ■, and ■ (next page modification) has the lowest priority.

According to the above logic, if a mishit is detected (
Under the control of the microprogram control section), the control circuit 37 replaces the corresponding entry in the TLB 35 as described later. Furthermore, in the case of a main memory protection violation, an interrupt is generated at the software level. Also, in the case of a modified interrupt),
11, the modification bit M of the corresponding entry in the page table 12 and the corresponding entry in the TLB 35 are set. In addition, in the case of a next page miss, TLB35 is
The corresponding entries are replaced. In addition, in the case of next page modification, the modification bit M of the corresponding entry in the page table 12 is set, as in the case of modification (interrupt), and then T L B
The contents of 35 are changed. Note that next page misses and next page modifications may occur when full word access is performed across page boundaries.

Here, a case will be described in which the contents of the TLB 35 are changed, such as replacing a corresponding entry in the TLB 35. In the following description, the virtual address loaded into the MAR 32 will be referred to as a target virtual address, and the entry in the TLB 35 corresponding to the target virtual address will be referred to as a TLBI entry. In addition, the TLB entry set corresponding to the page immediately before the target virtual address is set as the TLB entry set immediately before the target virtual address.
The TLB entry set corresponding to the page immediately after the target virtual address is called the TLB entry set immediately after.

(1) In the case of a miss during a memory read When a miss (interrupt) occurs during a memory read, the main memory protection information P, LEV in the corresponding entry of the segment table 11 is first read under the control of the microprogram control unit.
EL is loaded into the protection register 33, and the real page number RPA in the corresponding entry of the corresponding page table 12 is loaded into the RPA register 34. P and LEVEL are obtained by accessing the segment tilt pull 11 using the segment table starting point address stored in a segment table starting point register (not shown) and the segment number SN of the virtual address. At this time, the page table starting point address is also obtained. In addition, RPA is
It is obtained by accessing the corresponding page table 12 using the page table starting point address and the page number PN of the virtual address.

P, LEVEL# and RP/l'0-F, a TLB replace (read) command is issued by the microprogram. With this command, TLB35A, 35B
Among the corresponding entries, the entry that was referenced the earliest, for example, the corresponding entry in TLB 35A (A side of TL 835) is rewritten. At this time, either the A side or the B side is rewritten (in this example, the A side) is stored.

In this rewriting (replacement), SN=, PN' of the target virtual address, P from the protection register 33, LE
VEL and RPA from the RPA register 34 are written into a predetermined field of the corresponding entry in the LB. Also, bit V' of the TLB corresponding entry is set, bit V
NA, VN8. M, MNA, and MNB are reset.

However, MNA and MNB may remain unchanged. Note that the entry to be rewritten (replaced) is T L B
35A side or TLB 35B side is determined based on the reference bit R in the corresponding entry of TLB 35B. When rewriting, the above reference bit I
n) Logical values are inverted.

After the above-described rewriting, the contents of MAR 32 are changed to indicate one page before the target virtual address, and then a control section change (read) command is issued. This command simultaneously changes the control section C8 of the TLB immediately preceding entry set.

The contents of this C8 change are that the TLB immediately preceding entry set is
It has correct address translation information corresponding to the virtual address set in M A R32 (virtual address indicating one page before the target virtual address) (TLB hit)
or not (TLB miss) as follows. However, the following example is a case where AIall of TLB 35 is replaced by a TLB replace (read) command.

a) In case of TLB hit V: Unchanged VNA: Set VNB: Unchanged (reset) M: Unchanged MNA: Reset MNB: Unchanged (reset) b) In case of TLB miss V: Unchanged VNA: Reset VNB: Unchanged N1: Unchanged MNA: Reset MNB: Unchanged (2 In case of a miss during memory write The TLB control procedure when a miss (interrupt) occurs during memory write is ) commands are stored in memory, except that a control section change (write) command is applied instead of a control section change (read) command, and the modify bit M of the corresponding entry in page table 12 is set. This is the same as when reading. In this case, the control section C8 of the TLB corresponding entry and TLB immediately preceding entry set is as follows.

a) Two sets of TLB corresponding entry V VNA: Reset VNB: Reset M; Set MNA: Reset MNB: Reset b) Reset the end immediately before TLB However, if side A is replaced b-1) In the case of TLB hit ■: Unchanged VNA: Set VNB: Unchanged (reset) M: Unchanged MNA: Sera 1~ MNB: Unchanged (reset 1-) b-2> In case of TLB miss V: Unchanged VNA: Reset 1~ VNB: Unchanged M: Unchanged MNA: Reset MNB: Unchanged (3) Modify interrupt during memory write When a modify interrupt occurs during memory write, the modify bit M of the corresponding entry in page table 12 is first set.
is set. Next, the target virtual address is set in the MAR 32, and then a set/modify command is issued. This command sets bit M1 in the TLS11 entry (assumed to be the corresponding entry on the A side of TL835). Next, M.A.
The contents of R32 are changed to indicate one page before the target virtual address, and then the control section
A change (modification) directive is issued. This command changes the control section C8 of the TLB immediately preceding entry set. The details of this C8 change are as follows:
Depends on whether the B-immediate entry set correctly has address translation information corresponding to the virtual address set in MAR32 (virtual address indicating one page before the target virtual address) (TLB hit) or not (TLB miss). ,
They differ as follows. However, the following example is a case where bit M in the corresponding entry on the A side of the TLB 35 is set by a set/modify command.

a) In case of TLB hit V: Unchanged VNA: Unchanged (set) VNB: Unchanged N・1: Unchanged MNA: Set MNB: Unchanged b) In case of TLB miss V: Unchanged VNA: Unchanged (reset) VNB: Unchanged M; Unchanged MNA: Unchanged (reset) MNB: Unchanged According to the TLB control described above, the latest information for not only the corresponding page but also the next page is correctly set in the control section C8 of each entry of the TLB 35. For example, if a miss (interruption) occurs during a memory read using a virtual address, the corresponding TLB entry is replaced. At this time, V and M are uniquely set to correct values. At this time, with the replacement of the corresponding TLB entry, the TLBr entry entry set, VNB, MNA, and MNB are also changed to reflect the state of the corresponding TLB entry. In addition, in this embodiment, when the corresponding TLB entry is replaced, the VNi and MNi of the TLB corresponding entry are
It does not necessarily reflect the state of the entry set immediately after B correctly. However, TLBii! When a post-end reset is replaced, the V of the corresponding TLB entry is
Ni.

MNi always correctly reflects the state □ of the entry set immediately after TLB.

In addition, if the above memory read is a full word access that spans page boundaries, and the TLB1 entity entry conversion information is not stored correctly for any page, the TLB entry can be changed as follows. Changes are made. In this case, as is clear from the interrupt priority order, it will be treated as a miss, and the corresponding TLB entry on the first page will be replaced (including changing O3), and the entry set immediately before that TLB will be replaced with O8 (VN
A, VNB, MNA, MNB) will be changed. If an attempt is made to perform the full word access described above again, this time it will be treated as a next page miss. In this case, replace the corresponding entry in the TLB of the next page (including changing C3) and the entry set immediately before that TLB, that is, C8 of the corresponding entry in the TLB of the first page.
(VNA, VNB, MNA, MNB) are changed. As a result, information indicating that correct address translation information is stored in the TLB corresponding entry corresponding to the first page is set in both the entry and the entry set immediately after the TLB.

In addition, when a memory write access is performed to a page in which a TLB entry has been entered due to a miss during a memory read, a modify interrupt is generated (if a main memory protection violation does not occur), and the bit of the TLB entry is Only M is set. At this time,
C8 (MN i inside) of the TLB immediately before end reset is changed to reflect the state of the corresponding TLB entry. Additionally, the modify bit M of the corresponding entry in the page table 12 is also set. If you want to reduce the number of set operations for the modify bit M of the page table 12 without applying a modify interrupt, modify (interrupt), next page modify (
The states corresponding to (interrupts) may also be treated as misses (interrupts) and next page misses (interrupts). However, in this case, the TLB entry is replaced, so
Since access to the segment table 11 and page table 12 is required, the efficiency is lower than that of the above-described method.

In the above embodiment, the main memory protection information P, LEVE
Although the case where there is one type of L has been described, the present invention is not limited to this. For example, to improve the efficiency of main memory protection,
The same method can be implemented even when three types of main memory protection information are prepared: read protection, write protection, and instruction execution protection. In this case, main memory protection violation is detected using main memory protection information corresponding to the type of memory access.

[Effects of the Invention] As described in detail above, according to the present invention, the following effects can be achieved.

■ Since the latest control information for not only the relevant page but also the next page is correctly set in each TLB entry, even in the case of memory access that crosses page boundaries, this type of control information can be solved by simply checking the TLB entry corresponding to the first page. The validity of memory access can be guaranteed, and therefore processing speed can be improved.

■ When adopting a method of preparing a modify bit in a page table entry that indicates whether the corresponding page has been rewritten, the state of the modify bit can be easily grasped even when memory access spans two pages. The number of times the modify bit of a table entry is set can be reduced.

(2) In the case of adopting a method in which modification hits of page table entries can be easily ascertained, it is possible to eliminate the need to replace the corresponding TLB entry when memory is written to a page that was previously read accessed.

[Brief explanation of the drawing]

The drawing is a block diagram showing the configuration of the main part of the calculation method of the virtual storage control system according to an embodiment of the present invention. 10... Main memory, 11... Segment table,
12...Bage table, 35...TLB, 36...
...Boundary check 4 circuits, 37...Control circuit.

Claims (3)

[Claims] (1) In a computer using a virtual memory control method, each TLB entry has a bit V' indicating whether the entry is valid or invalid;
T corresponding to the page following the page indicated by the same entry
Bit VNi (i=1
, ... n, n is an integer greater than or equal to 1), and a TLB including a field of address translation information, a target virtual address, and the bits V' and VNi of the TLB entry corresponding to the target virtual address upon memory access. , and a predetermined field of address translation information, it is determined whether correct address translation information is stored in the same entry, and whether correct address translation information is stored in the TLB entry corresponding to the page next to the page indicated by the same entry. a first detection means for detecting whether one memory access spans two pages; a second detection means for detecting whether one memory access spans two pages; a replacement means for replacing the corresponding entries; and when the replacement means replaces the TLB entries, the above-mentioned bit V' of the TLB entry to be replaced is
A TLB control method comprising means for setting bit VNi and resetting bit VNi, and means for changing bit VNi of the TLB entry corresponding to the page immediately before the page indicated by the TLB entry to be replaced. (2) In a computer with a virtual memory control system, which has a page table in which each page table entry has a modify bit indicating whether the corresponding page has been rewritten and a field for the real page number, each TLB entry has the same Bit V' indicating validity/invalidity of entry, TLB corresponding to the page following the page indicated by the same entry
Bit VNi (i=1, ・
...n, n is an integer greater than or equal to 1), bit M' indicating the state of the modify bit of the above page table entry corresponding to the page indicated by the same entry, and bit M' indicating the state of the modify bit of the above page table entry corresponding to the page indicated by the same entry, the above corresponding to the page next to the page indicated by the same entry. Bit MN indicating the state of the modify bit of the page table entry
i, and a TLB containing a field of address translation information.
At the time of memory access, it is determined whether correct address translation information is stored in the entry based on the target virtual address, the bits V′ and VNi of the TLB entry corresponding to the target virtual address, and a predetermined field of address translation information. whether correct address translation information is stored in the TLB entry corresponding to the page following the page indicated by the same entry, and the state of the modify bit of the page table entry corresponding to the page indicated by the same entry. , a first detection means for detecting the state of the modify bit of the page table entry corresponding to the page next to the page indicated by the same entry, and a first detection means for detecting whether one memory access spans two pages. 2 detection means; a replacement means for replacing the corresponding entries of the TLB according to the detection results of the first and second detection means; and when the replacement means replaces the TLB entries, the bit V of the TLB entry to be replaced is detected. ' and bit VNi
and reset/set the bit M' in response to memory read/write, and memory read bits VNi and MNi of the TLB entry corresponding to the page immediately before the page indicated by the TLB entry to be replaced. / A TLB control method characterized by comprising: means for changing according to the write. (3) In a computer with a virtual memory control system, which has a page table in which each page table entry has a modify bit indicating whether the corresponding page has been rewritten and a field for the real page number, each TLB entry has the same Bit V' indicating validity/invalidity of entry, TLB corresponding to the page following the page indicated by the same entry
Bit VNi (i=1, ・
...n, n is an integer greater than or equal to 1), bit M' indicating the state of the modify bit of the above page table entry corresponding to the page indicated by the same entry, and bit M' indicating the state of the modify bit of the above page table entry corresponding to the page indicated by the same entry, the above corresponding to the page next to the page indicated by the same entry. Bit MN indicating the state of the modify bit of the page table entry
i, and a TLB containing a field of address translation information.
When accessing the memory, correct address translation information is stored in the entry using the target virtual address, the bits V', VNi, M', MNi of the TLB entry corresponding to the target virtual address, and a predetermined field of address translation information. Whether correct address translation information is stored in the above TLB entry corresponding to the page following the page indicated by the same entry, and whether the above page table entry corresponding to the page indicated by the same entry is stored. a first detection means for detecting the state of the modify bit and the state of the modify bit of the page table entry corresponding to the page next to the page indicated by the same entry; and whether one memory access spans two pages. a second detection means for detecting whether the
The above T according to the detection results of the first and second detecting means.
An exchanging means for exchanging the corresponding entry of the LB, and when exchanging the TLB entry by this exchanging means, sets the above-mentioned bit V' of the TLB entry to be exchanged, resets the bit VNi, and performs memory read/write.
means for resetting/setting the bit M' in response to a write, and a bit V of the TLB entry corresponding to the page immediately before the page indicated by the TLB entry to be replaced;
means for changing Ni and MNi in accordance with memory read/write; means for setting only bit M' of the corresponding entry of the TLB in accordance with the detection results of the first and second detecting means; M′ set target TL
A TLB control method comprising: means for changing bit MNi of the TLB entry corresponding to the page immediately preceding the page indicated by the B entry.