JPS61152024A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61152024A
JPS61152024A JP28166184A JP28166184A JPS61152024A JP S61152024 A JPS61152024 A JP S61152024A JP 28166184 A JP28166184 A JP 28166184A JP 28166184 A JP28166184 A JP 28166184A JP S61152024 A JPS61152024 A JP S61152024A
Authority
JP
Japan
Prior art keywords
film
gate electrode
semiconductor film
semiconductor
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28166184A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP28166184A priority Critical patent/JPS61152024A/en
Publication of JPS61152024A publication Critical patent/JPS61152024A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To make it feasible to substantially laminate a metal or metallic compound on a gate insulating film on an extremely thin semiconductor film coming into close contact therewith by a method wherein, within an insulating gate type field effect semiconductor device, a semiconductor film and a conductor thereon are formed in the same reactor without exposing them to atmosphere. CONSTITUTION:A P-type channel region 10 and a gate electrode 6 made of metallic tungsten are formed on a substrate 1. A silicon oxide film 3 300Angstrom thick is formed and then a semiconductor film 4 30-300Angstrom thick is formed by photochemical reactor on the film 3. Later metallic tungsten is formed by plasma CVD process by vacuumizing and leading tungsten fluoride and hydrogen to a reactor without exposing the tungsten to atmosphere. After forming a conductor 5 for gate electrode, a gate electrode 6 is formed by photolithography. Within said processes, the gate electrode 6 and a lead extending therefrom are not subject to any exfoliation phenomenon even if the pattern width thereof is extremely narrow e.g. 1mum.

Description

【発明の詳細な説明】 r発明の利用分野」 本発明は、絶縁ゲイト型電界効果半導体装置(IGFと
いう)のゲイト電極、キャパシタの電極の作製方法であ
って、電極膜の一部または全部として半導体被膜を光化
学反応を用いたCVD (気相反応)方法により形成す
るとともに、この被膜表面を大気に触れさせることなく
、この半導体膜上に゛ 金属または金属化合物を積層し
て作製する方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a method for manufacturing a gate electrode of an insulated gate field effect semiconductor device (referred to as IGF) and an electrode of a capacitor. This invention relates to a method in which a semiconductor film is formed by a CVD (vapor phase reaction) method using a photochemical reaction, and a metal or a metal compound is laminated on the semiconductor film without exposing the surface of the film to the atmosphere.

r従来の技術」 IGFのゲイト電極の作製方法として、半導体膜とその
上の導体膜をそれぞれを異なる反応方法で異なる反応容
器を用いて作製する方法が知られている。特にシリコン
半導体に関しては、塩酸酸化法により作られたゲイト絶
縁股上に半導体特にシリコン半導体と、この半導体上に
電気伝導度を助長させるための導体、例えばモリブデン
の2層構造を形成している。しかし、このシリコン半導
体を300Å以下の厚さに均一に作製することが、これ
までのプロセス技術である減圧気相法、プラズマ気相法
では不可能であったこともあり、半導体膜は300〜3
000人の厚さを有し、その上に金属膜を1000〜3
000人の厚さに形成していた。かかる厚さにおいては
、半導体と導体の界面における吸着酸素、水の効果は特
に大きな問題にならなかった。
4. Prior Art As a method for manufacturing a gate electrode of an IGF, a method is known in which a semiconductor film and a conductor film thereon are each manufactured using different reaction methods and different reaction vessels. In particular, regarding silicon semiconductors, a two-layer structure is formed on a gate insulating layer made by a hydrochloric acid oxidation method, consisting of a semiconductor, especially a silicon semiconductor, and a conductor, such as molybdenum, on top of this semiconductor to promote electrical conductivity. However, it has been impossible to uniformly fabricate this silicon semiconductor to a thickness of 300 Å or less using conventional process technologies such as low-pressure vapor phase method and plasma vapor phase method. 3
It has a thickness of 1,000 to 3,000 and a metal film on it is 1,000 to 3,000.
It was formed to a thickness of 0,000 people. At such a thickness, the effects of adsorbed oxygen and water at the interface between the semiconductor and the conductor did not pose a particular problem.

しかしこの半導体膜を30〜300人と薄くすると、こ
の吸着物により半導体自体が酸化してしまい、金属がゲ
イト絶縁膜に実質的に直接接するようになり、信頼性低
下を誘発してしまった。
However, when this semiconductor film was made thinner by 30 to 300 people, the semiconductor itself was oxidized by the adsorbed substances, and the metal came into substantially direct contact with the gate insulating film, causing a decrease in reliability.

このため1μ以下のマイクロチャネル旧5−LSIにお
いては、ゲイト電極の基板とのショートが発生し、歩留
りの低下を誘発してしまった。
For this reason, in the microchannel old 5-LSI with a size of 1 μm or less, a short circuit between the gate electrode and the substrate occurred, causing a decrease in yield.

r問題を解決するための手段1 本発明はこれらの問題を解決するため、下地の酸化珪素
膜にまったく損傷を与えることない安定な半導体被膜を
光CVD法で形成せしめ、さらに引き続いてこの表面を
大気に触れさせることなく金属または金属化合物を形成
せしめて2層ゲイト電極を構成させたものである。かか
る工程により、ゲイト電極の半導体と水、酸素等の吸着
物との反応をなくし、きわめて薄い半導体特にシリコン
半導体膜に密着性よく金属または金属化合物をゲイト絶
縁膜上に実質的に積層させることが可能となった。
Means for Solving Problem 1 In order to solve these problems, the present invention uses photo-CVD to form a stable semiconductor film that does not cause any damage to the underlying silicon oxide film, and then subsequently coats this surface. A two-layer gate electrode is constructed by forming a metal or a metal compound without exposing it to the atmosphere. This process eliminates the reaction between the semiconductor of the gate electrode and adsorbed substances such as water and oxygen, and allows the metal or metal compound to be substantially laminated on the gate insulating film with good adhesion to an extremely thin semiconductor film, especially a silicon semiconductor film. It has become possible.

r作用1 この半導体被膜であるシリコン(アモルファスまたは多
結晶)′は、光CVD法で作ることにより、30〜30
0人ときわめて薄く、均一な膜厚を下地絶縁膜に何等の
損傷な(形成させ得る。そして、この上に金属または金
属化合物を形成せしめる際、この半導体の表面の酸化物
の吸着を防いだ。その結果、ゲイト絶縁物とゲイト電極
用高融点金属との間に金属の酸化物の存在と水素化物に
より金属がゲイト絶縁物に実質的に、特に直接接触する
ことによる触媒作用とをも防いだものである。かくして
緯緑物−電極界面近傍(電極内の半導体−金属界面を含
む)にて局部的な反応による、一部絶縁性を有し、また
一部半導体膜を破壊しての金属と酸化珪素との反応を初
めて防ぐことが可能となつた。
r effect 1 This semiconductor film, silicon (amorphous or polycrystalline)', can be made by photo-CVD to
It is possible to form an extremely thin and uniform film with zero damage to the underlying insulating film.And when forming a metal or metal compound on top of this, it prevents the adsorption of oxides on the surface of the semiconductor. As a result, the presence of metal oxides and hydrides between the gate insulator and the high melting point metal for the gate electrode also prevents the catalytic action caused by the metal coming into substantial, especially direct contact with the gate insulator. In this way, a local reaction near the lattice-electrode interface (including the semiconductor-metal interface in the electrode) partially insulates and partially destroys the semiconductor film. For the first time, it has become possible to prevent the reaction between metals and silicon oxide.

本発明では半導体被膜とその上の導体とを同一反応炉に
て半導体被膜上を大気に触れさせることなく形成した。
In the present invention, the semiconductor film and the conductor thereon are formed in the same reaction furnace without exposing the semiconductor film to the atmosphere.

即ち、まず半導体被膜を光CVD法にて形成した後、反
応炉内を真空引きし、次に導体用反応性気体を導入し、
CVD法にて積層して形成するという1つの反応炉方式
である。しかしそれぞれの被膜を互いに連結した2つの
反応炉にてそれぞれ被膜形成する方法、即ちまず半導体
膜を光CVD法で形成し、真空引きの後、ゲイト弁を開
として隣の反応炉に基板を移し、ゲイト弁を閉とした後
、ここで大気に触れさせることなく導体被膜を積層して
形成するというマルチチャンバ方式を採用することも可
能である。
That is, after first forming a semiconductor film by photo-CVD, the inside of the reactor is evacuated, and then a reactive gas for the conductor is introduced.
This is one reactor method in which layers are formed using the CVD method. However, there is a method in which each film is formed in two reactors connected to each other, that is, the semiconductor film is first formed by photo-CVD, and after evacuation, the gate valve is opened and the substrate is transferred to the adjacent reactor. It is also possible to adopt a multi-chamber method in which the conductive film is laminated and formed without exposing it to the atmosphere after the gate valve is closed.

実施例1 第1図に本発明のIGFの縦断面図を示す。Example 1 FIG. 1 shows a longitudinal cross-sectional view of the IGF of the present invention.

即ち、IGPは基板(1)、フィールド絶縁物(2)、
酸化珪素膜(3)よりなるゲイト絶縁物(5)、半導体
被膜(4)及び金属または金属化合物(5)よりなるゲ
イト電極(6)、ソース(7)、ドレイン(8)、チャ
ネルカット(9)、チャネル形成領域(10)よりなっ
ている。
That is, the IGP consists of a substrate (1), a field insulator (2),
Gate insulator (5) made of silicon oxide film (3), gate electrode (6) made of semiconductor film (4) and metal or metal compound (5), source (7), drain (8), channel cut (9) ), and a channel forming region (10).

図面はNチャネルIGFであり、基板(1)上にP(1
0)のチャネル形成領域を有し、チャネル長は1.5μ
、チャネル巾10μとした。ゲイト電極は金属タングス
テンとした。酸化珪素膜(3)は300人の厚さを有せ
しめ、塩酸酸化法による熱酸化膜である。
The drawing shows an N-channel IGF with P(1) on the substrate (1).
0), and the channel length is 1.5μ.
, the channel width was 10μ. The gate electrode was made of tungsten metal. The silicon oxide film (3) has a thickness of 300 nm and is a thermal oxide film formed by a hydrochloric acid oxidation method.

その上の半導体被膜の製造方法について詳細を実施例2
に示すが、光化学反応により30〜300人の厚さ例え
ば100人の厚さに形成した。この後、真空引きをし、
反応炉に弗化タングステン(wph)と水素とを導入し
、電気エネルギを加え、1’h+  3Hg    W
  +  6HFとして金属タングステンをプラズマC
VD法により形成した。
Example 2 details of the method for manufacturing the semiconductor film thereon
As shown in Figure 2, the film was formed to a thickness of 30 to 300 people, for example, 100 people, by photochemical reaction. After this, vacuum the
Introducing tungsten fluoride (wph) and hydrogen into the reactor, adding electrical energy to 1'h+3Hg W
+ 6HF to plasma C tungsten metal
It was formed by the VD method.

このゲイト電極用導体は WF6 +  2SiHa−WSiz +68F+H2
として金属化合物を形成してもよい。
This gate electrode conductor is WF6 + 2SiHa-WSiz +68F+H2
A metal compound may also be formed as a metal compound.

かかるゲイト電極用の導体を形成した後、公知のフォト
リソグラフィ技術を用い、ゲイト電極を形成した。さら
にイオン注入法によりソース(7)。
After forming such a conductor for the gate electrode, a gate electrode was formed using a known photolithography technique. Furthermore, a source (7) is formed by ion implantation.

ドレイン(8)に不純物を注入し、光アニールを行った
。かくしてセルファライン法によりゲイト、ソース、ド
レインを作製したが、これらの工程でゲイト電極及びそ
れより延在したリードに剥離現象はそのパターン巾が1
μときわめて狭くても見られなかった。
Impurities were implanted into the drain (8), and photoannealing was performed. In this way, the gate, source, and drain were fabricated using the self-line method, but during these steps, the peeling phenomenon occurred on the gate electrode and the leads extending from it because the pattern width was 1.
I could not see it even though it was extremely narrow.

かかるIGFにおいては、シリコン半導体膜を形成しな
い即ち酸化珪素に直接耐熱性金属であるMo。
In such an IGF, Mo, which is a heat-resistant metal, does not form a silicon semiconductor film, that is, directly coats silicon oxide.

TitII4.l’1Stz+ Mo5tz、Ti5i
z等を形成した場合に比べて、実質的に電極用導体に下
地絶縁膜と優れた密着性を有せしめることができた。そ
の結果、v thは0.7V + 0.2Vと一定であ
り、150 ℃l  I XIO’ V/c11の電界
でのB−T (バイアス・温度)テスト(3時間)にお
いてドリフト量は0.2v以下しかみられなった。
TitII4. l'1Stz+ Mo5tz, Ti5i
Compared to the case where z or the like is formed, it was possible to substantially provide the electrode conductor with excellent adhesion to the base insulating film. As a result, v th was constant at 0.7 V + 0.2 V, and the amount of drift was 0.0 in the BT (bias/temperature) test (3 hours) in an electric field of 150 °C I XIO' V/c11. I could only see 2v or less.

実施例2 以下第2図に示した図面に基づき、本発明の光CVD法
によるSi膜の製造および、それに引き続き導体を半導
体上に大気に触れさせることなく形成する方法の詳細を
記す。
Example 2 Hereinafter, based on the drawing shown in FIG. 2, details of the production of a Si film by the photo-CVD method of the present invention and the method of subsequently forming a conductor on a semiconductor without exposing it to the atmosphere will be described.

第2図において、被形成面を有するシリコン基板(1)
はホルダ(1゛)に保持され、反応室(12)内のハロ
ゲンヒータ(13) (上面を水冷(31))に近接し
て設けられている。反応室(12)、紫外光源が配設さ
れた光源室(35)及びヒータ(13)が配設された加
熱室(30)は、それぞれの圧力を10torr以下の
概略同一の真空度に保持した。このために反応に支障の
ない気体(水素、アルゴンまたはヘリューム)を(28
)より(36)に供給しZまたは(36“)より排気す
ることにより成就した。また透光性遮蔽板である石英窓
(40)により、光源室(35)と反応室(12)とが
仕切られている。この窓(40)の上側にはノズル(3
4)が設けられ、反応性気体(33)が内側に導かれる
ようにした。このノズルは同時にメツシュ(34°)を
有しプラズマCVD用の電極を構成している。
In FIG. 2, a silicon substrate (1) having a surface to be formed
is held in a holder (1') and is provided in close proximity to a halogen heater (13) (the top surface of which is water-cooled (31)) in the reaction chamber (12). The reaction chamber (12), the light source chamber (35) in which the ultraviolet light source was disposed, and the heating chamber (30) in which the heater (13) was disposed were maintained at approximately the same degree of vacuum of 10 torr or less. . For this purpose, a gas (hydrogen, argon or helium) that does not interfere with the reaction (28
) to (36) and exhaust from Z or (36'').Also, the light source chamber (35) and reaction chamber (12) are separated by the quartz window (40), which is a light-transmitting shielding plate. There is a nozzle (3) on the upper side of this window (40).
4) was provided to guide the reactive gas (33) inside. This nozzle also has a mesh (34°) and constitutes an electrode for plasma CVD.

このノズル(34)は、光CVD法で被膜を形成してし
まった後、導体被膜を形成するプラズマ気相法及び窓(
40)上に形成される不要物の゛プラズマエッチ法によ
る除去を行う際の高周波電源(15) (周波数13.
56MH2)の一方の電極となっている。
This nozzle (34) uses a plasma vapor phase method and a window (
40) High frequency power source (15) (frequency 13.
56MH2).

光源室の排気に際し逆流による反応性気体の光源室まで
の混入防止のためヒータ(29)を配設した。
A heater (29) was provided to prevent reactive gas from entering the light source chamber due to backflow when the light source chamber was evacuated.

これにより反応性気体のうちの分解後固体となる成分を
トラツブし気体のみの導入とさせた。
As a result, components of the reactive gas that become solid after decomposition were removed, and only the gas was introduced.

移動に関し、圧力差が生じないようにしたロード・ロッ
ク方式を用いた。まず、予備室(14)にて基板(1)
及びホルダ(1゛)を挿入・配設し、真空引きをした後
、ゲート弁(16)を開とし、反応室(12)に移した
。またゲート弁(16)を閉として、反応室(12) 
、予備室(14)を互いに仕切った。
Regarding movement, a load-lock system was used to prevent pressure differences from occurring. First, the board (1) is placed in the preliminary room (14).
After inserting and arranging the holder (1') and evacuating, the gate valve (16) was opened and the reactor was transferred to the reaction chamber (12). Also, with the gate valve (16) closed, the reaction chamber (12)
, the preliminary rooms (14) were partitioned off from each other.

ドーピング系(37)は、パルプ(22) 、流量計(
21)よりなり、%IF&は(23)より、水素を(2
4) 、 (26)より供給した。Si、P6または5
izH6を(25)より、またエツチング用ガスのNF
3を(27)より供給した。
The doping system (37) includes pulp (22), flowmeter (
21), and %IF& is from (23), hydrogen is (2
4), (26). Si, P6 or 5
izH6 from (25) and etching gas NF.
3 was supplied from (27).

反応室の圧力制御は、コントロールバルブ(17) 。The pressure in the reaction chamber is controlled by a control valve (17).

コック(20)を経てターボ分子ポンプ(大阪真空製P
G550を使用) (18) 、ロータリーポンプ(1
9)を経、排気させた。
A turbo molecular pump (Osaka Vacuum P
G550) (18), rotary pump (1
9) and then evacuated.

排気系(38)はコック(20)により予備室(14)
を真空引きをする際はそちら側を開とし、反応室(12
)側を閉とする。また反応室を真空引きする際は反応室
を開とし、予備室側を閉とした。
The exhaust system (38) is connected to the preliminary chamber (14) by the cock (20).
When vacuuming the chamber, open that side and open the reaction chamber (12
) side is closed. Furthermore, when evacuating the reaction chamber, the reaction chamber was opened and the preliminary chamber side was closed.

かくして基板を反応室に図示の如く挿着した。The substrate was thus inserted into the reaction chamber as shown.

この反応室の真空度は10−?torr以下とした。こ
の後、(28)より窒素を導入し、さらにSigHhま
たはSigFhを(25)よりa、(26)とともに反
応室に導入して珪素半導体被膜形成を行った。
The degree of vacuum in this reaction chamber is 10-? torr or less. Thereafter, nitrogen was introduced from (28), and SigHh or SigFh was introduced from (25) together with a and (26) into the reaction chamber to form a silicon semiconductor film.

反応用光源は低圧水銀灯(34)とし、水冷(31°)
を設けた。その紫外光源は、低圧水銀灯(185n+m
The light source for the reaction was a low-pressure mercury lamp (34), water-cooled (31°).
has been established. The ultraviolet light source is a low-pressure mercury lamp (185n+m
.

254n−の波長を発光する発光長40cm、照射強度
15mW/c■2.ランプ電力40−)ランプ数16本
である。
Emit light with a wavelength of 254n-, emission length 40cm, irradiation intensity 15mW/c■2. Lamp power: 40-) Number of lamps: 16.

この紫外光は、透光性遮蔽板である石英(40)を経て
反応室(12)の基板(1)の被形成面上を照射する。
This ultraviolet light passes through quartz (40), which is a transparent shielding plate, and irradiates the surface of the substrate (1) in the reaction chamber (12) to be formed.

ヒータ(13)は反応室の上側に位置した「ディポジソ
ション・アップ」方式とし、基板を300℃に加熱した
The heater (13) was a "deposition up" type heater located above the reaction chamber, and heated the substrate to 300°C.

かくしてSi膜を100人の厚さに約5分で形成させる
ことができた。この後(25) 、 (26)を閉とし
、反応室(2)を10− ’ torrまでターボポン
プ(1B) ニて真空引きした。さらに(23)より畦
、を水素(24)とともに流した。加えて圧力Q、 l
 torrにて13.56Ml(z(15)を印加し、
珪素半導体膜上を大気に触れさせることなく導体を形成
した。
In this way, a Si film with a thickness of 100 layers could be formed in about 5 minutes. Thereafter, (25) and (26) were closed, and the reaction chamber (2) was evacuated to 10-' torr using a turbo pump (1B). Further, the ridge (23) was flowed together with hydrogen (24). In addition, the pressure Q, l
13.56 Ml (z(15) was applied at torr,
A conductor was formed on a silicon semiconductor film without exposing it to the atmosphere.

図面の場合の被形成有効面積は30cw X 30ca
*であり、直径5インチの基板(1)5枚がホルダ(1
゛)に配設され得る構成を有せしめた。
In the case of the drawing, the effective area to be formed is 30cw x 30ca
*, and five boards (1) with a diameter of 5 inches are placed in a holder (1).
(a)).

導体膜をWSigとする場合はWFh(23)と5il
t(25)とを流して形成すればよい。
When the conductor film is WSig, WFh (23) and 5il
t(25).

実施例3  Si膜及びモリブデン膜の作製5ilF、
または5izHaを(25)に連結し、8cc/分で供
給した。(26)より水素を30cc/分で供給した。
Example 3 Preparation of Si film and molybdenum film 5ilF,
Alternatively, 5izHa was connected to (25) and fed at 8 cc/min. (26) supplied hydrogen at a rate of 30 cc/min.

すると、これらは紫外光源(32)より184rv+の
光を受けて水銀を用いることなく光分解し、Si被膜を
基板(1)の被形成面に約100人の厚さに形成させる
ことができた。即ち、珪素膜の窓(40)上への形成に
より紫外光が遮蔽されるまでの厚さの30〜300人の
厚さで形成させることができた。
Then, these were photodecomposed by receiving 184 rv+ light from the ultraviolet light source (32) without using mercury, and it was possible to form a Si film to a thickness of approximately 100 nm on the surface of the substrate (1). . That is, by forming the silicon film on the window (40), it was possible to form the silicon film to a thickness of 30 to 300 nm, which is the thickness required to block ultraviolet light.

かかる多結晶またはアモルファス珪素膜上にモリブデン
膜を形成した。即ち、塩化モリブデンを(23)より、
また水素を(24)より供給し、光CVD、光プラズマ
反応の双方を同時に行う光プラズマCVDまたはプラズ
マCVDによりこの上面に金属モリブデン膜を形成した
。かくしてゲイト絶縁膜上に半導体および金属膜をゲイ
ト電極用導体として形成した。
A molybdenum film was formed on the polycrystalline or amorphous silicon film. That is, from (23), molybdenum chloride is
Further, hydrogen was supplied from (24), and a metal molybdenum film was formed on the upper surface by photo-plasma CVD or plasma CVD in which both photo-CVD and photo-plasma reactions were performed simultaneously. In this way, a semiconductor and a metal film were formed on the gate insulating film as a conductor for a gate electrode.

反応後の反応炉内のプラズマエッチはNF3を用いて基
板を取り出した後、(15)より80−の高周波エネル
ギを加えて行った。
Plasma etching in the reactor after the reaction was performed using NF3 to take out the substrate and then applying 80-high frequency energy from (15).

r効果J 本発明は以上の説明より明らかなごとく、ゲイト電極と
して光CVO法を用いた半導体被膜およびそれに引き続
き導体を形成したものである。
r effect J As is clear from the above description, the present invention is a gate electrode formed by forming a semiconductor film using a photo-CVO method, and subsequently forming a conductor thereon.

その結果、高融点金属の密着性に優れ、ゲイト電極に加
えた電圧を有効に半導体(1)のチャネル形成領域(1
0) (第1図)に印加でき、空乏層を設けることがで
きた。
As a result, the high melting point metal has excellent adhesion, and the voltage applied to the gate electrode can be effectively applied to the channel forming region (1) of the semiconductor (1).
0) (Fig. 1), and a depletion layer could be formed.

本発明において、シリコン半導体の作製方法として光C
VD法を用いた。しかし、その際の被膜形成温度を20
0〜350℃と低温ではな(、水素の被膜内への残存を
防ぐため500〜900℃の高温度(圧力0.1〜3 
torr)として行ってもよく、またシリコンではな(
G13H++GezFh+GeFaを用いてゲルマニュ
ーム膜の形成を行ってもよいことはいうまでもない。
In the present invention, optical C
The VD method was used. However, the film formation temperature at that time was 20
At low temperatures of 0 to 350 degrees Celsius (at high temperatures of 500 to 900 degrees Celsius (at pressures of 0.1 to 3 degrees Celsius) to prevent hydrogen from remaining in the film).
torr), or silicon (
It goes without saying that the germanium film may be formed using G13H++GezFh+GeFa.

本発明は、以上の説明より明らかなごとく、大面積の基
板上に被膜を形成するにあたり、窓上の不要反応生成被
膜が形成されて、それにより被膜形成が中断される前に
30〜300人のきわめて薄い膜をゲイト電極の下側の
金属の絶縁物へのプロフキング層として作製したもので
ある。このため、第2図の装置ではこの被膜形成が完了
して基板を取り出して後、反応室内を真空引きして窓上
の不要物をプラズマエツチングより完全に除去し、次の
新たな面の被膜形成を行うことがきわめて重要である。
As is clear from the above description, when forming a film on a large-area substrate, the present invention prevents the formation of an unnecessary reaction-generated film on the window, which requires 30 to 300 people before the film formation is interrupted. This extremely thin film was fabricated as a profking layer on the metal insulator below the gate electrode. For this reason, in the apparatus shown in Figure 2, after this film formation is completed and the substrate is taken out, the reaction chamber is evacuated and unnecessary materials on the window are completely removed by plasma etching, and the next new surface is coated. It is extremely important to carry out the formation.

さらにこの光CVD法による半導体被膜形成に加えて、
前工程としてゲイト絶縁膜の一部として酸化珪素膜上に
重ねて窒化珪素膜または窒化アルミニューム膜を光CV
D法で形成してもよい。
Furthermore, in addition to forming a semiconductor film using this photo-CVD method,
As a pre-process, a silicon nitride film or aluminum nitride film is deposited on the silicon oxide film as part of the gate insulating film by photoCVD.
It may be formed by method D.

なお本発明において、電極材料は真性または不純物が添
加された珪素およびそれに大気に触れさせることな(積
層した半導体、珪素を主成分とする化合物(MO5iz
+WSiz、Ti5it)またはMo、W、 Ti、^
l。
In the present invention, the electrode material is silicon to which intrinsic or impurities have been added, as well as silicon that is not exposed to the atmosphere (laminated semiconductors, silicon-based compounds (MO5iz), etc.).
+WSiz, Ti5it) or Mo, W, Ti, ^
l.

Siの金属を示した。しかしその他の導体も用い得る。Indicates the metal of Si. However, other conductors may also be used.

また17r/cal1等のキャパシタの電極として本発
明方法を用いることは有効である。
Further, it is effective to use the method of the present invention as an electrode of a capacitor such as 17r/cal1.

多層膜に関しては、最初半導体膜を第1の反応炉にて形
成し、さらにその上に導体を連結した隣の反応炉を用い
積層して形成することにより、第1の半導体被膜の表面
を大気に触れさせることな(第2の導電性被膜を積層し
て形成させることはその生産性の向上にさらに優れたも
のである。
Regarding multilayer films, the semiconductor film is first formed in a first reactor, and then the surface of the first semiconductor film is exposed to the atmosphere by stacking layers on top of it using an adjacent reactor connected to a conductor. Forming the second conductive film in a layered manner is even more excellent in improving productivity.

前記した実験例において、光CVD用の光源として低圧
水銀灯ではな(エキシマレーザ(波長100〜400n
m) 、アルゴンレーザ、窒素レーザ等を用いてもよい
ことはいうまでもない。
In the experimental example described above, a low-pressure mercury lamp was not used as the light source for optical CVD (an excimer laser (wavelength: 100 to 400 nm) was used as the light source.
m) It goes without saying that an argon laser, a nitrogen laser, etc. may also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の絶縁ゲイト型電界効果半導体装置を示
す。 第2図は本発明のCVO装置である。
FIG. 1 shows an insulated gate field effect semiconductor device of the present invention. FIG. 2 shows the CVO device of the present invention.

Claims (1)

【特許請求の範囲】 1、絶縁ゲイト型電界効果半導体装置におけるゲイト電
極またはキャパシタ電極の一部または全部の被膜として
絶縁膜または誘電体上に半導体被膜を形成する工程と、
該工程の後、前記被膜を大気に触れさせることなく前記
被膜上に金属膜または金属化合物の被膜を形成する工程
とを有することを特徴とする半導体装置作製方法。 2、特許請求の範囲第1項において、半導体被膜は光気
相反応法により形成するとともに、導体はプラズマ気相
反応、光気相反応またはその双方を同時に行う光プラズ
マ気相反応により形成することを特徴とする半導体装置
作製方法。
[Claims] 1. Forming a semiconductor film on an insulating film or dielectric as a film for part or all of a gate electrode or a capacitor electrode in an insulated gate field effect semiconductor device;
A method for manufacturing a semiconductor device, comprising the step of forming a metal film or a metal compound film on the film without exposing the film to the atmosphere after the step. 2. In claim 1, the semiconductor film is formed by a photo-vapor phase reaction method, and the conductor is formed by a photo-plasma vapor phase reaction that performs a plasma vapor phase reaction, a photo vapor phase reaction, or both simultaneously. A semiconductor device manufacturing method characterized by:
JP28166184A 1984-12-25 1984-12-25 Manufacture of semiconductor device Pending JPS61152024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28166184A JPS61152024A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28166184A JPS61152024A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61152024A true JPS61152024A (en) 1986-07-10

Family

ID=17642212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28166184A Pending JPS61152024A (en) 1984-12-25 1984-12-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61152024A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06224190A (en) * 1992-10-30 1994-08-12 Hyundai Electron Ind Co Ltd Manufacture of tungsten plug

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188913A (en) * 1983-04-11 1984-10-26 Semiconductor Energy Lab Co Ltd Photo cvd device
JPS59198718A (en) * 1983-04-25 1984-11-10 Semiconductor Energy Lab Co Ltd Manufacture of film according to chemical vapor deposition

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188913A (en) * 1983-04-11 1984-10-26 Semiconductor Energy Lab Co Ltd Photo cvd device
JPS59198718A (en) * 1983-04-25 1984-11-10 Semiconductor Energy Lab Co Ltd Manufacture of film according to chemical vapor deposition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06224190A (en) * 1992-10-30 1994-08-12 Hyundai Electron Ind Co Ltd Manufacture of tungsten plug

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