JPS61151515A - Optical gate device - Google Patents

Optical gate device

Info

Publication number
JPS61151515A
JPS61151515A JP27339884A JP27339884A JPS61151515A JP S61151515 A JPS61151515 A JP S61151515A JP 27339884 A JP27339884 A JP 27339884A JP 27339884 A JP27339884 A JP 27339884A JP S61151515 A JPS61151515 A JP S61151515A
Authority
JP
Japan
Prior art keywords
optical gate
optical
gate array
polarized wave
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27339884A
Other languages
Japanese (ja)
Other versions
JPH0133807B2 (en
Inventor
Seiichi Naito
内藤 誠一
Akio Hiraide
平出 章夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP27339884A priority Critical patent/JPS61151515A/en
Publication of JPS61151515A publication Critical patent/JPS61151515A/en
Publication of JPH0133807B2 publication Critical patent/JPH0133807B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the output drift generated in an optical gate array element by dividing an input light to plural optical paths and providing plural optical gate arrays which intercept lights of individual optical paths in stages and switching these optical gate arrays in time division. CONSTITUTION:The light emitted from a light source 32 is separated to a p- polarized wave and an s-polarized wave by a polarizing beam splitter 61, and the p-polarized wave is inputted to an optical gate array 68, and the s-polarized wave is inputted to an optical gate array 67. When the optical gate array 67 is turned on, the electrooptic effect is generated, and the s-polarized wave which passes it has the plane of polarization rotated at 90 deg. and becomes a p-polarized wave and is outputted in the direction of an arrow A, and the p-polarized wave which passes the optical gate array 68 is outputted in the direction of an arrow B. When the optical gate array 68 is turned on, the electrooptic effect is generated, and the p-polarized wave which passes it has the plane of polarization rotated at 90 deg. and becomes an s-polarized wave and is outputted in the direction of the arrow, and the s-polarized wave which passes the optical gate array 67 is outputted in the direction of the arrow B. Thus, optical gate arrays are switched by a cycle T0 to reduce the bad influence due to drift of PLZT.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、光パワーメータや光パワーキャリブレータな
どに用いて有効な、光の段階的な遮断を行なう光ゲート
装置の改善に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement of an optical gate device that is effective for use in optical power meters, optical power calibrators, etc. and that blocks light in stages.

(従来の技術) 光ゲート装置の関連する技術として、第6図の光パワー
キャリブレータの例を説明する。1は暗室、2は基準光
源、3は一定の孔を有するスリット、4は光検出器であ
る。5はスリット3からの基準光源2の光を平行にする
ための第1のレンズ、6は第1のレンズからの光の透過
量を制限するための光遮蔽手段、7は光遮蔽手段6を透
過した光を収束するための第2のレンズである。8は光
遮蔽手段6の遮蔽量をi+11111するための遮蔽制
御手段、9は光遮蔽手段6の遮KmυfwJ信号と、光
検出器4からの出力信号との関係を比較・演算し、CR
Tやプロッタ上に表示する表示手段である。
(Prior Art) As a technology related to an optical gate device, an example of an optical power calibrator shown in FIG. 6 will be described. 1 is a dark room, 2 is a reference light source, 3 is a slit having a certain hole, and 4 is a photodetector. 5 is a first lens for parallelizing the light from the reference light source 2 from the slit 3; 6 is a light shielding means for limiting the amount of light transmitted from the first lens; 7 is a light shielding means 6; This is a second lens for converging the transmitted light. 8 is a shielding control means for increasing the shielding amount of the light shielding means 6 by i+11111; 9 is a CR
This is a display means for displaying on a T or plotter.

第7図は光遮蔽手段6の詳細を説明する図で、PLZT
などの電気光学材料からなる基板20に複数個の電極2
1a、21b、・・・21nを設け、この基板20の両
側に第1の偏光板22および第2の偏光板23を、その
偏光面が互いに直行するように配し、基板20に設けた
それぞれの電極21a、21b、・・・21nに所定の
電界を印加し、その電界によって基板20に入射する光
線24の電界方向に対して水平・垂直偏光成分の光束に
位相差を与え、この先124が第2偏光板23を通過す
るように透過窓を構成し、その電界の印加を遮蔽量制御
手段8により制御するようにしたものである。
FIG. 7 is a diagram illustrating details of the light shielding means 6.
A plurality of electrodes 2 are mounted on a substrate 20 made of an electro-optic material such as
1a, 21b, . A predetermined electric field is applied to the electrodes 21a, 21b, . A transmission window is configured to pass through the second polarizing plate 23, and the application of the electric field is controlled by the shielding amount control means 8.

上記のような構成のパワーキャリブレータにおいて、任
意の数の透過窓を開(または閉)にすれば、その透過窓
の数に比例した光量が光検出器4に照射され、そのとき
の遮蔽量制御手段8の出力信号および光検出器4の電気
信号を表示手段9に入力して演算・比較を行いCRTや
プロッタに表示することにより、光検出器4の校正を行
なうことができる。
In the power calibrator configured as above, when an arbitrary number of transmission windows is opened (or closed), the photodetector 4 is irradiated with an amount of light proportional to the number of transmission windows, and the amount of shielding at that time is controlled. The photodetector 4 can be calibrated by inputting the output signal of the means 8 and the electric signal of the photodetector 4 to the display means 9, performing calculations and comparisons, and displaying the results on a CRT or plotter.

(発明が解決しようとする問題点) しかしながら、光遮蔽手段6に用いられているPLZT
ゲートアレイ素子は、時間とともにPLZTの電気光学
効果が変化するので、スイッチとして使用する場合には
出力のドリフトを誘起して、精度、直線性を悪化させる
という欠点があった。
(Problem to be solved by the invention) However, the PLZT used in the light shielding means 6
Since the electro-optic effect of PLZT changes over time, the gate array element has the disadvantage that when used as a switch, it induces output drift and deteriorates accuracy and linearity.

特に光エネルギが高いときに問題となる。This is especially a problem when the light energy is high.

本発明は上記の問題点を解決するためになされたもので
、光ゲートアレイ素子において生じる出力ドリフトを減
少させた光ゲート装置を実現することを目的としている
The present invention has been made to solve the above problems, and an object of the present invention is to realize an optical gate device in which output drift occurring in an optical gate array element is reduced.

(問題点を解決するための手段) 本発明の光ゲート装置の第1の発明は、入力光を段階的
に遮断する光ゲート装置において、入力光を複数の光路
に分割する手段と、前記各光路の光を段階的に遮断する
複数の光ゲートアレイと、この複数の光ゲートアレイを
時分割で切換える制御回路とを有し、出力光において生
じるドリフトを減少さぼることを特徴とする。
(Means for Solving the Problems) A first aspect of the optical gate device of the present invention is an optical gate device that blocks input light in stages, and includes means for dividing the input light into a plurality of optical paths, and a method for dividing the input light into a plurality of optical paths. It is characterized by having a plurality of optical gate arrays that block light in an optical path in stages, and a control circuit that switches the plurality of optical gate arrays in a time-division manner, thereby reducing drift occurring in output light.

本発明の光ゲート装置の第2の発明は、入力光と、この
複数の光ゲートアレイを時分割で切換えるとともに1周
期の平均値が0となる駆動信号を・各光ゲートアレイに
加える制御回路とを有し、出力光において生じるドリフ
トを減少させることを特徴とする。
The second aspect of the optical gate device of the present invention is a control circuit that switches the input light and the plurality of optical gate arrays in a time division manner, and applies a drive signal whose average value in one cycle is 0 to each optical gate array. It is characterized by reducing drift occurring in output light.

(作用) 本発明の第1の発明に係る構成によれば、駆動信号を各
光ゲートアレイに加える時間が短くなるので、各光ケー
トアレイに生じるドリフト量を減少させることができる
(Function) According to the configuration according to the first aspect of the present invention, since the time for applying a drive signal to each optical gate array is shortened, the amount of drift occurring in each optical gate array can be reduced.

また本発明の第2の発明に係る構成によれば、互いに極
性が逆の駆動信号を印加することにより、ドリフトを相
殺することができる。
Further, according to the configuration according to the second aspect of the present invention, drifts can be canceled out by applying drive signals having mutually opposite polarities.

(実施例) 以下本発明を図面を用いて詳しく説明する。(Example) The present invention will be explained in detail below using the drawings.

第1図は本発明に係る光ゲート装置を光パワーキャリブ
レータに応用した場合の一実施例で、2つのゲートアレ
イを交互に用いるものを示す構成説明図である。32は
基準光源、35はこの基準光源32から出た光を集光さ
せるレンズ、36はこのレンズ35からの光の透過量を
制限するためψ光遮蔽手段で、61および64は偏光ビ
ームスレリッタ、62および63は全反射プリズム、6
1におよび66は光束の幅を限定する同一特性のコリメ
ータ、67および68はそれぞれ偏光ビームスプリッタ
61から出た2つの偏光波が照射されるように設置され
た同一特性のPLZT光ゲートアレイ、37は光検出器
34に光を集光するための集光レンズである。67.6
8のPLZT光ゲートアレイには第7図の電極21a、
21b、・・・21nと同様な電極が設けられている。
FIG. 1 is an explanatory diagram of a configuration in which an optical gate device according to the present invention is applied to an optical power calibrator, and shows an example in which two gate arrays are used alternately. 32 is a reference light source, 35 is a lens for condensing the light emitted from this reference light source 32, 36 is a ψ light shielding means for limiting the amount of light transmitted from this lens 35, and 61 and 64 are polarizing beam filters. , 62 and 63 are total reflection prisms, 6
1 and 66 are collimators with the same characteristics that limit the width of the light beam; 67 and 68 are PLZT optical gate arrays with the same characteristics installed so that the two polarized waves emitted from the polarizing beam splitter 61 are irradiated; 37 is a condensing lens for condensing light onto the photodetector 34. 67.6
The 8 PLZT optical gate array has electrodes 21a shown in FIG.
Electrodes similar to those 21b, . . . 21n are provided.

38は光ゲートアレイ67.68のゲートを駆動する制
御信号Q1.Q2を発生する制御回路である。(l;i
光ビームスプリッタ61.64および全反射プリズム6
2.63は入力光を複数の光路に分割する手段を構成し
ている。
38 is a control signal Q1.38 that drives the gates of the optical gate arrays 67 and 68. This is a control circuit that generates Q2. (l;i
Optical beam splitter 61, 64 and total reflection prism 6
2.63 constitutes means for dividing input light into a plurality of optical paths.

この様な構成の装置の動作を次に述べる。今2つの光ゲ
ートアレイ67.68が1単位の光量を交互にスイッチ
ングしている場合を説明する。光源32から出た光は偏
光ビームスプリッタ61によりP波とS波とに分離され
、P波は光ゲートアレイ68にS波は光ゲートアレイ6
7にそれぞれ入る。
The operation of the apparatus having such a configuration will be described next. Now, a case will be explained in which the two optical gate arrays 67 and 68 alternately switch the amount of light of one unit. The light emitted from the light source 32 is separated into P waves and S waves by a polarizing beam splitter 61, and the P waves are sent to the optical gate array 68 and the S waves are sent to the optical gate array 6.
7 each.

光ゲートアレイ67がオンになると電気光学効果が生じ
、ここを通過するS波は偏光面が90’回転してP波と
なり、全反射プリズム63.偏光・鈴−ムスプリッタ6
4を経て爪方向に出力される。
When the optical gate array 67 is turned on, an electro-optic effect occurs, and the polarization plane of the S wave passing through it is rotated by 90' to become a P wave, and the total reflection prism 63. Polarized light/bell splitter 6
4 and is output in the direction of the claw.

+力先ゲートアレイ68はオフとなるので電気光・、門
効果は生じず、ここを通過するP波は偏光ビームスプリ
ッタ64を経てB方向に出力される。
Since the front gate array 68 is turned off, no electro-optic gate effect occurs, and the P wave passing through it is output in the B direction via the polarizing beam splitter 64.

逆に、光ゲートアレイ68ががオンになると電気光学効
果が生じ、ここを通過するP波は偏光面が90″回転し
てS波となり、偏光ビームスプリッタ64を経て爪方向
に出力される。−力先ゲー17−アレイ67はオフなの
で電気光学効果は生じず、ここを通過するS波は全反射
プリズム63.偏光ビームスプリッタ64を経てB方向
に出力される。
Conversely, when the optical gate array 68 is turned on, an electro-optic effect occurs, and the polarization plane of the P wave passing through it is rotated by 90'' to become an S wave, which is outputted in the direction of the nail via the polarizing beam splitter 64. - Power tip gear 17 - Since the array 67 is off, no electro-optic effect occurs, and the S wave passing through it is output in the B direction via a total reflection prism 63 and a polarizing beam splitter 64.

これをTo周期で繰返すと、異なる光ゲートアレイを通
過した1単位の光が交互に出力される結果、B方向への
出力光は第2図のタイムチャートのようになる。光ゲー
トアレイに複数単位の光量を設定した場合も同様に複数
単位の光を交互に出力するので、光ゲート数に対するB
方向への出力光mは第3図の特性曲線図のように変化す
る。
When this is repeated at the To period, one unit of light that has passed through different optical gate arrays is output alternately, and as a result, the output light in the B direction becomes as shown in the time chart of FIG. 2. Even when multiple units of light intensity are set for the optical gate array, multiple units of light are output alternately in the same way, so the B for the number of optical gates is
The output light m in the direction changes as shown in the characteristic curve diagram in FIG.

このようにTo周期で光ゲートアレイをスイッチングす
ることにより、PLZTのドリフトによる悪影響を減少
させることができる。
By switching the optical gate array at the To period in this manner, the adverse effects of PLZT drift can be reduced.

なお上記の実施例では制御信号Q+、Q2として同一極
性のものを用いたが、第4図のタイムチャートが示すよ
うに、1周期の平均値が0となるように極性の変化する
駆動信号を制御回路から各兎ゲートアレイに加えれば、
極性の異なる印加電圧によってPLZTに生じる互いに
逆方向のトリ゛・テトが相殺され、さらにドリフトを減
少させるこ立由できる。
In the above embodiment, control signals Q+ and Q2 of the same polarity were used, but as shown in the time chart of FIG. If added to each rabbit gate array from the control circuit,
By applying voltages with different polarities, the tri-tets occurring in the PLZT in opposite directions are canceled out, and drift can be further reduced.

また上記の各実施例において、爪方向の光出力も利用す
れば同時に2台の光検出器の校正が可能となる。
Furthermore, in each of the above embodiments, if the optical output in the claw direction is also used, it becomes possible to calibrate two photodetectors at the same time.

また上記の各実施例において、第5図に示すように、光
出力A、Bを全反射プリズム71を用いて平行光とした
侵レンズ72で光検出器73に集光することにより、2
倍の出力光量を得ることができる。
In each of the above embodiments, as shown in FIG.
It is possible to obtain twice the amount of output light.

また上記の各実施例において、偏光子と検光子の間に複
数のPLZTとコリメータをく例えば第1図の紙面に!
直な方向に)配置し、これを順次切換えて使用すれば、
1つのPLZT当りの利用時間が短縮してざらにドリフ
トを減少させることができる。
Furthermore, in each of the above embodiments, a plurality of PLZTs and collimators are provided between the polarizer and the analyzer, for example, as shown in the paper of FIG.
If you place it in the straight direction) and use it by switching sequentially,
The usage time per PLZT can be shortened and drift can be roughly reduced.

(発明の効果) 以上述べたように本発明によれば、光ゲートアレイ素子
において生じる出力ドリフトを減少させた光ゲート装置
を実現することができ、これを利用した光パワーキャリ
ブレータなどにおいて、精度、直線性を向上させること
ができる。
(Effects of the Invention) As described above, according to the present invention, it is possible to realize an optical gate device that reduces the output drift that occurs in an optical gate array element, and to improve accuracy and Linearity can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

#I!!f第1図は本発明に係わる光ゲート装置の一実
施11を示すための光パワーキャリブレータの構成説塙
f図、第2図は第1図装置のl!llIヤを説明するた
めのタイムチャート、第3図は第1図装置の動作を説明
するための特性曲線図、第4図は第1図の装置の変形例
の動作を説明するためのタイムチャート、第5図は第1
図装置の他の変形例を説明する要部構成説明図、第6図
は関連する光パワーキャリブレータの例、第7図はこれ
に使用されている光遮蔽手段である。 38・・・制御回路、61.62,63.64・・・入
力光を複数の光路に分割する手段、67.68・・・光
ゲートアレイ、Ql、Q2・・・駆動信号。
#I! ! Fig. 1 is a diagram showing the construction of an optical power calibrator to show one embodiment 11 of the optical gate device according to the present invention, and Fig. 2 is a diagram showing the construction of an optical power calibrator to show an embodiment 11 of the optical gate device according to the present invention. 3 is a characteristic curve diagram for explaining the operation of the device shown in FIG. 1, and FIG. 4 is a time chart for explaining the operation of a modified example of the device shown in FIG. 1. , Figure 5 is the first
FIG. 6 is an explanatory diagram of the main part configuration for explaining another modification of the apparatus, FIG. 6 is an example of a related optical power calibrator, and FIG. 7 is a light shielding means used therein. 38... Control circuit, 61.62, 63.64... Means for dividing input light into a plurality of optical paths, 67.68... Optical gate array, Ql, Q2... Drive signal.

Claims (4)

【特許請求の範囲】[Claims] (1)入力光を段階的に遮断する光ゲート装置において
、入力光を複数の光路に分割する手段と、前記各光路の
光を段階的に遮断する複数の光ゲートアレイと、この複
数の光ゲートアレイを時分割で切換える制御回路とを有
し、出力光において生じるドリフトを減少させることを
特徴とする光ゲート装置。
(1) An optical gate device that blocks input light in stages, including means for dividing input light into a plurality of optical paths, a plurality of optical gate arrays that block light in each optical path in stages, and An optical gate device comprising a control circuit that switches a gate array in a time-division manner and reduces drift occurring in output light.
(2)入力光を段階的に遮断する光ゲート装置において
、入力光を複数の光路に分割する手段と、前記複数の光
路の光を段階的に遮断する複数の光ゲートアレイと、こ
の複数の光ゲートアレイを時分割で切換えるとともに1
周期の平均値が0となる駆動信号を各光ゲートアレイに
加える制御回路とを有し、出力光において生じるドリフ
トを減少させることを特徴とする光ゲート装置。
(2) An optical gate device that blocks input light in stages, comprising: means for dividing input light into a plurality of optical paths; a plurality of optical gate arrays that block light in the plurality of optical paths in stages; Switching the optical gate array in time division and 1
1. An optical gate device comprising: a control circuit that applies a drive signal whose period has an average value of 0 to each optical gate array, thereby reducing drift occurring in output light.
(3)光ゲートアレイの電気光学素子としてPLZTを
用いた特許請求の範囲第1項記載の光ゲート装置。
(3) The optical gate device according to claim 1, which uses PLZT as the electro-optical element of the optical gate array.
(4)光ゲートアレイの電気光学素子としてPLZTを
用いた特許請求の範囲第2項記載の光ゲート装置。
(4) The optical gate device according to claim 2, which uses PLZT as the electro-optical element of the optical gate array.
JP27339884A 1984-12-26 1984-12-26 Optical gate device Granted JPS61151515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27339884A JPS61151515A (en) 1984-12-26 1984-12-26 Optical gate device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27339884A JPS61151515A (en) 1984-12-26 1984-12-26 Optical gate device

Publications (2)

Publication Number Publication Date
JPS61151515A true JPS61151515A (en) 1986-07-10
JPH0133807B2 JPH0133807B2 (en) 1989-07-14

Family

ID=17527338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27339884A Granted JPS61151515A (en) 1984-12-26 1984-12-26 Optical gate device

Country Status (1)

Country Link
JP (1) JPS61151515A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2351356A (en) * 1999-05-24 2000-12-27 Marconi Applied Techn Ltd Electro-optic devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4866545U (en) * 1971-11-25 1973-08-23
JPS5470094A (en) * 1977-11-15 1979-06-05 Shimadzu Corp Fluorescent polarization dissolution apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4866545U (en) * 1971-11-25 1973-08-23
JPS5470094A (en) * 1977-11-15 1979-06-05 Shimadzu Corp Fluorescent polarization dissolution apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2351356A (en) * 1999-05-24 2000-12-27 Marconi Applied Techn Ltd Electro-optic devices

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