JPS61150566A - Picture scanning clock generating device in optical scanning device - Google Patents

Abstract

PURPOSE:To make dispersion of starting points of scanning small easily and surely by generating plural kinds of clocks having phases deviated to each other from a reference clock and correcting clocks of frequency N times that of the reference clock, selecting one of them and using it as a picture scanning clock. CONSTITUTION:A reference clock oscillator 10 generates a reference clock Co of the same frequency as a frequency f of a picture scanning clock. A correcting clock oscillator 12 generates correcting clocks SCK1, SCK2 of frequency N times (f) (N=n/2). Shift registers 14, 16 generate plural kinds of clocks C1-Cn of frequency f and having phases deviated to each other. A latch circuit 18 latches input clocks C1-Cn by a synchronization detection signal from a photo sensor, and outputs signals corresponding to each of latched clock. A clock selector circuit 20 operates input signals from the latch circuit and selects one of plural kinds of clocks by a specific relation with the result of operation, and outputs it as a picture scanning clock. Thus, dispersion of starting points of scanning becomes 1/n.

Description

TECHNICAL FIELD The present invention relates to an image scanning clock generation device for an optical scanning device, and more particularly to an image scanning clock generation device for an optical scanning device that uses a rotary deflector as a light deflecting means.

(Prior Art) An optical scanning device periodically deflects a light beam to create a scanning beam, and scans a predetermined strained surface with the scanning beam to read information on the scanned surface or to scan the surface. It is known as a device that does not write information on the scanning surface.

Among such optical scanning devices, there is one that uses a rotating deflector as a means for periodically deflecting a light beam.

A rotary deflector is a device that deflects a light beam by rotating, for example, a rotating polygon mirror or a hologram disk on which a linear diffraction grating is formed by a hologram. When a light beam is deflected by a device, the repetition of the polarization of the light beam may not be exactly the same due to manufacturing errors in the rotating polygon mirror or hologram disk, or mechanical errors in their mechanical rotation. .

On the other hand, when scanning a surface to be scanned by a scanning beam, it is necessary to properly align the starting points of the scanning area, that is, the starting points of scanning by the scanning beam. If the starting points of the scanning areas are not aligned, image distortion due to jitter will occur in the written image, or image distortion due to jitter will also occur in the reproduced image of the read information.

One method of aligning the starting points of scanning by scanning beams is to deploy an optical sensor outside the scanning area, detect the scanning beam heading toward the optical scanning area for each deflection, and generate a synchronization detection signal. There is a method of counting a predetermined number of image scanning clocks based on , and performing optical scanning after the counting is completed. That is, as soon as the synchronization detection signal is generated, counting of image scanning clocks is started, for example, the number of clocks corresponding to 12 m clocks is counted, and scanning is started at the m+1th clock.

In this method, since the image scanning clock is generated continuously, if the generation of the synchronization detection signal varies due to an error in the rotating deflector, the synchronization detection signal will vary with respect to the image scanning clock. If the clock count is performed when the image scanning clock changes from the N low state to the high state, it will occur immediately before the image scanning clock changes from the 10 state to the high state in the state where the synchronization detection signal is generated. In some cases, it is immediately counted for one clock, but when it occurs immediately after the image scanning clock changes from the low state to the 7-a state, the synchronization detection signal is counted immediately after the image scanning clock changes from the low state to the low state.
Since the change to the high state is counted as the first clock, the starting point of the image scan will vary by at most one clock of the image scan clock.

The image scanning clock is a reference clock for optical scanning, and the width of one clock is one pixel for reading or writing in optical scanning, so in the above method, the starting point of optical scanning is one pixel. As a limit, there will be variations, and corresponding jitter will occur in the written image and the read and reproduced image. Image distortion due to jitter becomes quite noticeable when the number of pixels exceeds the limit, and the visual beauty of the image is significantly impaired.

Conventionally, methods disclosed in Japanese Patent Laid-Open No. 51-89346 and Japanese Patent Laid-Open No. 56-126378 are known as methods for reducing variations in scanning starting points due to scanning beams.

However, in the former method, for example, in order to reduce the variation in the scanning starting point to 1 or less, a reference clock with a frequency that is 1 times that of the image scanning clock is required. Since it is proportional, there is a problem that the effect itself is limited by the achievable value of the frequency of the reference clock.

In addition, when the latter method is actually implemented, it is affected by the operational tolerance of the delay element, and in order to obtain the desired effect, it is necessary to suppress the variation in the error. There is a problem that the cost becomes high as a result.

(Purpose) The present invention has been made in view of the above-mentioned circumstances, and its purpose is to achieve a method that can be realized at low cost, and also easily and reliably reduce the variation in scanning starting points. An object of the present invention is to provide a novel image scanning chroma generation device.

(Structure) Hereinafter, the present invention will be described in the case where the variation in the scanning starting point is set to 1.

The image scanning clock generation device of the present invention includes a reference clock oscillator, a correction clock oscillator, a shift register, a latch circuit, and a clock selection circuit.

The reference clock oscillator generates a reference clock having the same frequency as the image scanning clock frequency f.

The correction clock oscillator has a frequency N times the frequency of the reference clock (
Here, a corrected chronograph with a frequency of N = n is generated. Note that n is a natural number of 2 or more.

The soft register receives the reference clock and the correction clock, and generates multiple types of clocks having a frequency of f and whose phases are shifted from each other.

The latch circuit receives multiple types of clocks generated by the soft register, latches the input clocks according to the synchronization detection signal from the optical sensor, and outputs a signal corresponding to each of the latched clocks.

The clock selection circuit receives both the output of the latch circuit and multiple types of clocks from the soft register,
The input signal from the latch circuit is arithmetic processed, one of the plurality of types of clocks is selected in a predetermined association with the arithmetic result, and output as an image scanning clock.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, please refer to FIGS. 1 to 3.

In FIG. 1, a portion indicated by the reference numeral 22 and surrounded by a chain line is a device portion that generates a plurality of types of clocks.

Now, in FIG. 1, a reference clock Co having a frequency f (equal to the frequency of the image scanning clock) is generated from a reference clock oscillator. Straddle correction clock oscillator 1
2, the frequency f of the reference clock Co is N times (N =
21 n is a natural number of 2 or more) two correction clocks 5C
K1 and 5CK2 are generated.

These are the reference clock CO1 and the correction clock SCK.

5CK2 is shown in FIG. Correction clock 5CK
I.

8CK2 have the same frequency in the example of this description, and their phases are 180 degrees out of phase with each other.

The reference clock CO is the soft register 14. 16. On the other hand, the correction clock 5CKl, 5CK
2 are input into shift registers 14 and 16, respectively.

As shown in FIG. 2, the soft register 14 outputs a correction clock 5CK1 based on the input reference pulse CO.
Therefore, the clock CI, C3+c, .

Cn, and the shift register 16 generates clocks C2+C4, .

Generate Cn. Note that n is treated as an even number here. When the clock is an odd number, the clock generated from the shift register 14 is C1+C3+...,cn
Yes, the clocks generated from the shift register 16 are C2+ C4+ . . . lc, -1.

Thus, n types of Cronk values, C2, . . . , Cn are obtained from the soft registers 14.16. These n types of clocks are shown in FIG. These n types of clocks CI to Cn have a clock period TOs and a pulse width tw,
The phases are shifted from each other by Δto. This phase shift amount Δto is equal to the pulse width of the correction clocks 5CK1 and 5CK2.

These clocks c1-cn are input to the latch circuit 18 and also to the clock selection circuit 2o.

The latch circuit 18 receives input tarots c1 to Cn.
is latched by the synchronization detection signal from the optical sensor, and the value of each clock in the latched state and its inverted value are
C1+ Ql to Qn, output as Qn and applied to the clock selection circuit 2o.

Here, N Qz + Qz is the state of the latched clock ci (i = 1-n) and its inverted value, and is latched. Qi: 11Q? When Tsuku Ci is in the high state? :=0, Qi=o when in low state.

Qj=1.

The clock selection circuit 20 selects the input Qr, Qt
=Qn.

Predetermined arithmetic processing is performed based on Qn. This arithmetic processing is to find out the relative relationship between the synchronization detection signal and the clock signal C7L, and for example, the input Q1+
~) From Qn, Qi-Qi+t (z=1~n.

When i=n, z+1=t) is calculated.

In this way, the synchronization detection signal and the clock C1~.

Once the relative relationship with C7 is known, the clock selection circuit 2
0 selects a clock having a predetermined fixed relative relationship with respect to the synchronization detection signal, and outputs this as an image scanning clock. In this way, this device generates a proper image scanning clock based on the synchronization detection signal.

As one specific case, the case where n=6 will be described below with reference to FIG.

The six types of clocks C1 to C6 shown in FIG. 4 have the same period as the image scanning clock, and the phases of each clock are sequentially shifted by 100 periods.

If these clocks are clocked by the latch circuit with the synchronization detection signal as shown in FIG. 4, the states of the clocks Cb C2, C3+C4+C5+C6 at this time are LOW, LOW, LOW, and HIGH, respectively.

It's in a high, high state. Therefore, Q+～+Q
The capacity of n and the value of Qz-Qj+1 are as shown in the following table.

Table As is clear from this table, Qz-Qz+x is 1 only in the case of C6.Ql, and is O in other cases. This means that the synchronization detection signal is the clock C6 and C1.
In other words, this occurs after the clock C6 goes high but before the clock C1 goes high, which exactly matches the case in FIG.

In this way, once the relationship between the synchronization detection signal and the clocks Ci to C6 is determined, a clock that has a certain relative relationship with the synchronization detection signal is always selected and used as the image scanning clock. The above-mentioned relative relationship can be arbitrarily selected, and therefore any clock can be selected, but in the example shown in Figure 4, the clock that became low immediately before the synchronization detection signal was generated is selected. The above relative relationships have been selected so that The synchronization detection signal is clock C6 as shown in Fig. 4.
and C1, the clock C3 satisfies this relative relationship, and this clock C3 is selected as the image scanning clock. Note that the image scanning clock is in a completely undefined state before the 1 synchronization detection signal is generated, as shown in FIG. Note that after the image scanning clock is selected by the synchronization detection signal, when the image scanning clock is stopped generating after scanning that line and outputting the predetermined number of clocks, the image scanning clock must be in a constant state immediately before the image scanning clock is selected. be.

FIG. 5 is a block diagram of a circuit for selecting a clock which is in the low state immediately before the synchronization detection signal is generated, in the example explained with reference to FIG. 4. It is composed of six AND circuits 4-1 to 4-6 and an OR circuit 4-7.

By selecting the image scanning clock in this way, the variation in the scanning starting point can be suppressed to less than a micropixel, but the frequency of the correction clock required for this is relative to the frequency f of the image scanning clock. 3f or 7
It's double.

By the way, when n clocks are obtained from the shift register, the frequency of the correction clock is 7 times the frequency of the image scanning clock.
Therefore, in order to obtain N clocks, the frequency of the corrected clock SCK or 5CK2 is divided into 1/i using an N/2 frequency divider as shown in Figure 6. , the reference clock Co can be obtained as is. In other words, if the correction clock oscillator and si. A reference clock oscillator can be configured with the frequency divider (N is an even number in this case). For the N clocks C1 to CN obtained at this time, the ratio of the phase shift amount of the even and odd numbers is the corrected clock SCK, , 5CK
This is the ratio of the pulse width of 2. The variation in the scanning starting point is less than or equal to the pulse width of the clock with a wider pulse width among the correction clocks SCK, 5CK2, and 5CK2.

In order to equalize the pulse widths of the correction clocks SCK, , 5CK2, the clock 5CK (=
If the correction reference clock with a frequency twice that of 5CKI = 5CK2) is divided into 1/2 frequency using a divider by 2, we get
A corrected clock SCK can be obtained. In this case, as shown in FIG. 8, the reference clock co and the correction clock are applied to a single /ft register 24 to obtain clocks CI+c, . . . '+Cn. I can do it.

(Effects) As described above, according to the present invention, the novel
An image scanning clock generation device can be provided.

In this device, the frequency of the correction clock for correction is the same as the image scanning frequency. Even though it is twice as large, the variation in the scanning starting point can be suppressed to one pixel or less.

Also, since multiple types of clocks and clocks are generated by the /ft register, the phase frg of these clocks is high,
It is more accurate than the delay line configuration and can be implemented at a lower cost.

However, since the entire device can be configured digitally, it is possible to use a digital gate array, and by doing so, the electrical system can be made cheaper.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining the present invention, FIGS. 4 and 5 are diagrams for explaining one embodiment of the present invention, and FIG. 6 is a reference clock in the present invention. FIG. 7 is a diagram for explaining an example of an oscillator, FIG. 7 is a diagram for explaining an example of a corrected clock oscillator in the present invention, and FIG. 8 is a block diagram showing another embodiment of the present invention. Co...Reference clock, 5CKI, 5CK2.
SCK, -correction clock, CI, C2,..., Cn
...Clocks of the same frequency with mutually shifted phases, Qt,
Qt, . . . + Qn... Signals according to clock Ci, . . . , cn. (J U (J
Uki z map c, -1 old-1211-cho 11th 5 diagram mercenary G diagram 7th Genkan δ diagram

Claims (1)

[Claims] In an optical scanning device that optically scans a predetermined surface to be scanned by periodically deflecting a light beam using a rotating deflector, an optical scanning device that is disposed outside the optical scanning area and moves toward the optical scanning area A device that generates an image scanning clock based on a synchronization detection signal from an optical sensor that detects a beam, which comprises: a reference clock oscillator that generates a reference clock with the same frequency f as the image scanning clock; a correction clock oscillator that generates a correction clock with a frequency of (N is a natural number of 2 or more); a shift register that receives the reference clock and the correction clock and generates multiple types of clocks whose phases are shifted from each other at a frequency f; A latch circuit that receives multiple types of clocks from the shift register, latches the input clocks based on the synchronization detection signal from the optical sensor, and outputs a signal corresponding to each latched clock; and an output of the latch circuit. and a plurality of types of clocks from the shift register, which processes the input signal from the latch circuit, selects one of the plurality of clocks, and outputs it as an image scanning clock. An image scanning clock generation device in an optical scanning device, comprising: