JPS61150374A - Semiconductor device - Google Patents

Abstract

PURPOSE:To keep the impurity concentration of a channel stopper high, and to prevent the protruding of glass by annularly forming mesa grooves on the inside and outside of a channel stopper layer doubly and filling the mesa grooves with glass in a planar type SCR. CONSTITUTION:In a SCR having planar type PNPN four layer structure, two annular grooves 5a, 5'a are shaped while holding an N<+> type channel stopper 9, and filled with glass 5, 5'. The grooves 5a, 5'a extend along a main surface, are formed on P-N junction surfaces among a P layer 1, an N<-> layer 2 and a P layer 3 and near the junctions surfaces while using an oxide film 10 as a mask, and are approximately 15mum deep. The grooves are filled with glass, and coated with CVDSiO2 11. According to the constitution, glass is not protruded, th instability of photoetching work is eliminated, glass is not cracked by shocks, the channel stopper is kept at initial high impurity-concentration, and a required glass film can be formed, thus remarkably improving the stability of a device at high voltage at a high temperature.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a thyristor (SCR) having a planar structure.
It relates to semiconductor devices such as triacs and triacs, and is particularly used in the arrangement structure of a channel stopper layer and a passivation film.

[Technical Background of the Invention] SCRs, triacs (three-pole bidirectional thyristors), and the like are used as power control elements for various electrical devices.
FIG. 3 is a sectional view of a conventional planar type SCR.
The SCR is a semiconductor device having a pnpn 4H structure including a 091479 layer 1, an n-type base layer 2, a p-type base B3, and an n-type emitter layer 4.

6 is a first main electrode (anode), 7 is a second main electrode (cathode), and 8 is a control electrode (gate).

In a forward blocking state in which no current flows even when a forward voltage is applied, most of the forward voltage is applied to the junction between the n-type base layers and reverse biases this junction.

The depletion diagram caused by this reverse bias voltage spreads into the n-type base layer, which has a relatively low impurity density, and forms an electric field. More electric lines of force gather near the surface than inside the n-type base layer, and the electric field strength becomes stronger.

In order to improve the forward blocking voltage, a glass layer 5 is formed on this portion, that is, on the substrate surface including the n-type base layer and the two pn junctions in contact with it, in order to reduce the electric field strength. However, the charge in the glass layer is unstable during glass formation and is prone to electric field concentration and channel formation. It is mainly influenced by the temperature and atmosphere during glass formation.

Channel formation is particularly likely to occur at high temperatures <SC
The characteristics of R become unstable. In order to block channel current on the surface of the n-type base layer, an n-type channel stopper layer 9 having a high impurity concentration almost the same as that of the n-type emitter layer is usually provided on the main surface side of the n-type base layer. S shown in Figure 4
The CR is the same as the SCR shown in FIG. 3, except that a groove is formed in advance on the substrate surface on which the glass layer 5 is to be adhered, and a glass layer is embedded therein. The difference is that the depth of the channel stopper layer is shallow because it is a groove filled in the glass layer.

[Problems with the background art] In the structure shown in FIG. 3 of the prior art, the glass layer 5
is formed so as to bulge on the lli main surface.
Subsequent photoetching processes such as electrode formation (hereinafter referred to as PEP)
When forming a pattern (abbreviated as I), the distance between the mask and the substrate surface becomes large, and the accuracy and resolution of the pattern deteriorate due to light diffraction, making it impossible to obtain a desired pattern shape. Furthermore, since the glass layer 5 is raised, impact is often applied to the glass during the divine process, making the glass more likely to break.

In the structure of FIG. 4, the channel stopper layer is also etched at the same time. Since the impurity concentration decreases exponentially from the substrate surface toward the inside, etching removes the portions with high impurity concentration, reducing the concentration at the surface of the channel stopper layer.

In particular, since the impurity concentration in the single layer of the Dennel stopper is high, the etching rate is higher than in other parts and the concentration tends to decrease. It also becomes difficult to control the amount of etching to keep this concentration decrease to a constant value. If the temperature decreases by 1 degree, the effect as a channel stopper will be weakened, resulting in unstable electrical properties, especially properties at high temperatures.

[Object of the Invention] An object of the present invention is to solve the above-mentioned problems, maintain the impurity density of the channel stopper layer at its original high concentration, and prevent cracks in the protective insulating layer formed of a glass material or the like. It is an object of the present invention to provide a semiconductor device having a structure free from instability in the PEP process due to swelling.

[Summary of the Invention] The present invention provides a semiconductor device having a channel stopper layer such as a planar structure SCR, in which an n-type base layer and a p-type emitter are formed along a first main surface adjacent to one side of the channel stopper layer. an annular groove extending in the vicinity of the n-type channel stopper layer, including the bonding surface with the n-type base layer; This semiconductor device is characterized by forming a double mesa groove with an annular groove extending nearby, and filling each groove with a protective insulating material such as glass.
As the protective insulating material, other than glass, any electrically and thermally stable material may be used. In the case of glass, the thickness of the protective insulating layer needs to be greater than a certain value in consideration of process margins. The depth of the mesa groove to be formed is approximately this value.

The structure of the present invention allows the channel stopper layer to be removed from the original position.
Even if an electrically stable amount of glass or the like is filled at a certain temperature, there will be almost no swelling from the substrate surface.

Furthermore, the structure of the present invention can be easily realized by simply changing the mask pattern so that the channel stopper layer remains when forming the annular groove.

[Embodiments of the Invention] An SCR having a planar pnpn four-layer structure and a channel stopper will be described below as an embodiment of the present invention. Note that the same reference numerals represent the same parts in the subsequent drawings. FIG. 1(a) is a sectional view of the SCR of the present invention.

FIG. 1(1)) is a detailed enlarged sectional view of the main part of the invention shown in FIG. 1(a). Two annular grooves 5a sandwich the n-type channel stopper layer 9.

51a are carved and each is filled with glass (protective insulating material) to form a glass layer 5.5'.

The annular ifM5a and 5'a are adjacent to the outer and inner surfaces of the channel stopper layer 9, respectively, and extend along the first main surface to cover the vicinity including the respective pn junction surfaces. The depths of the annular grooves 5a and 5'a are determined considering electrical and process margins.

It is necessary to form a glass layer with a certain thickness. For example 1
It is assumed to be several micrometers. The annular groove is formed using the oxide film 10 as a mask, and after being filled with glass, a CVD film 11 is deposited.

FIG. 2 is a sectional view of a planar triac according to another embodiment of the present invention. The first main electrode 6, the second
The main electrode 7 and the control electrode 8 are formed in contact with two layers, an n-type semiconductor layer and an n-type semiconductor layer, respectively. A TRIAC is a bidirectional thyristor configured with two thyristors arranged in antiparallel, and the present invention can be applied thereto.

[Effects of the Invention] According to the structure of the present invention, it is possible to eliminate the swelling of the glass layer (protective insulating film), improve the instability of PEP work, and obtain good pattern accuracy and resolution. There were no more cracks. It is possible to maintain the impurity density of the channel stopper layer at the original high concentration and form a glass protective film with sufficient thickness necessary for electrical stability, which significantly improves the stability of the device when high temperature and high voltage are applied. did. As described above, according to the present invention, a device of good quality and easy to manufacture can be provided.

[Brief explanation of the drawing]

FIG. 1(a) is a sectional view of an SCR according to an embodiment of the present invention, FIG. 1(b) is a partially enlarged sectional view of FIG. 1(a), and FIG. 2 is another embodiment of the present invention. Triac cross section, 3rd
4 and 4 are cross-sectional views of conventional SCRs, respectively. 1... N-type emitter layer, 2... N-type base layer, 3
...p-type base layer, 4...n-type emitter layer, 5
゜5'...Protective insulating layer (glass layer), 5a, 5
' a... Annular groove, 9... N-type channel stopper layer.

Claims (1)

[Claims] 1. An n-type base layer formed on the first main surface side of the n-type semiconductor substrate, a p-type emitter layer selectively formed adjacent to the outer surface of the n-type base layer, and a p-type emitter layer selectively formed in the n-type base layer. a p-type base layer selectively formed in the p-type base layer, an n-type emitter layer selectively formed in the p-type base layer, and a first main surface side between the p-type emitter layer and the p-type base layer. In a semiconductor device having a planar structure including a selectively formed n-type channel stopper layer, one of the n-type channel stopper layers
an annular groove adjacent to one side surface and extending along the first main surface including the junction surface between the n-type base layer and the p-type emitter layer and the vicinity thereof;
An annular groove is formed adjacent to the other side surface of the n-type channel stopper layer and extends along the first principal surface including the junction surface between the n-type base layer and the p-type base layer, and a protective layer is formed in each groove. A semiconductor device characterized by being filled with an insulating material.