JPS61150191A - Optical memory cell's driving system - Google Patents

Abstract

PURPOSE:To reduce the small consumption of electric power of an optical memory cell by lowering the effective resistance value of a circuit inserted between the optical memory cell and a driving power source during the access of the memory. CONSTITUTION:During the input of pulse wise optical input Pin, a transistor 11 is turned on, the effective resistance value of a circuit inserted between an light stabilizing bielement 10 and a driving power source terminal 13 is rapidly reduced, the operating point of an element 10 in accordance with a load line (b) moves to B and the writing of an optical memory cell is completed. When a control pulse and the optical input Pin impressed to an input terminal 11a are removed, the transistor is turned off, the operating point moves from B to C on a load line (a), while the ON condition of the element 10 is maintained as it is, keeping a low operating current. In such a manner, the maintaining current of the optical memory can be lowered without deteriorating a memory characteristic, which is a large advantage for the integration of the optical memory.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a driving method for an optical memory cell used as a basic element of an optical combinator, optical exchange, etc.

(Prior art and its problems) Bistable semiconductor lasers that utilize the supersaturation absorption characteristics of semiconductors and bistable light emitting devices that utilize the turn-on characteristics of pnP (thyristor) structures are used as optical memories. Conventionally, thyristor In an optical memory using a bistable light emitting device, the current vs. voltage characteristic shown in Figure 2 was obtained by simply connecting an optical memory cell and a resistor in series and connecting it to a driving power source (Applied Physics Vol. 53, Vol. No. 5, pages 427-4
page 31). For example, when using an optical memory cell with the characteristics shown in FIGS. 2 and 3, when the drive power supply voltage is 5.5V,
When used with a 0Ω resistor inserted, this optical memory cell can write information with an optical input of approximately 20 μW, and then retains a current of approximately 25 mA even when the optical input is removed, and writes approximately 290 μW of current. Maintains optical output status. However, it is desired that K of this holding current be as small as possible for the purpose of integrating optical memories. To this end, in conventional examples, measures have been taken such as increasing the insertion resistance value. For example, in the above example, if the resistance value is increased from 20Ω to 200Ω, the holding current value will change from 25 mA to 9
It can be reduced to about mA.

However, as shown in FIG. 2, this conventional technique has the disadvantage that the reduction in holding current leads to a decrease in writing sensitivity and a decrease in readout light output.

(Object of the Invention) An object of the present invention is to provide a driving method for an optical memory cell that eliminates the above-mentioned drawbacks, enables reduction in power consumption for optical memory cells, and facilitates integration.

(Structure of the Invention) According to the present invention, in a driving method of an optical memory cell in which a basic memory cell is an optical bistable element having a thyristor type current-to-voltage hysteresis characteristic, an optical bistable element having a thyristor-type current-to-voltage hysteresis characteristic is inserted between the optical memory cell and a driving power source. A method for driving an optical memory cell is obtained, which is characterized in that the effective resistance value of the circuit is lowered during memory access.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a first embodiment based on the present invention. This example is an optical bistable element having the thyristor-type current vs. voltage characteristics and optical output vs. current characteristics shown in FIGS. 2 and 3! IKΩ connected to 0 and its p-side electrode 6
The circuit is composed of a resistor 12 and a resistor 11. The n-side electrode 7 of the optical bistable element 10 is grounded, and the drive power terminal 13 on the collector side of the transistor 11 has a voltage of 5.5
v is applied. Optical input pin for memory writing
is inputted from the light receiving window 7W provided on the n electrodes 7, and the optical output Pout at the time of memory reading is outputted from the light emitting window 6W provided on the p side electrode 8. The input/output light wavelength of the optical memory is 13 μm. The optical bistable device 10 used has the most basic configuration and is made of 'p-InGaA' epitaxially grown on a substrate 1' made of n-InP.
A light-receiving layer 2 made of sP (absorption edge wavelength 1.35 am), a confinement layer 3 made of n-InP, and n-InGa.
Light-emitting layer 4p-I consisting of A-P (emission wavelength 1.3 μm)
This is the structure of the confinement layer 5 made of nP.

In this embodiment, writing and reading of the optical memory cell are performed in the following steps. When writing, first piI
The optical memory cell is reset by grounding the ll electrode 6 or temporarily setting the drive power supply terminal 13 to zero potential. Next, an optical input Pin of 20 μW or more is applied in a pulsed manner, and at the same time, a control pulse signal of 5 V or more is applied to the input terminal 11'a on the pace side of the transistor 110. At this time, the transistor 11 is turned on, and the effective resistance value of the circuit inserted between the optical bistable element 10 and the drive power supply terminal 13 rapidly decreases, and the optical bistable element is turned on according to the load line shown in FIG. At the operating point No. 10, BK transition occurs and writing of the optical memory cell is completed. When the control pulse signal applied to the input terminal 11-a and the optical input P1n are removed, the transistor 1
1 is in the OFF state, and the operating point shifts from B to C on the load line a, but the ON state of the optical bistable element 100 is maintained until t even though the operating current is low. Note that when the optical input Pin during writing is zero, the operating point of the optical bistable element 10 is the second
Although it temporarily moves from point A to point A' in the figure, it returns to point A at the same time as the control pulse signal is removed, and the Zion state is maintained, that is, "0" is written.

To read, it is sufficient to simply apply a control pulse signal of 5V or more to the input terminal 14m. When the optical bistable element 10 is in the on state, that is, when "1" is written, the control pulse signal moves the optical bistable element 10 from the operating point C to the operating point B shown in FIG. Output. On the other hand, when the optical bistable element lO is in the off state, that is, when "O" is written, the operating point moves from A to A' by the control pulse signal, but the current remains at a low level and the optical output is rarely occurs.

FIG. 4 is a circuit diagram showing the configuration of the second embodiment. In this embodiment, a circuit inserted between the optical bistable element 10, which is an optical memory cell, and the drive power source is provided on the ground side of the optical bistable element 10, and the inserted circuit is connected to the switching transistor 11. It consists of resistors 12m and 12b. The 12m resistor works as a current limiter and the resistance value is 50m.
Ω, and the resistor 12b is for memory holding current bias and has a resistance value of IKΩ. In this embodiment, when accessing, the input terminal 11
Apply a positive pulse to m to make transistor 11 conductive.

FIG. 5 is a circuit diagram showing the configuration of the third embodiment. The resistors 12m and 12b in this embodiment also perform the same function as in the second embodiment. They are 50Ω and IKΩ, respectively. Input terminal 11& is for access signal, input terminal 11b
is for the reset signal.

The resistors connected to the optical bistable element 10 are switched by transistors 11 and 14. In this embodiment, the transistor 11 is turned on during access, and the transistor 14 is turned on in the hold state. Also transistor 11.1
The original memory cell can be reset by turning off both of 4 and 4. That is, the input terminals 11a, ll
The optical bistable element 10 is reset by setting the voltage applied to b to zero.

FIG. 6 is a circuit diagram showing the configuration of the fourth embodiment. In this embodiment, a field effect transistor 15 having variable resistance characteristics is used in the inserted circuit. At the time of memory access, a positive pulse signal is applied to the input terminal 11m to bring the field effect transistor 15 into a low resistance conduction state, and in the holding state, it is biased to such an extent that a required holding current can be obtained. Resetting can be performed by applying a pulse input such that the voltage at the input terminal 11m becomes equal to or lower than the pinch-off voltage of the field effect transistor 5.

Now, in all of the above embodiments, the optical memory cell is pnp.
Although the optical bistable element is described as having an n-structure, the present invention is not limited to this as long as it has a thyristor-type current-voltage hysteresis characteristic as shown in FIG.

(Effects of the Invention) To summarize the effects obtained by the present invention, it is possible to reduce the holding current of an optical memory without deteriorating the memory characteristics, which is a great advantage for the integration of optical memories. Additionally, it also has the effect of suppressing unnecessary light emission from the optical memory, and contributes to reducing bit-to-bit interference, which is a problem with integration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment based on the present invention. 3 is a characteristic diagram of an optical bistable element and a configuration diagram of a fourth embodiment. In the figure, IO is an optical bistable element, and 13 is a drive power supply terminal. E 1 Figure □ 1 Optical input O 2 Figure Current between voltages (mA) Figure 74 ″:A-5 Figure 71-Drawing

Claims (1)

[Claims] In a drive method for an optical memory cell whose basic memory cell is an optical bistable element having thyristor-type current-to-voltage hysteresis characteristics, the effective resistance value of the circuit inserted between the optical memory cell and the drive power source is reduced during memory access. A driving method for an optical memory cell, which is characterized by: