JPS61148956A - Read circuit of plural sensor signals - Google Patents

Abstract

PURPOSE:To simplify a scanning circuit by selecting two sensors in time series in one cycle of a clock. CONSTITUTION:When a selection pulse S1 is selected, since a photodiode 6 corresponding to the pulse S1 is charged again in response to the stored exposure, the pulse is extracted as an output. in this case, a light current exposed at present in the photodeiode 6 corresponding to the pulse S1 is extracted also. When selection pulses S1, S2 are selected, the recharging of the photodiode 6 corresponding to the pulse S1 is finished. Since the recharging corresponding to the exposure stored in the photodiode 6 corresponding to the pulse S2 is executed, it is extracted as an output. The light current for the exposure at present in the photodiode 6 corresponding to the pulses S1, S2 is extracted together in this case.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal output circuit for an integrated sensor in which a plurality of sensors are commonly connected by a group of matrix (line) switches. Let me explain with an example.

[Conventional technology]

Conventional Example 1 A conventional multiple sensor signal readout circuit is disclosed in Japanese Patent Application Laid-open No. 5959-1.
A running i-circuit as shown in FIG. 10750 and FIG. 5 IC was used. The selection signal of the sensor is synchronized with the AFF1 phase clock, and the selection pulse width is less than one cycle of the clock.

Conventional example 2 The conventional optical line sensor is the t.
, Z, S, the COD chips are arranged in a staggered pattern K.
Conventional example 5 was a system in which several m number of optical line sensors were arranged and an optical image was formed using a focusing rod lens array.
The device shown in the figure used an optical system in which images were formed using a converging rod lens array, and the sensor array (photodiode array) consisted of one chip, and the scanning circuit consisted of one or more chips of hybrid integrated circuits.

[Problem that the invention seeks to solve]

A close-contact image sensor is constructed as shown in Conventional Example 2.5. The problem with the close-contact type is that the sensor length is long. Therefore, it is composed of multiple chips,
Alternatively, the sensor array could be configured with a single chip and the scanning circuit could be configured with multiple chips, which would of course be costly, so the "Nikkei Electronics 1984-9-2J
12! shown on p128-Pt29J! l) A scanning f circuit and a photodiode play are integrated on the same substrate for a contact type one-dimensional sensor. When integrated on the same substrate, the cost can be reduced as the number of elements on a chip is smaller. Therefore, it is necessary to simplify the scanning circuit in the conventional example 1 as well.

[Means for solving problems]

The multiple sensor signal readout circuit of the present invention is characterized by having a scanning means that always selects two adjacent sensors and sequentially reads two sensors in one clock cycle.

□ [Operation] Since the scanning means of the present invention selects two sensors in time series in one cycle of the clock, it is possible to select and control two sensors using a conventional shift register that only has one sensor. Since two adjacent sensors are always selected, there is no need to gate the output of the 7-foot register.

〔Example〕

Figure 1 shows the circuit configuration of the multiple sensor signal reading circuit of the present invention, and Figure 2 is a diagram for explaining its operation. In order to avoid complication of explanation, only the circuit configuration is shown as a 5-element line sensor, and the timing generator is omitted.

In Figure 3, the scanning circuit 101 is composed of an inverter 1 and a clocked gate converter 2.5, and its operation is as shown in Figure 2.
When L is applied, one clock period is added to the half period of the clock.
Generates a time-series pulse (see 8t*St6days) with a width equal to a period.

The photodiode array 102 is composed of an analog switch 5 and a photodiode 6 (or a photoconductive capacitor).The photodiode 6 performs an accumulation operation. That is, the voltage across the photodiode 6 is initially charged to the sensor bar 1 as voltage vgi+. After being exposed to light, the electric charge is discharged.For reading purposes, a certain analog switch 5 selected by the scanning circuit 101 is turned on (5j!, when the clock is half a cycle). (The previously selected analog switch 5 is also on.) Then, the corresponding photodiode 6 receives a voltage v8B.
is applied, a recharging current Io flows into the preamplifier 103, and a signal is extracted to the outside using this.

Preamplifier 105 includes resistor R1*R1 and operational amplifier 7
It consists of an inverting current-voltage conversion system and has a smooth operation.

The integrator 104 is a resistor Rfi + capacitor CIm operational amplifier 8. and an analog switch 10 to form an inverting integrator, and a reset pulse R11? The waveform shown in FIG. 2 is applied to reset the charge on the capacitor C1. The sample holder 105 samples and holds the sample by applying the sample hold pulse 8B shown in FIG.

In FIG. 2, the recharge current generator 0 includes a signal charge qe+ and a noise charge Qm. The noise charge QN is generated by the coupling of the clock CT,+ to the photodiode array 102 through a stray parasitic capacitor, and the noise charge Q,If is of positive and negative polarity, respectively, in the recharging process 0.
are symmetrical, and the amount of coupling is determined by modularizing the scanning circuit 10s1, the photodiode array 102, and the preamplifier ta5 (for example, by making the hybrid circuit 10s1 into a monolift circuit, and by making the hybrid circuit into each block).
can.

In FIG. 2, the waveform of the recharge current generator 0 is schematically expressed for the convenience of explanation, that is, the signal charge QB and the noise charge QN are shown separated in time. In reality, since the time constants are close to each other, the waveforms are not separated in time series.The operation when the clock signal is not suppressed is shown by the integral waveform Vc' and the output waveform vo' in FIG. , it is clear from FIG. 2 that the clock cb is superimposed on both the outputs when the photodiode 6 is not selected and when the same amount of light is incident on each photodiode. .

Therefore, analog switches tt, tz, inno(-
15, variable voltage source VOL, capacitor C1, resistor R4
A clock suppression circuit 106 is used.

Analog switch to which clock 0'L is input %1゜1
2. The inverter 15 and the variable voltage source VOL constitute a square wave generator that is in phase with the clock (L) and whose amplitude is variable. The amount of suppression of the clock Or,+ is determined by the variable voltage source vO- and the capacitor C3. By adjusting the size and C4 and setting both values large, the amount of F injection increases.Resistor R4 is added to prevent a steep waveform from being applied to the integrator, and the fixed pattern is the product of capacitor C2 and resistor R6. It is set to be proportional to the time constant, and also to have a time constant equal to the recharge current factor 0.

Further, since the preamplifier is an inverting amplifier, in order to suppress the clock OL, a compensation signal in phase with the clock OL may be used when inputting from the integrator as shown in FIG. Similarly, when compensating by injecting from the input terminal of the preamplifier 1050, a signal with the opposite phase to the clock OL is required, and since it is suppressed before being amplified, it is necessary to inject a small compensation signal.

The operation when using the clock suppression circuit 106 is shown in the integral waveform Va and the output waveform VoK in Figure @2. Integrator 1
Since 04 is used, there is no need to compensate with the same waveform as the noise charges Q, II. , Therefore, the waveform response of the integral waveform Vc is disordered, but the output waveform vO obtained by sampling and holding it suppresses the clock CL. The problem with this circuit is the stability of the capacitive coupling between the clock OL and the photodiode array-02, but if the configuration is electrically and mechanically stable, the only problem will be the temperature characteristics, and the variable voltage source vob
If K has the same temperature characteristics, a clock suppression effect with considerable temperature stability can be obtained.

Since the present invention has a moving means that always selects two adjacent sensors, its operation will be explained. In FIG. 1.2, when the selection pulse S is in the selected state, the photodiode 6 corresponding to %"1 is recharged according to the accumulated study exposure amount and is taken out as an output. ．．
The photocurrent currently exposed to the photodiode 6 corresponding to 8 is also taken out. Then, when the selection pulses s, Is, enter the selected state, the photodiode 6 corresponding to 8 completes recharging.

ing. Then, the photodiode 6 corresponding to S is recharged according to the amount of exposure accumulated in the photodiode 6, so that it is output as an output. At this time, the photocurrent currently being exposed to the photodiode 6 corresponding to the BLE day is also taken out. In this process, the unaccumulated outputs of the sensors selected 17 times appear as errors, but since they are adjacent bits, the information is correlated. 171,000 or less), exposure can be stopped after successive cycles, etc., so this is not a big problem. [Effect] As described above, according to the present invention, the scanning circuit can be simplified. This is because a 1-pit sensor can be driven by a shift register, which is a normal half-pit, and it can be configured with only a shift register and a buffer inverter. The simplification of the scanning circuit is one of the reasons why the one-chip type contact image sensor (Ill. ``Nikkei Electronics 19
84-9-24'? 128 to F 129 J) and the number of elements can be reduced. As a result, costs are reduced. Furthermore, the simplicity of the scanning circuit also leads to an improvement in operating speed.

As described above, the present invention is particularly effective in reducing the cost and increasing the speed of a one-chip contact type image sensor.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a multiple sensor signal readout circuit according to the present invention. The faz diagram is a rhythm diagram of a circuit for successively generating multiple sensor signals according to the present invention. OL beam a-tsuku, 6 is sensor (photodiode) 101
is a scanning circuit % 102 is a sensor array (photodiode array), 105 is a pre-up, 104 is an integrator, 106
is a clock suppression circuit. that's all

Claims (2)

[Claims] (1) A multi-sensor signal reading circuit that reads two sensors out of a plurality of sensors in time series in one clock cycle is characterized by having a scanning means that always selects two adjacent sensors. Multiple sensor signal readout circuit. (2) the scanning means uses respective master and slave outputs of a master-slave type shift register;
The multiple sensor signal readout circuit according to claim 1, wherein the sensor array and the scanning means are integrated on the same substrate.