JPS61148899A - Manufacture of substrate for circuit - Google Patents

Manufacture of substrate for circuit

Info

Publication number
JPS61148899A
JPS61148899A JP27142584A JP27142584A JPS61148899A JP S61148899 A JPS61148899 A JP S61148899A JP 27142584 A JP27142584 A JP 27142584A JP 27142584 A JP27142584 A JP 27142584A JP S61148899 A JPS61148899 A JP S61148899A
Authority
JP
Japan
Prior art keywords
electrodeposition
manufacturing
core plate
electrodeposited
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27142584A
Other languages
Japanese (ja)
Inventor
千葉 公夫
光司 大川
秀明 白井
広瀬 道夫
吉岡 道彦
石井 昭弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dainichi Nippon Cables Ltd
Original Assignee
Dainichi Nippon Cables Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dainichi Nippon Cables Ltd filed Critical Dainichi Nippon Cables Ltd
Priority to JP27142584A priority Critical patent/JPS61148899A/en
Priority to US06/759,210 priority patent/US4695515A/en
Priority to US06/759,209 priority patent/US4767674A/en
Priority to CA000487695A priority patent/CA1232971A/en
Priority to CA000487703A priority patent/CA1240072A/en
Priority to CA000487694A priority patent/CA1225462A/en
Publication of JPS61148899A publication Critical patent/JPS61148899A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electroplating Methods And Accessories (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔利 用 分 野〕 本発明性、ヒートシンク材や磁気at材などとして機能
する金属芯板と導電性金属箔との間に電気絶縁警を有す
る構造の回路用基板の新規な製造法に関する。
[Detailed Description of the Invention] [Field of Use] The present invention relates to a circuit board having an electrical insulation layer between a metal core plate and a conductive metal foil, which function as a heat sink material, a magnetic AT material, etc. Concerning new manufacturing methods.

〔従来の技術〕[Conventional technology]

近時における電子機器の軽量小形化に伴い、上記構造の
回路用基板として耐電圧特性の一層優れなものが要求さ
れている。
As electronic devices have become lighter and smaller in recent years, circuit boards having the above-mentioned structure are required to have even better withstand voltage characteristics.

従来、その回路用基板はヂリイミドなどの耐熱性及び電
気絶縁性に優れた有機高分子のフィルムを、金属芯板と
導電性金属箔との間に介在接着させる方法で製造されて
いる。
Conventionally, circuit boards have been manufactured by interposing and adhering a film of an organic polymer having excellent heat resistance and electrical insulation properties, such as diriimide, between a metal core plate and a conductive metal foil.

〔解決すべき問題点〕[Problems to be solved]

ところで、市販の有機高分子フィルムは所々にピンホー
〃を有するのでこのピンホール部分を有するフィVムを
絶縁1として有する基板は電気特性が真常に低い。別記
すると、従来品は耐電圧i性の面で品質にバラツキがあ
り信来性に劣るものであったつ そこで、本発明者らは鋭意研究の結果、水溶性又は水分
散性の電着ワニスを用いて電着塗装してなる電着膜1/
1k111が安定した耐電圧特性を有してお9、回路用
基板の電気絶縁−として好適であることを見出し喪。
By the way, since commercially available organic polymer films have pinholes in some places, a substrate having a film having pinholes as the insulator 1 has extremely low electrical characteristics. As a separate note, the quality of conventional products varied in terms of voltage resistance and was inferior in reliability.As a result of intensive research, the present inventors developed a water-soluble or water-dispersible electrodeposited varnish. Electrodeposited film 1/
It was discovered that 1k111 has stable voltage resistance characteristics9 and is suitable as electrical insulation for circuit boards.

しかしながら、電着絶縁1は一般に耐剥離強度が乏しく
、回路の半田付けの際の加熱により剥離すること;4る
という問題を有していた。
However, the electrodeposited insulation 1 generally has a problem of poor peeling strength and peeling due to heating during circuit soldering.

〔問題点の解決手段〕[Means for solving problems]

本発明は、耐電圧特性、耐剥−性の優れた回路用基板の
新規な製造法を提供する。ことを目的とするものである
The present invention provides a novel method for manufacturing a circuit board with excellent voltage resistance and peeling resistance. The purpose is to

すなわち、本発明の回路用基板の製造法は、金属芯板又
は/及び導電性金属箔に電着方式による電気絶縁層を設
け、次いで該電気絶#譬を介して金属芯板と導電性金属
箔とを接着して回路用基板を製造するに際し、前記の電
着処理に先立って電着処理場れる金属表面を機械的に粗
面化することを粗面化するものである。
That is, the method for manufacturing a circuit board of the present invention includes providing an electrically insulating layer on a metal core plate and/or a conductive metal foil by electrodeposition, and then bonding the metal core plate and the conductive metal via the electrical insulation layer. When a circuit board is manufactured by adhering a foil, the metal surface is mechanically roughened in an electrodeposition treatment field prior to the electrodeposition treatment described above.

本発明において金属芯板としてはアVミニウム、鋼など
の熱導電性の良好な金属からなるヒートシンク用の板、
鉄、ケイ素鋼、ステンレスなどの鉄系材のような磁性金
属からなる磁気遮蔽−の板などが用いられる。被電着体
がアvミニウム板の場合、一般にアVミニウムは電着さ
れ難−ので電着処理に先立ってその表面に銅、エフケル
1亜鉛など特に銅をメッキしておくことが望ましい。被
電゛ 着体がケイ素鋼板である場合、市販のケイ素鋼板
には両面に防錆剤が塗布されているので苛性アルカリ水
溶液などでそれを剥離竺去することが望ましい。導電性
金属箔としては銅、ニッケVなどの良導電性の金属箔が
用いられる。
In the present invention, the metal core plate is a heat sink plate made of a metal with good thermal conductivity such as AV aluminum or steel;
A magnetic shielding plate made of a magnetic metal such as iron, silicon steel, stainless steel, or other iron-based material is used. When the object to be electrodeposited is an AV aluminium plate, it is generally difficult to electrodeposit AV aluminium, so it is desirable to plate the surface with copper, especially copper such as F-Cl 1 zinc, prior to the electrodeposition process. When the electrified object is a silicon steel plate, since commercially available silicon steel plates are coated with a rust preventive agent on both sides, it is desirable to remove the rust preventive agent using a caustic aqueous solution or the like. As the conductive metal foil, a highly conductive metal foil such as copper or nickel V is used.

本発明においては金属芯板に電着処理を施し、形成され
た電着膜を介して金属芯板と導電性金属箔とを接着して
もよいし、その逆であってもよい。
In the present invention, the metal core plate may be subjected to electrodeposition treatment, and the metal core plate and the conductive metal foil may be bonded together via the formed electrodeposited film, or vice versa.

また、更に金属芯板と導電性金属箔の双方に電着処理を
施し、形成された電着1同士を接着するもよい。
Furthermore, both the metal core plate and the conductive metal foil may be subjected to electrodeposition treatment, and the formed electrodepositions 1 may be adhered to each other.

いずれにせよ本発明では電着される金属面は予め機械的
方法にて粗面化される。この粗面化は、六とえば研磨ロ
ールや研磨シートを用いて行うことができる。これらの
手段で粗面化され虎金属表rNK111着処理を施すこ
とにより、耐剥離性の優れた電慶絶#智を形成すること
ができる。一般に、粗面化が軽度であると形成される電
着膜の耐剥離性の改善が不充分であり、一方粗面化が過
度に行われると金属表面の突起が電界集中作用をなして
電歎絶縁智の耐電圧強度を低下せしめることとなる。こ
の六め、研磨粗さ200〜t、o o o番手、特に8
00〜800番手の上記手段により粗面加工することが
望ましい。
In any case, in the present invention, the metal surface to be electrodeposited is roughened in advance by a mechanical method. This surface roughening can be performed using, for example, a polishing roll or a polishing sheet. By roughening the surface using these methods and subjecting it to the NK111 adhesion treatment, it is possible to form Denkei Zetsu#chi which has excellent peeling resistance. In general, if the surface is lightly roughened, the peeling resistance of the electrodeposited film will not be improved sufficiently, while if the surface is excessively roughened, the protrusions on the metal surface will concentrate the electric field. This will reduce the withstand voltage strength of the insulation. This sixth, polishing roughness 200~t, o o o count, especially 8
It is desirable to roughen the surface by the above-mentioned method using a number of 00 to 800.

粗面化された金属表面への電着処理は通常の方式で行っ
てよく、電着ワニスとしては喪とえばマグネットワイヤ
の製造に用いられているもの、その例を挙げるとアクリ
ル系ワニス、エポキシ−アク13 kl系ワニスなどが
好適であり、また−1耐電圧特性の優れた電着膜とする
ために焼付けに先立って電着1を100〜700℃の高
温水蒸気や常温〜高温たとえば200℃のジメチVホV
ムアミドなどの親水性溶媒で処理することが望ましい。
Electrodeposition treatment on roughened metal surfaces may be carried out by the usual method, and electrodeposition varnishes such as those used in the manufacture of magnet wires, such as acrylic varnishes and epoxy -Ak 13kl-based varnish is suitable, and in order to obtain an electrodeposited film with excellent voltage resistance, the electrodeposition 1 may be heated with high-temperature steam at 100 to 700°C or room temperature to high temperature, such as 200°C, before baking. Dimechi V Ho V
It is desirable to treat with a hydrophilic solvent such as Muamide.

□ 〔発明の効果〕 本発明によれば耐電圧特性、耐剥離性の安定し大回路用
基板の製造が可能となるので、本発明は電子、電気機器
の−1の軽量小形化を推進するうえで−る有用である。
□ [Effects of the Invention] According to the present invention, it is possible to manufacture a large circuit board with stable voltage resistance and peeling resistance, so the present invention promotes -1 lighter weight and smaller size of electronic and electrical equipment. It is very useful.

〔実施例、比較例〕[Example, comparative example]

実施例1 鋼メフキアVミニウム板(厚さ0.8MM)の銅メッキ
面を500番手のサンドペーパーで一様に研磨して粗面
化したのち、片面に塩化ビニル粘着シートを1着してマ
スク処理し、この鋼めっきアルミニラム板の非マスク銅
めっき面を陽極としてエポキシ−アクリル水分散ワニス
(菱電化成社成、V−551−20,ワニス濃度20重
196)を用い、ワニス温度80℃、課電条件7.5 
mAIcd、7秒間及び電極間距離80fiの条件で電
着処理し、電着1を形成させた。次に、この電着嚇を有
するアルミニウム板を80℃のN、N−ジメチルホルム
アミドに10秒間浸漬して電着Wを処理したのちアルミ
ニウム板の片面に設けたマスクシートを剥離除去し、こ
れを150℃で40分間加熱して電着−を1次キエアさ
せた。
Example 1 After uniformly polishing the copper-plated surface of a steel Mefkia V minium plate (thickness 0.8 mm) with 500-grit sandpaper to make it rough, one side was covered with a vinyl chloride adhesive sheet to form a mask. Using epoxy-acrylic water dispersion varnish (manufactured by Ryoden Kasei Co., Ltd., V-551-20, varnish concentration 20 weight 196) with the non-mask copper-plated surface of this steel-plated aluminum plate as an anode, the varnish temperature was 80°C. Charging conditions 7.5
Electrodeposition was performed under the conditions of mAIcd, 7 seconds, and an interelectrode distance of 80fi to form electrodeposition 1. Next, the aluminum plate with this electrodeposition was immersed in N,N-dimethylformamide at 80°C for 10 seconds to treat the electrodeposition W, and then the mask sheet provided on one side of the aluminum plate was peeled off and removed. The electrodeposition was heated for 40 minutes at 150 DEG C. for the first time.

ついで、1次キエアさせた電着@(厚さ40μm)の上
に接着剤(米国デュポン社製、パイフラックス、LF−
0100、厚さ25pm)を塗布し、これを介して厚さ
85μmO銅箔を200℃、40分間、20#/dの条
件で熱プレス処理して接着することによりアルミニウム
ヒートシンク付回路用基板を得た。
Next, an adhesive (Pyflux, LF-, manufactured by DuPont, USA) was applied on the primary air-deposited electrodeposited @ (thickness: 40 μm).
0100, thickness 25 pm), and then heat-pressed an 85 μm O copper foil at 200° C. for 40 minutes at 20 #/d to obtain a circuit board with an aluminum heat sink. Ta.

実施例2 アルミニウム板に代えて表面の防錆層が除去されたケイ
素鋼板(厚さQ、51EI)を用いた点のみ実施例1と
異なる方法、条件にてケイ素鋼板付回路用基板を得た。
Example 2 A circuit board with a silicon steel plate was obtained using a method and conditions different from Example 1 except that a silicon steel plate (thickness Q, 51EI) from which the surface anti-corrosion layer had been removed was used instead of the aluminum plate. .

比較例1,2 研磨を行わすに電着した点においてのみそれぞれ実施例
1又は2と異る方法で回路用基板の製造を行った。
Comparative Examples 1 and 2 Circuit boards were manufactured using a method different from Example 1 or 2, respectively, only in that electrodeposition was performed before polishing.

〔評 価 試 験〕〔Evaluation test〕

実施例1.2並びに比較例1,2で得た回路用基板の2
60℃、60分間の加熱処理の前後における金属芯板と
電気絶縁響とのTピール剥離費度を測定した。結果を表
に示した。
2 of the circuit boards obtained in Example 1.2 and Comparative Examples 1 and 2
The peeling cost of the T-peel between the metal core plate and the electrical insulation board was measured before and after heat treatment at 60° C. for 60 minutes. The results are shown in the table.

Claims (1)

【特許請求の範囲】 1、金属芯板又は/及び導電性金属箔に電着方式により
電気絶縁層を設け、次いで該電気絶縁層を介して金属芯
板と導電性金属箔とを接着して回路用基板を製造するに
際し、前記の電着処理に先立って電着処理される金属表
面を機械的に粗面化することを特徴とする回路用基板の
製造法。 2、金属芯板が銅メッキアルミニウム板であり銅メッキ
表面を機械的に粗面化して電着処理する特許請求の範囲
第1項記載の製造法。 3、金属芯板がケイ素鋼板、鉄板、ステンレス板からな
る鉄系板より選ばれた一種であり、該鉄系板の少なくと
も片面に電着処理を施す特許請求の範囲第1項記載の製
造法。 4、導電性金属箔として銅箔を用い、該銅箔に電着処理
を施す特許請求の範囲第1項記載の製造法。 5、研磨粗さ200〜1,000番手の研磨ロール又は
研磨シートで電着処理すべき表面を粗面化する特許請求
の範囲第1〜4項記載の製造法。
[Claims] 1. An electrically insulating layer is provided on a metal core plate and/or a conductive metal foil by electrodeposition, and then the metal core plate and the conductive metal foil are bonded via the electrically insulating layer. A method for manufacturing a circuit board, which comprises mechanically roughening the surface of the metal to be electrodeposited prior to the electrodeposition process. 2. The manufacturing method according to claim 1, wherein the metal core plate is a copper-plated aluminum plate, and the copper-plated surface is mechanically roughened and electrodeposited. 3. The manufacturing method according to claim 1, wherein the metal core plate is one selected from iron-based plates such as silicon steel plates, iron plates, and stainless steel plates, and at least one side of the iron-based plate is subjected to electrodeposition treatment. . 4. The manufacturing method according to claim 1, wherein a copper foil is used as the conductive metal foil, and the copper foil is subjected to an electrodeposition treatment. 5. The manufacturing method according to claims 1 to 4, wherein the surface to be electrodeposited is roughened with a polishing roll or a polishing sheet having a polishing roughness of 200 to 1,000.
JP27142584A 1984-01-27 1984-12-22 Manufacture of substrate for circuit Pending JPS61148899A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP27142584A JPS61148899A (en) 1984-12-22 1984-12-22 Manufacture of substrate for circuit
US06/759,210 US4695515A (en) 1984-07-30 1985-07-26 Metal cored board and method for manufacturing same
US06/759,209 US4767674A (en) 1984-01-27 1985-07-26 Metal cored board and method for manufacturing same
CA000487695A CA1232971A (en) 1984-07-30 1985-07-29 Metal cored board and method for manufacturing same
CA000487703A CA1240072A (en) 1984-07-30 1985-07-29 Metal cored circuit board with baked-on polymer layer
CA000487694A CA1225462A (en) 1984-07-30 1985-07-29 Aluminium cored board and method for manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27142584A JPS61148899A (en) 1984-12-22 1984-12-22 Manufacture of substrate for circuit

Publications (1)

Publication Number Publication Date
JPS61148899A true JPS61148899A (en) 1986-07-07

Family

ID=17499852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27142584A Pending JPS61148899A (en) 1984-01-27 1984-12-22 Manufacture of substrate for circuit

Country Status (1)

Country Link
JP (1) JPS61148899A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292820A (en) * 1985-06-11 1986-12-23 三菱電線工業株式会社 Manufacture of organic high polymer covered metal body
JPH01165672U (en) * 1988-05-12 1989-11-20

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292820A (en) * 1985-06-11 1986-12-23 三菱電線工業株式会社 Manufacture of organic high polymer covered metal body
JPH01165672U (en) * 1988-05-12 1989-11-20

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